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Prims.Tot

val eval_VShufpd (permutation: int) (src1 src2: quad32) : option quad32

let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2)

val eval_VShufpd (permutation: int) (src1 src2: quad32) : option quad32 let eval_VShufpd (permutation: int) (src1 src2: quad32) : option quad32 =

check_avx (eval_Shufpd_raw permutation src1 src2)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation)

Vale.X64.Instructions_s.fsti

val eval_VShufpd (permutation: int) (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_VShufpd

permutation: Prims.int -> src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Pxor (dst src: quad32) : option quad32

let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src))

val eval_Pxor (dst src: quad32) : option quad32 let eval_Pxor (dst src: quad32) : option quad32 =

check_sse2 (Some (quad32_xor dst src))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu

Vale.X64.Instructions_s.fsti

val eval_Pxor (dst src: quad32) : option quad32

Vale.X64.Instructions_s.eval_Pxor

dst: Vale.X64.Machine_s.quad32 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_VPslldq (count: nat8) (src: quad32) : option quad32

let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src)

val eval_VPslldq (count: nat8) (src: quad32) : option quad32 let eval_VPslldq (count: nat8) (src: quad32) : option quad32 =

check_avx (eval_Pslldq_raw count src)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1)

Vale.X64.Instructions_s.fsti

val eval_VPslldq (count: nat8) (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_VPslldq

count: Vale.Def.Types_s.nat8 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val is_full_byte_reversal_mask (q: quad32) : bool

let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203

val is_full_byte_reversal_mask (q: quad32) : bool let is_full_byte_reversal_mask (q: quad32) : bool =

q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation)

Vale.X64.Instructions_s.fsti

val is_full_byte_reversal_mask (q: quad32) : bool

Vale.X64.Instructions_s.is_full_byte_reversal_mask

q: Vale.X64.Machine_s.quad32 -> Prims.bool

Prims.Tot

val eval_Comment:option unit

let eval_Comment : option unit = Some ()

val eval_Comment:option unit let eval_Comment:option unit =

Some ()

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2 let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None val ins_SHA256_msg1 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg1 let eval_SHA256_msg2 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg2_spec src1 src2) else None val ins_SHA256_msg2 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg2 let eval_Ghost : option unit = Some () val ins_Ghost : instr_dep [] [] PreserveFlags eval_Ghost

Vale.X64.Instructions_s.fsti

val eval_Comment:option unit

Vale.X64.Instructions_s.eval_Comment

FStar.Pervasives.Native.option Prims.unit

Prims.Tot

val eval_VAESNI_enc_last (src1 src2: quad32) : option quad32

let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2)

val eval_VAESNI_enc_last (src1 src2: quad32) : option quad32 let eval_VAESNI_enc_last (src1 src2: quad32) : option quad32 =

check_avx (eval_AESNI_enc_last src1 src2)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last

Vale.X64.Instructions_s.fsti

val eval_VAESNI_enc_last (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_VAESNI_enc_last

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Bswap64 (dst: nat64) : option nat64

let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst)

val eval_Bswap64 (dst: nat64) : option nat64 let eval_Bswap64 (dst: nat64) : option nat64 =

Some (reverse_bytes_nat64 dst)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64

Vale.X64.Instructions_s.fsti

val eval_Bswap64 (dst: nat64) : option nat64

Vale.X64.Instructions_s.eval_Bswap64

dst: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.nat64

Prims.Tot

val eval_Psrldq_8_raw (count: nat8) (src: quad32) : option quad32

let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None

val eval_Psrldq_8_raw (count: nat8) (src: quad32) : option quad32 let eval_Psrldq_8_raw (count: nat8) (src: quad32) : option quad32 =

if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 =

Vale.X64.Instructions_s.fsti

val eval_Psrldq_8_raw (count: nat8) (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_Psrldq_8_raw

count: Vale.Def.Types_s.nat8 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_AESNI_imc (src: quad32) : option quad32

let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None

val eval_AESNI_imc (src: quad32) : option quad32 let eval_AESNI_imc (src: quad32) : option quad32 =

if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last

Vale.X64.Instructions_s.fsti

val eval_AESNI_imc (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_AESNI_imc

src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_AESNI_enc (src1 src2: quad32) : option quad32

let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None

val eval_AESNI_enc (src1 src2: quad32) : option quad32 let eval_AESNI_enc (src1 src2: quad32) : option quad32 =

if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm)

Vale.X64.Instructions_s.fsti

val eval_AESNI_enc (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_AESNI_enc

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_SHA256_msg1 (src1 src2: quad32) : option quad32

let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None

val eval_SHA256_msg1 (src1 src2: quad32) : option quad32 let eval_SHA256_msg1 (src1 src2: quad32) : option quad32 =

if sha_enabled then Some (sha256_msg1_spec src1 src2) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2

Vale.X64.Instructions_s.fsti

val eval_SHA256_msg1 (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_SHA256_msg1

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_VPsrldq (count: nat8) (src: quad32) : option quad32

let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src)

val eval_VPsrldq (count: nat8) (src: quad32) : option quad32 let eval_VPsrldq (count: nat8) (src: quad32) : option quad32 =

check_avx (eval_Psrldq_8_raw count src)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0)

Vale.X64.Instructions_s.fsti

val eval_VPsrldq (count: nat8) (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_VPsrldq

count: Vale.Def.Types_s.nat8 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val is_high_dup_reversal_mask (q: quad32) : bool

let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B

val is_high_dup_reversal_mask (q: quad32) : bool let is_high_dup_reversal_mask (q: quad32) : bool =

q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F

Vale.X64.Instructions_s.fsti

val is_high_dup_reversal_mask (q: quad32) : bool

Vale.X64.Instructions_s.is_high_dup_reversal_mask

q: Vale.X64.Machine_s.quad32 -> Prims.bool

Prims.Tot

val eval_Pshufb_raw (src1 src2: quad32) : option quad32

let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None

val eval_Pshufb_raw (src1 src2: quad32) : option quad32 let eval_Pshufb_raw (src1 src2: quad32) : option quad32 =

if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 =

Vale.X64.Instructions_s.fsti

val eval_Pshufb_raw (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_Pshufb_raw

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Space:option unit

let eval_Space : option unit = Some ()

val eval_Space:option unit let eval_Space:option unit =

Some ()

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2 let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None val ins_SHA256_msg1 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg1 let eval_SHA256_msg2 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg2_spec src1 src2) else None val ins_SHA256_msg2 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg2 let eval_Ghost : option unit = Some () val ins_Ghost : instr_dep [] [] PreserveFlags eval_Ghost let eval_Comment : option unit = Some () val ins_Comment (_:string) : instr_dep [] [] PreserveFlags eval_Comment let eval_LargeComment : option unit = Some () val ins_LargeComment (_:string) : instr_dep [] [] PreserveFlags eval_LargeComment let eval_Newline : option unit = Some () val ins_Newline : instr_dep [] [] PreserveFlags eval_Newline

Vale.X64.Instructions_s.fsti

val eval_Space:option unit

Vale.X64.Instructions_s.eval_Space

FStar.Pervasives.Native.option Prims.unit

Prims.Tot

val eval_AESNI_dec (dst src: quad32) : option quad32

let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None

val eval_AESNI_dec (dst src: quad32) : option quad32 let eval_AESNI_dec (dst src: quad32) : option quad32 =

if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last

Vale.X64.Instructions_s.fsti

val eval_AESNI_dec (dst src: quad32) : option quad32

Vale.X64.Instructions_s.eval_AESNI_dec

dst: Vale.X64.Machine_s.quad32 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Newline:option unit

let eval_Newline : option unit = Some ()

val eval_Newline:option unit let eval_Newline:option unit =

Some ()

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2 let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None val ins_SHA256_msg1 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg1 let eval_SHA256_msg2 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg2_spec src1 src2) else None val ins_SHA256_msg2 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg2 let eval_Ghost : option unit = Some () val ins_Ghost : instr_dep [] [] PreserveFlags eval_Ghost let eval_Comment : option unit = Some () val ins_Comment (_:string) : instr_dep [] [] PreserveFlags eval_Comment let eval_LargeComment : option unit = Some () val ins_LargeComment (_:string) : instr_dep [] [] PreserveFlags eval_LargeComment

Vale.X64.Instructions_s.fsti

val eval_Newline:option unit

Vale.X64.Instructions_s.eval_Newline

FStar.Pervasives.Native.option Prims.unit

Prims.Tot

val eval_SHA256_rnds2 (src1 src2 wk: quad32) : option quad32

let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None

val eval_SHA256_rnds2 (src1 src2 wk: quad32) : option quad32 let eval_SHA256_rnds2 (src1 src2 wk: quad32) : option quad32 =

if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm)

Vale.X64.Instructions_s.fsti

val eval_SHA256_rnds2 (src1 src2 wk: quad32) : option quad32

Vale.X64.Instructions_s.eval_SHA256_rnds2

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> wk: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val check_sse2 (#a: Type0) (x: option a) : option a

let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None

val check_sse2 (#a: Type0) (x: option a) : option a let check_sse2 (#a: Type0) (x: option a) : option a =

if sse2_enabled then x else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None

Vale.X64.Instructions_s.fsti

val check_sse2 (#a: Type0) (x: option a) : option a

Vale.X64.Instructions_s.check_sse2

x: FStar.Pervasives.Native.option a -> FStar.Pervasives.Native.option a

Prims.Tot

val eval_VPclmulqdq (imm: int) (src1 src2: quad32) : option quad32

let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2)

val eval_VPclmulqdq (imm: int) (src1 src2: quad32) : option quad32 let eval_VPclmulqdq (imm: int) (src1 src2: quad32) : option quad32 =

check_avx (eval_Pclmulqdq imm src1 src2)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm)

Vale.X64.Instructions_s.fsti

val eval_VPclmulqdq (imm: int) (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_VPclmulqdq

imm: Prims.int -> src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Shr64 (dst amt: nat64) : option nat64

let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None

val eval_Shr64 (dst amt: nat64) : option nat64 let eval_Shr64 (dst amt: nat64) : option nat64 =

if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64

Vale.X64.Instructions_s.fsti

val eval_Shr64 (dst amt: nat64) : option nat64

Vale.X64.Instructions_s.eval_Shr64

dst: Vale.X64.Machine_s.nat64 -> amt: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.nat64

Prims.Tot

val eval_Cpuid (rax rcx: nat64) : option (nat64 & (nat64 & (nat64 & nat64)))

let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx)))

val eval_Cpuid (rax rcx: nat64) : option (nat64 & (nat64 & (nat64 & nat64))) let eval_Cpuid (rax rcx: nat64) : option (nat64 & (nat64 & (nat64 & nat64))) =

Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx)))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64

Vale.X64.Instructions_s.fsti

val eval_Cpuid (rax rcx: nat64) : option (nat64 & (nat64 & (nat64 & nat64)))

Vale.X64.Instructions_s.eval_Cpuid

rax: Vale.X64.Machine_s.nat64 -> rcx: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Vale.X64.Machine_s.nat64 * (Vale.X64.Machine_s.nat64 * (Vale.X64.Machine_s.nat64 * Vale.X64.Machine_s.nat64)))

Prims.Tot

val eval_Movdqu (src: quad32) : option quad32

let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src)

val eval_Movdqu (src: quad32) : option quad32 let eval_Movdqu (src: quad32) : option quad32 =

check_sse2 (Some src)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None

Vale.X64.Instructions_s.fsti

val eval_Movdqu (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_Movdqu

src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val check_ssse3 (#a: Type0) (x: option a) : option a

let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None

val check_ssse3 (#a: Type0) (x: option a) : option a let check_ssse3 (#a: Type0) (x: option a) : option a =

if ssse3_enabled then x else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None

Vale.X64.Instructions_s.fsti

val check_ssse3 (#a: Type0) (x: option a) : option a

Vale.X64.Instructions_s.check_ssse3

x: FStar.Pervasives.Native.option a -> FStar.Pervasives.Native.option a

Prims.Tot

val eval_And64 (dst src: nat64) : option nat64

let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src)

val eval_And64 (dst src: nat64) : option nat64 let eval_And64 (dst src: nat64) : option nat64 =

Some (iand dst src)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64

Vale.X64.Instructions_s.fsti

val eval_And64 (dst src: nat64) : option nat64

Vale.X64.Instructions_s.eval_And64

dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.nat64

Prims.Tot

val eval_Xgetbv (rcx: nat64) : option (nat64 & nat64)

let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None

val eval_Xgetbv (rcx: nat64) : option (nat64 & nat64) let eval_Xgetbv (rcx: nat64) : option (nat64 & nat64) =

if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction

Vale.X64.Instructions_s.fsti

val eval_Xgetbv (rcx: nat64) : option (nat64 & nat64)

Vale.X64.Instructions_s.eval_Xgetbv

rcx: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Vale.X64.Machine_s.nat64 * Vale.X64.Machine_s.nat64)

Prims.Tot

val check_sse4_1 (#a: Type0) (x: option a) : option a

let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None

val check_sse4_1 (#a: Type0) (x: option a) : option a let check_sse4_1 (#a: Type0) (x: option a) : option a =

if sse4_1_enabled then x else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None

Vale.X64.Instructions_s.fsti

val check_sse4_1 (#a: Type0) (x: option a) : option a

Vale.X64.Instructions_s.check_sse4_1

x: FStar.Pervasives.Native.option a -> FStar.Pervasives.Native.option a

Prims.Tot

val eval_Shufpd (permutation: int) (src1 src2: quad32) : option quad32

let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2)

val eval_Shufpd (permutation: int) (src1 src2: quad32) : option quad32 let eval_Shufpd (permutation: int) (src1 src2: quad32) : option quad32 =

check_sse2 (eval_Shufpd_raw permutation src1 src2)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None

Vale.X64.Instructions_s.fsti

val eval_Shufpd (permutation: int) (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_Shufpd

permutation: Prims.int -> src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Psrld (amt: int) (dst: quad32) : option quad32

let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None)

val eval_Psrld (amt: int) (dst: quad32) : option quad32 let eval_Psrld (amt: int) (dst: quad32) : option quad32 =

check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt)

Vale.X64.Instructions_s.fsti

val eval_Psrld (amt: int) (dst: quad32) : option quad32

Vale.X64.Instructions_s.eval_Psrld

amt: Prims.int -> dst: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Pand (dst src: quad32) : option quad32

let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src))

val eval_Pand (dst src: quad32) : option quad32 let eval_Pand (dst src: quad32) : option quad32 =

check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor

Vale.X64.Instructions_s.fsti

val eval_Pand (dst src: quad32) : option quad32

Vale.X64.Instructions_s.eval_Pand

dst: Vale.X64.Machine_s.quad32 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Cmovc64 (dst src: nat64) (carry: bool) : option nat64

let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst)

val eval_Cmovc64 (dst src: nat64) (carry: bool) : option nat64 let eval_Cmovc64 (dst src: nat64) (carry: bool) : option nat64 =

Some (if carry then src else dst)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64

Vale.X64.Instructions_s.fsti

val eval_Cmovc64 (dst src: nat64) (carry: bool) : option nat64

Vale.X64.Instructions_s.eval_Cmovc64

dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> carry: Prims.bool -> FStar.Pervasives.Native.option Vale.X64.Machine_s.nat64

Prims.Tot

val eval_Pslldq_raw (count: nat8) (src: quad32) : option quad32

let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None

val eval_Pslldq_raw (count: nat8) (src: quad32) : option quad32 let eval_Pslldq_raw (count: nat8) (src: quad32) : option quad32 =

if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 =

Vale.X64.Instructions_s.fsti

val eval_Pslldq_raw (count: nat8) (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_Pslldq_raw

count: Vale.Def.Types_s.nat8 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Pshufd (permutation: nat8) (src: quad32) : option quad32

let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3)))

val eval_Pshufd (permutation: nat8) (src: quad32) : option quad32 let eval_Pshufd (permutation: nat8) (src: quad32) : option quad32 =

check_sse2 (let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3)))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb

Vale.X64.Instructions_s.fsti

val eval_Pshufd (permutation: nat8) (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_Pshufd

permutation: Vale.Def.Types_s.nat8 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_LargeComment:option unit

let eval_LargeComment : option unit = Some ()

val eval_LargeComment:option unit let eval_LargeComment:option unit =

Some ()

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2 let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None val ins_SHA256_msg1 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg1 let eval_SHA256_msg2 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg2_spec src1 src2) else None val ins_SHA256_msg2 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg2 let eval_Ghost : option unit = Some () val ins_Ghost : instr_dep [] [] PreserveFlags eval_Ghost let eval_Comment : option unit = Some () val ins_Comment (_:string) : instr_dep [] [] PreserveFlags eval_Comment

Vale.X64.Instructions_s.fsti

val eval_LargeComment:option unit

Vale.X64.Instructions_s.eval_LargeComment

FStar.Pervasives.Native.option Prims.unit

Prims.Tot

val eval_Palignr (amount: nat8) (src1 src2: quad32) : option quad32

let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2)

val eval_Palignr (amount: nat8) (src1 src2: quad32) : option quad32 let eval_Palignr (amount: nat8) (src1 src2: quad32) : option quad32 =

check_ssse3 (eval_Palignr_raw amount src1 src2)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None

Vale.X64.Instructions_s.fsti

val eval_Palignr (amount: nat8) (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_Palignr

amount: Vale.Def.Types_s.nat8 -> src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Prefetchnta: nat64 -> option unit

let eval_Prefetchnta (_:nat64) : option unit = Some ()

val eval_Prefetchnta: nat64 -> option unit let eval_Prefetchnta (_: nat64) : option unit =

Some ()

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2 let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None val ins_SHA256_msg1 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg1 let eval_SHA256_msg2 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg2_spec src1 src2) else None val ins_SHA256_msg2 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg2 let eval_Ghost : option unit = Some () val ins_Ghost : instr_dep [] [] PreserveFlags eval_Ghost let eval_Comment : option unit = Some () val ins_Comment (_:string) : instr_dep [] [] PreserveFlags eval_Comment let eval_LargeComment : option unit = Some () val ins_LargeComment (_:string) : instr_dep [] [] PreserveFlags eval_LargeComment let eval_Newline : option unit = Some () val ins_Newline : instr_dep [] [] PreserveFlags eval_Newline let eval_Space : option unit = Some () val ins_Space (_:nat) : instr_dep [] [] PreserveFlags eval_Space

Vale.X64.Instructions_s.fsti

val eval_Prefetchnta: nat64 -> option unit

Vale.X64.Instructions_s.eval_Prefetchnta

_: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Prims.unit

Prims.Tot

val check_avx (#a: Type0) (x: option a) : option a

let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None

val check_avx (#a: Type0) (x: option a) : option a let check_avx (#a: Type0) (x: option a) : option a =

if avx_enabled then x else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv

Vale.X64.Instructions_s.fsti

val check_avx (#a: Type0) (x: option a) : option a

Vale.X64.Instructions_s.check_avx

x: FStar.Pervasives.Native.option a -> FStar.Pervasives.Native.option a

Prims.Tot

val eval_Ghost:option unit

let eval_Ghost : option unit = Some ()

val eval_Ghost:option unit let eval_Ghost:option unit =

Some ()

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2 let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None val ins_SHA256_msg1 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg1 let eval_SHA256_msg2 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg2_spec src1 src2) else None val ins_SHA256_msg2 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg2

Vale.X64.Instructions_s.fsti

val eval_Ghost:option unit

Vale.X64.Instructions_s.eval_Ghost

FStar.Pervasives.Native.option Prims.unit

Prims.Tot

val eval_VAESNI_enc (src1 src2: quad32) : option quad32

let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2)

val eval_VAESNI_enc (src1 src2: quad32) : option quad32 let eval_VAESNI_enc (src1 src2: quad32) : option quad32 =

check_avx (eval_AESNI_enc src1 src2)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc

Vale.X64.Instructions_s.fsti

val eval_VAESNI_enc (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_VAESNI_enc

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Palignr_raw (amount: nat8) (src1 src2: quad32) : option quad32

let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None

val eval_Palignr_raw (amount: nat8) (src1 src2: quad32) : option quad32 let eval_Palignr_raw (amount: nat8) (src1 src2: quad32) : option quad32 =

if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 =

Vale.X64.Instructions_s.fsti

val eval_Palignr_raw (amount: nat8) (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_Palignr_raw

amount: Vale.Def.Types_s.nat8 -> src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_SHA256_msg2 (src1 src2: quad32) : option quad32

let eval_SHA256_msg2 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg2_spec src1 src2) else None

val eval_SHA256_msg2 (src1 src2: quad32) : option quad32 let eval_SHA256_msg2 (src1 src2: quad32) : option quad32 =

if sha_enabled then Some (sha256_msg2_spec src1 src2) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None val ins_AESNI_keygen_assist (imm:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_AESNI_keygen_assist imm) let eval_SHA256_rnds2 (src1 src2 wk:quad32) : option quad32 = if sha_enabled then Some (sha256_rnds2_spec src1 src2 wk) else None val ins_SHA256_rnds2 : instr_dep [inOut opXmm] [opXmm; oneXmm (OReg 0)] PreserveFlags eval_SHA256_rnds2 let eval_SHA256_msg1 (src1 src2:quad32) : option quad32 = if sha_enabled then Some (sha256_msg1_spec src1 src2) else None val ins_SHA256_msg1 : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_SHA256_msg1

Vale.X64.Instructions_s.fsti

val eval_SHA256_msg2 (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_SHA256_msg2

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_AddCarry64 (old_carry: bool) (dst src: nat64) : option (bool & nat64)

let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64)

val eval_AddCarry64 (old_carry: bool) (dst src: nat64) : option (bool & nat64) let eval_AddCarry64 (old_carry: bool) (dst src: nat64) : option (bool & nat64) =

let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64

Vale.X64.Instructions_s.fsti

val eval_AddCarry64 (old_carry: bool) (dst src: nat64) : option (bool & nat64)

Vale.X64.Instructions_s.eval_AddCarry64

old_carry: Prims.bool -> dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Prims.bool * Vale.X64.Machine_s.nat64)

Prims.Tot

val eval_Mul64 (rax src: nat64) : option (nat64 & nat64)

let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src)

val eval_Mul64 (rax src: nat64) : option (nat64 & nat64) let eval_Mul64 (rax src: nat64) : option (nat64 & nat64) =

Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64

Vale.X64.Instructions_s.fsti

val eval_Mul64 (rax src: nat64) : option (nat64 & nat64)

Vale.X64.Instructions_s.eval_Mul64

rax: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Vale.X64.Machine_s.nat64 * Vale.X64.Machine_s.nat64)

Prims.Tot

val eval_Paddd_raw (src1 src2: quad32) : option quad32

let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32))

val eval_Paddd_raw (src1 src2: quad32) : option quad32 let eval_Paddd_raw (src1 src2: quad32) : option quad32 =

Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand

Vale.X64.Instructions_s.fsti

val eval_Paddd_raw (src1 src2: quad32) : option quad32

Vale.X64.Instructions_s.eval_Paddd_raw

src1: Vale.X64.Machine_s.quad32 -> src2: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Adcx64_Adox64 (old_flag: bool) (dst src: nat64) : option (bool & nat64)

let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None

val eval_Adcx64_Adox64 (old_flag: bool) (dst src: nat64) : option (bool & nat64) let eval_Adcx64_Adox64 (old_flag: bool) (dst src: nat64) : option (bool & nat64) =

let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64

Vale.X64.Instructions_s.fsti

val eval_Adcx64_Adox64 (old_flag: bool) (dst src: nat64) : option (bool & nat64)

Vale.X64.Instructions_s.eval_Adcx64_Adox64

old_flag: Prims.bool -> dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Prims.bool * Vale.X64.Machine_s.nat64)

Prims.Tot

val eval_Mulx64 (rdx src: nat64) : option (nat64 & nat64)

let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None

val eval_Mulx64 (rdx src: nat64) : option (nat64 & nat64) let eval_Mulx64 (rdx src: nat64) : option (nat64 & nat64) =

let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64

Vale.X64.Instructions_s.fsti

val eval_Mulx64 (rdx src: nat64) : option (nat64 & nat64)

Vale.X64.Instructions_s.eval_Mulx64

rdx: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Vale.X64.Machine_s.nat64 * Vale.X64.Machine_s.nat64)

Prims.Tot

val eval_IMul64 (dst src: nat64) : option nat64

let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src)

val eval_IMul64 (dst src: nat64) : option nat64 let eval_IMul64 (dst src: nat64) : option nat64 =

Some (FStar.UInt.mul_mod #64 dst src)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64

Vale.X64.Instructions_s.fsti

val eval_IMul64 (dst src: nat64) : option nat64

Vale.X64.Instructions_s.eval_IMul64

dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.nat64

Prims.Tot

val eval_Sbb64 (old_carry: bool) (dst src: nat64) : option (bool & nat64)

let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64)

val eval_Sbb64 (old_carry: bool) (dst src: nat64) : option (bool & nat64) let eval_Sbb64 (old_carry: bool) (dst src: nat64) : option (bool & nat64) =

let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64

Vale.X64.Instructions_s.fsti

val eval_Sbb64 (old_carry: bool) (dst src: nat64) : option (bool & nat64)

Vale.X64.Instructions_s.eval_Sbb64

old_carry: Prims.bool -> dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Prims.bool * Vale.X64.Machine_s.nat64)

Prims.Tot

val eval_Add64 (dst src: nat64) : option (bool & nat64)

let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64)

val eval_Add64 (dst src: nat64) : option (bool & nat64) let eval_Add64 (dst src: nat64) : option (bool & nat64) =

let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64

Vale.X64.Instructions_s.fsti

val eval_Add64 (dst src: nat64) : option (bool & nat64)

Vale.X64.Instructions_s.eval_Add64

dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Prims.bool * Vale.X64.Machine_s.nat64)

Prims.Tot

val eval_Sub64 (dst src: nat64) : option (bool & nat64)

let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64)

val eval_Sub64 (dst src: nat64) : option (bool & nat64) let eval_Sub64 (dst src: nat64) : option (bool & nat64) =

let diff = dst - src in Some (diff < 0, diff % pow2_64)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64

Vale.X64.Instructions_s.fsti

val eval_Sub64 (dst src: nat64) : option (bool & nat64)

Vale.X64.Instructions_s.eval_Sub64

dst: Vale.X64.Machine_s.nat64 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option (Prims.bool * Vale.X64.Machine_s.nat64)

Prims.Tot

val eval_Pcmpeqd (dst src: quad32) : option quad32

let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3))))

val eval_Pcmpeqd (dst src: quad32) : option quad32 let eval_Pcmpeqd (dst src: quad32) : option quad32 =

check_sse2 (let eq_result (b: bool) : nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3))))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation)

Vale.X64.Instructions_s.fsti

val eval_Pcmpeqd (dst src: quad32) : option quad32

Vale.X64.Instructions_s.eval_Pcmpeqd

dst: Vale.X64.Machine_s.quad32 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_AddLea64 (src1 src2: nat64) : option nat64

let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64)

val eval_AddLea64 (src1 src2: nat64) : option nat64 let eval_AddLea64 (src1 src2: nat64) : option nat64 =

Some ((src1 + src2) % pow2_64)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64

Vale.X64.Instructions_s.fsti

val eval_AddLea64 (src1 src2: nat64) : option nat64

Vale.X64.Instructions_s.eval_AddLea64

src1: Vale.X64.Machine_s.nat64 -> src2: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.nat64

Prims.Tot

val eval_Psrldq (amt: int) (dst: quad32) : option quad32

let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None)

val eval_Psrldq (amt: int) (dst: quad32) : option quad32 let eval_Psrldq (amt: int) (dst: quad32) : option quad32 =

check_sse2 (if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None)

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt)

Vale.X64.Instructions_s.fsti

val eval_Psrldq (amt: int) (dst: quad32) : option quad32

Vale.X64.Instructions_s.eval_Psrldq

amt: Prims.int -> dst: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_AESNI_keygen_assist (imm: nat8) (src: quad32) : option quad32

let eval_AESNI_keygen_assist (imm:nat8) (src:quad32) : option quad32 = if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None

val eval_AESNI_keygen_assist (imm: nat8) (src: quad32) : option quad32 let eval_AESNI_keygen_assist (imm: nat8) (src: quad32) : option quad32 =

if aesni_enabled then Some (Mkfour (Vale.AES.AES_s.sub_word src.lo1) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.lo1)) imm) (Vale.AES.AES_s.sub_word src.hi3) (ixor (Vale.AES.AES_s.rot_word_LE (Vale.AES.AES_s.sub_word src.hi3)) imm)) else None

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index) let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2))) val ins_Pinsrq (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrq index) let eval_Pslldq_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the two very special cases we need if count = 4 then Some (Mkfour 0 src.lo0 src.lo1 src.hi2) else if count = 8 then Some (Mkfour 0 0 src.lo0 src.lo1) else None let eval_VPslldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Pslldq_raw count src) val ins_VPslldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPslldq count) let eval_Psrldq_8_raw (count:nat8) (src:quad32) : option quad32 = // We only spec the one very special case we need if count = 8 then Some (Mkfour src.hi2 src.hi3 0 0) else None let eval_VPsrldq (count:nat8) (src:quad32) : option quad32 = check_avx (eval_Psrldq_8_raw count src) val ins_VPsrldq (count:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_VPsrldq count) let eval_Pclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = let Mkfour a0 a1 a2 a3 = src1 in let Mkfour b0 b1 b2 b3 = src2 in let f x0 x1 y0 y1 = let x = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo x0 x1) in let y = Vale.Math.Poly2.Bits_s.of_double32 (Mktwo y0 y1) in Vale.Math.Poly2.Bits_s.to_quad32 (Vale.Math.Poly2_s.mul x y) in if pclmulqdq_enabled then match imm with | 0 -> Some (f a0 a1 b0 b1) | 1 -> Some (f a2 a3 b0 b1) | 16 -> Some (f a0 a1 b2 b3) | 17 -> Some (f a2 a3 b2 b3) | _ -> None else None val ins_Pclmulqdq (imm:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Pclmulqdq imm) let eval_VPclmulqdq (imm:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Pclmulqdq imm src1 src2) val ins_VPclmulqdq (imm:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPclmulqdq imm) let eval_AESNI_enc (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.mix_columns_LE (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1))) src2) else None val ins_AESNI_enc : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc let eval_VAESNI_enc (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc src1 src2) val ins_VAESNI_enc : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc let eval_AESNI_enc_last (src1 src2:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.sub_bytes (Vale.AES.AES_s.shift_rows_LE src1)) src2) else None val ins_AESNI_enc_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_enc_last let eval_VAESNI_enc_last (src1 src2:quad32) : option quad32 = check_avx (eval_AESNI_enc_last src1 src2) val ins_VAESNI_enc_last : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VAESNI_enc_last let eval_AESNI_dec (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_mix_columns_LE (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst))) src) else None val ins_AESNI_dec : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec let eval_AESNI_dec_last (dst src:quad32) : option quad32 = if aesni_enabled then Some (quad32_xor (Vale.AES.AES_s.inv_sub_bytes (Vale.AES.AES_s.inv_shift_rows_LE dst)) src) else None val ins_AESNI_dec_last : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_AESNI_dec_last let eval_AESNI_imc (src:quad32) : option quad32 = if aesni_enabled then Some (Vale.AES.AES_s.inv_mix_columns_LE src) else None val ins_AESNI_imc : instr_dep [out opXmm] [opXmm] PreserveFlags eval_AESNI_imc

Vale.X64.Instructions_s.fsti

val eval_AESNI_keygen_assist (imm: nat8) (src: quad32) : option quad32

Vale.X64.Instructions_s.eval_AESNI_keygen_assist

imm: Vale.Def.Types_s.nat8 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Pinsrd (index: nat8) (dst: quad32) (src: nat64) : option quad32

let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4)))

val eval_Pinsrd (index: nat8) (dst: quad32) (src: nat64) : option quad32 let eval_Pinsrd (index: nat8) (dst: quad32) (src: nat64) : option quad32 =

check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4)))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index)

Vale.X64.Instructions_s.fsti

val eval_Pinsrd (index: nat8) (dst: quad32) (src: nat64) : option quad32

Vale.X64.Instructions_s.eval_Pinsrd

index: Vale.Def.Types_s.nat8 -> dst: Vale.X64.Machine_s.quad32 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Pinsrq (index: nat8) (dst: quad32) (src: nat64) : option quad32

let eval_Pinsrq (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat64_def dst src (index % 2)))

val eval_Pinsrq (index: nat8) (dst: quad32) (src: nat64) : option quad32 let eval_Pinsrq (index: nat8) (dst: quad32) (src: nat64) : option quad32 =

check_sse4_1 (Some (insert_nat64_def dst src (index % 2)))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2)))) val ins_Pextrq (index:nat8) : instr_dep [out op64] [opXmm] PreserveFlags (eval_Pextrq index) let eval_Pinsrd (index:nat8) (dst:quad32) (src:nat64) : option quad32 = check_sse4_1 (Some (insert_nat32 dst (src % pow2_32) (index % 4))) val ins_Pinsrd (index:nat8) : instr_dep [inOut opXmm] [op64] PreserveFlags (eval_Pinsrd index)

Vale.X64.Instructions_s.fsti

val eval_Pinsrq (index: nat8) (dst: quad32) (src: nat64) : option quad32

Vale.X64.Instructions_s.eval_Pinsrq

index: Vale.Def.Types_s.nat8 -> dst: Vale.X64.Machine_s.quad32 -> src: Vale.X64.Machine_s.nat64 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.quad32

Prims.Tot

val eval_Pextrq (index: nat8) (src: quad32) : option nat64

let eval_Pextrq (index:nat8) (src:quad32) : option nat64 = check_sse4_1 ( let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2))))

val eval_Pextrq (index: nat8) (src: quad32) : option nat64 let eval_Pextrq (index: nat8) (src: quad32) : option nat64 =

check_sse4_1 (let src_two = four_to_two_two src in Some (two_to_nat 32 (two_select src_two (index % 2))))

module Vale.X64.Instructions_s open FStar.Mul open Vale.Def.Words_s open Vale.Def.Words.Two_s open Vale.Def.Words.Four_s open Vale.Def.Types_s open Vale.X64.Machine_s open Vale.X64.Instruction_s open Vale.X64.CPU_Features_s open Vale.X64.CryptoInstructions_s open FStar.Seq.Base let eval_Mov64 (src:nat64) : option nat64 = Some src val ins_Mov64 : instr_dep [out op64] [op64] PreserveFlags eval_Mov64 let eval_MovBe64 (src:nat64) : option nat64 = if movbe_enabled then Some (reverse_bytes_nat64 src) else None val ins_MovBe64 : instr_dep [out op64] [op64] PreserveFlags eval_MovBe64 let eval_Bswap64 (dst:nat64) : option nat64 = Some (reverse_bytes_nat64 dst) val ins_Bswap64 : instr_dep [inOut op64] [] PreserveFlags eval_Bswap64 let eval_Cmovc64 (dst src:nat64) (carry:bool) : option nat64 = Some (if carry then src else dst) val ins_Cmovc64 : instr_dep [inOut op64] [op64; opFlagsCf] PreserveFlags eval_Cmovc64 let eval_Add64 (dst src:nat64) : option (bool & nat64) = let sum = dst + src in Some (sum >= pow2_64, sum % pow2_64) val ins_Add64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Add64 let eval_AddLea64 (src1 src2:nat64) : option nat64 = Some ((src1 + src2) % pow2_64) val ins_AddLea64 :instr_dep [out op64] [op64; op64] PreserveFlags eval_AddLea64 let eval_AddCarry64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_carry then 1 else 0) in Some (sum >= pow2_64, sum % pow2_64) val ins_AddCarry64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_AddCarry64 let eval_Adcx64_Adox64 (old_flag:bool) (dst src:nat64) : option (bool & nat64) = let sum = dst + src + (if old_flag then 1 else 0) in if adx_enabled then Some (sum >= pow2_64, sum % pow2_64) else None val ins_Adcx64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 val ins_Adox64 : instr_dep [inOut opFlagsOf; inOut op64] [op64] PreserveFlags eval_Adcx64_Adox64 let eval_Sub64 (dst src:nat64) : option (bool & nat64) = let diff = dst - src in Some (diff < 0, diff % pow2_64) val ins_Sub64 : instr_dep [out opFlagsCf; inOut op64] [op64] HavocFlags eval_Sub64 let eval_Sbb64 (old_carry:bool) (dst src:nat64) : option (bool & nat64) = let diff = dst - (src + (if old_carry then 1 else 0)) in Some (diff < 0, diff % pow2_64) // We specify cf, but underspecify everything else (via HavocFlags) val ins_Sbb64 : instr_dep [inOut opFlagsCf; inOut op64] [op64] HavocFlags eval_Sbb64 let eval_Mul64 (rax src:nat64) : option (nat64 & nat64) = Some (FStar.UInt.mul_div #64 rax src, FStar.UInt.mul_mod #64 rax src) val ins_Mul64 : instr_dep [out (one64Reg rRdx); inOut (one64Reg rRax)] [op64] HavocFlags eval_Mul64 let eval_Mulx64 (rdx src:nat64) : option (nat64 & nat64) = let hi = FStar.UInt.mul_div #64 rdx src in let lo = FStar.UInt.mul_mod #64 rdx src in if bmi2_enabled then Some (hi, lo) else None val ins_Mulx64 : instr_dep [out op64; out op64] [one64Reg rRdx; op64] PreserveFlags eval_Mulx64 let eval_IMul64 (dst src:nat64) : option nat64 = Some (FStar.UInt.mul_mod #64 dst src) val ins_IMul64 : instr_dep [inOut op64] [op64] HavocFlags eval_IMul64 let eval_And64 (dst src:nat64) : option nat64 = Some (iand dst src) val ins_And64 : instr_dep [inOut op64] [op64] HavocFlags eval_And64 let eval_Xor64 (dst src:nat64) : option (nat64 & (bool & bool)) = Some (Vale.Def.Types_s.ixor dst src, (false, false)) val ins_Xor64 : instr_dep [inOut op64; out opFlagsCf; out opFlagsOf] [op64] HavocFlags eval_Xor64 let eval_Shr64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishr dst amt) else None val ins_Shr64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shr64 let eval_Shl64 (dst amt:nat64) : option nat64 = if amt < 64 then Some (Vale.Def.Types_s.ishl dst amt) else None val ins_Shl64 : instr_dep [inOut op64] [op64] HavocFlags eval_Shl64 let eval_Cpuid (rax rcx:nat64) : option (nat64 & (nat64 & (nat64 & nat64))) = Some (cpuid rRax rax rcx, (cpuid rRbx rax rcx, (cpuid rRcx rax rcx, cpuid rRdx rax rcx))) val ins_Cpuid : instr_dep [inOut (one64Reg rRax); out (one64Reg rRbx); inOut (one64Reg rRcx); out (one64Reg rRdx)] [] PreserveFlags eval_Cpuid // The XGETBV instruction requires that OSXSAVE (in CPUID) is enabled. // We underspecify XGETBV here to only support fetching XCR0, which // is supported on any processor supporting the XGETBV instruction let eval_Xgetbv (rcx:nat64) : option (nat64 & nat64) = if osxsave_enabled && rcx = 0 then Some (xgetbv rRax rcx, xgetbv rRdx rcx) else None val ins_Xgetbv : instr_dep [out (one64Reg rRax); out (one64Reg rRdx)] [one64Reg rRcx] PreserveFlags eval_Xgetbv let check_avx (#a:Type0) (x:option a) : option a = if avx_enabled then x else None let check_sse2 (#a:Type0) (x:option a) : option a = if sse2_enabled then x else None let check_ssse3 (#a:Type0) (x:option a) : option a = if ssse3_enabled then x else None let check_sse4_1 (#a:Type0) (x:option a) : option a = if sse4_1_enabled then x else None let eval_Movdqu (src:quad32) : option quad32 = check_sse2 (Some src) val ins_Movdqu : instr_dep [out opXmm] [opXmm] PreserveFlags eval_Movdqu let eval_Pxor (dst src:quad32) : option quad32 = check_sse2 (Some (quad32_xor dst src)) val ins_Pxor : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pxor let eval_VPxor (src1 src2:quad32) : option quad32 = check_avx (Some (quad32_xor src1 src2)) val ins_VPxor : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPxor let eval_Pand (dst src:quad32) : option quad32 = check_sse2 (Some (four_map2 (fun di si -> iand di si) dst src)) val ins_Pand : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pand let eval_Paddd_raw (src1 src2:quad32) : option quad32 = Some (Mkfour ((src1.lo0 + src2.lo0) % pow2_32) ((src1.lo1 + src2.lo1) % pow2_32) ((src1.hi2 + src2.hi2) % pow2_32) ((src1.hi3 + src2.hi3) % pow2_32)) let eval_Paddd (src1 src2:quad32) : option quad32 = check_sse2 (eval_Paddd_raw src1 src2) val ins_Paddd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Paddd let eval_VPaddd (src1 src2:quad32) : option quad32 = check_avx (eval_Paddd_raw src1 src2) val ins_VPaddd : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPaddd let eval_Pslld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishl i amt) dst) else None) val ins_Pslld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Pslld amt) let eval_Psrld (amt:int) (dst:quad32) : option quad32 = check_sse2 (if 0 <= amt && amt < 32 then Some (four_map (fun i -> ishr i amt) dst) else None) val ins_Psrld (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrld amt) let eval_Psrldq (amt:int) (dst:quad32) : option quad32 = check_sse2 ( if 0 <= amt && amt < 16 then let src_bytes = le_quad32_to_bytes dst in let zero_pad = Seq.create amt 0 in let remaining_bytes = slice src_bytes amt (length src_bytes) in Some (le_bytes_to_quad32 (append zero_pad remaining_bytes)) else None) val ins_Psrldq (amt:int) : instr_dep [inOut opXmm] [] PreserveFlags (eval_Psrldq amt) let eval_Palignr_raw (amount:nat8) (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if amount = 4 then Some (Mkfour src2.lo1 src2.hi2 src2.hi3 src1.lo0) else if amount = 8 then Some (Mkfour src2.hi2 src2.hi3 src1.lo0 src1.lo1) else None let eval_Palignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Palignr_raw amount src1 src2) val ins_Palignr (amount:nat8) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Palignr amount) let eval_VPalignr (amount:nat8) (src1 src2:quad32) : option quad32 = check_avx (eval_Palignr_raw amount src1 src2) val ins_VPalignr (amount:nat8) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VPalignr amount) let eval_Shufpd_raw (permutation:int) (src1 src2:quad32) : option quad32 = if 0 <= permutation && permutation < 4 then Some (Mkfour (if permutation % 2 = 0 then src1.lo0 else src1.hi2) (if permutation % 2 = 0 then src1.lo1 else src1.hi3) (if (permutation / 2) % 2 = 0 then src2.lo0 else src2.hi2) (if (permutation / 2) % 2 = 0 then src2.lo1 else src2.hi3)) else None let eval_Shufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_sse2 (eval_Shufpd_raw permutation src1 src2) val ins_Shufpd (permutation:int) : instr_dep [inOut opXmm] [opXmm] PreserveFlags (eval_Shufpd permutation) let eval_VShufpd (permutation:int) (src1 src2:quad32) : option quad32 = check_avx (eval_Shufpd_raw permutation src1 src2) val ins_VShufpd (permutation:int) : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags (eval_VShufpd permutation) let is_full_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x04050607 && q.hi3 = 0x00010203 let is_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x00010203 && q.lo1 = 0x04050607 && q.hi2 = 0x08090A0B && q.hi3 = 0x0C0D0E0F let is_high_dup_reversal_mask (q:quad32) : bool = q.lo0 = 0x0C0D0E0F && q.lo1 = 0x08090A0B && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let is_lower_upper_byte_reversal_mask (q:quad32) : bool = q.lo0 = 0x04050607 && q.lo1 = 0x00010203 && q.hi2 = 0x0C0D0E0F && q.hi3 = 0x08090A0B let eval_Pshufb_raw (src1 src2:quad32) : option quad32 = // We only spec a restricted version sufficient for a handful of standard patterns if is_full_byte_reversal_mask src2 then Some (reverse_bytes_quad32 src1) else if is_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3)) else if is_high_dup_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else if is_lower_upper_byte_reversal_mask src2 then Some (Mkfour (reverse_bytes_nat32 src1.lo1) (reverse_bytes_nat32 src1.lo0) (reverse_bytes_nat32 src1.hi3) (reverse_bytes_nat32 src1.hi2)) else None let eval_Pshufb (src1 src2:quad32) : option quad32 = check_ssse3 (eval_Pshufb_raw src1 src2) val ins_Pshufb : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pshufb let eval_VPshufb (src1 src2:quad32) : option quad32 = check_avx (eval_Pshufb_raw src1 src2) val ins_VPshufb : instr_dep [out opXmm] [opXmm; opXmm] PreserveFlags eval_VPshufb let eval_Pshufd (permutation:nat8) (src:quad32) : option quad32 = check_sse2 ( let bits:bits_of_byte = byte_to_twobits permutation in Some (Mkfour (select_word src bits.lo0) (select_word src bits.lo1) (select_word src bits.hi2) (select_word src bits.hi3))) val ins_Pshufd (permutation:nat8) : instr_dep [out opXmm] [opXmm] PreserveFlags (eval_Pshufd permutation) let eval_Pcmpeqd (dst src:quad32) : option quad32 = check_sse2 ( let eq_result (b:bool):nat32 = if b then 0xFFFFFFFF else 0 in Some (Mkfour (eq_result (src.lo0 = dst.lo0)) (eq_result (src.lo1 = dst.lo1)) (eq_result (src.hi2 = dst.hi2)) (eq_result (src.hi3 = dst.hi3)))) val ins_Pcmpeqd : instr_dep [inOut opXmm] [opXmm] PreserveFlags eval_Pcmpeqd

Vale.X64.Instructions_s.fsti

val eval_Pextrq (index: nat8) (src: quad32) : option nat64

Vale.X64.Instructions_s.eval_Pextrq

index: Vale.Def.Types_s.nat8 -> src: Vale.X64.Machine_s.quad32 -> FStar.Pervasives.Native.option Vale.X64.Machine_s.nat64

Prims.Tot

let size_publickey = 32

let size_publickey =

32

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0"

Spec.Box.fst

val size_publickey : Prims.int

Spec.Box.size_publickey

Prims.int

Prims.Tot

let size_secretkey = 32

let size_secretkey =

32

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *)

Spec.Box.fst

val size_secretkey : Prims.int

Spec.Box.size_secretkey

Prims.int

Prims.Tot

val ecdh (pk: publickey) (sk: secretkey) : option secretkey

let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None

val ecdh (pk: publickey) (sk: secretkey) : option secretkey let ecdh (pk: publickey) (sk: secretkey) : option secretkey =

let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey

Spec.Box.fst

val ecdh (pk: publickey) (sk: secretkey) : option secretkey

Spec.Box.ecdh

pk: Spec.Box.publickey -> sk: Spec.Box.secretkey -> FStar.Pervasives.Native.option Spec.Box.secretkey

Prims.Tot

val box_beforenm (pk: publickey) (sk: secretkey) : option key

let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None

val box_beforenm (pk: publickey) (sk: secretkey) : option key let box_beforenm (pk: publickey) (sk: secretkey) : option key =

let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None

Spec.Box.fst

val box_beforenm (pk: publickey) (sk: secretkey) : option key

Spec.Box.box_beforenm

pk: Spec.Box.publickey -> sk: Spec.Box.secretkey -> FStar.Pervasives.Native.option Spec.SecretBox.key

Prims.Tot

val box_detached_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : tag & c: bytes{length c = length m}

let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m

val box_detached_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : tag & c: bytes{length c = length m} let box_detached_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : tag & c: bytes{length c = length m} =

secretbox_detached k n m

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None

Spec.Box.fst

val box_detached_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : tag & c: bytes{length c = length m}

Spec.Box.box_detached_afternm

k: Spec.SecretBox.key -> n: Spec.SecretBox.nonce -> m: Lib.ByteSequence.bytes {Lib.Sequence.length m / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t} -> Spec.SecretBox.tag * c: Lib.ByteSequence.bytes{Lib.Sequence.length c = Lib.Sequence.length m}

Prims.Tot

val box_open_detached_afternm (k: key) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c})

let box_open_detached_afternm (k:key) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = secretbox_open_detached k n t c

val box_open_detached_afternm (k: key) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c}) let box_open_detached_afternm (k: key) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c}) =

secretbox_open_detached k n t c

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m let box_detached (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (tag & c:bytes{length c = length m}) = let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None

Spec.Box.fst

val box_open_detached_afternm (k: key) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c})

Spec.Box.box_open_detached_afternm

k: Spec.SecretBox.key -> n: Spec.SecretBox.nonce -> t: Spec.SecretBox.tag -> c: Lib.ByteSequence.bytes {Lib.Sequence.length c / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t} -> FStar.Pervasives.Native.option (m: Lib.ByteSequence.bytes{Lib.Sequence.length m = Lib.Sequence.length c})

Prims.Tot

val box_easy_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : c: bytes{length c = size_tag + length m}

let box_easy_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : c:bytes{length c = size_tag + length m} = let (tg, c) = box_detached_afternm k n m in Seq.append tg c

val box_easy_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : c: bytes{length c = size_tag + length m} let box_easy_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : c: bytes{length c = size_tag + length m} =

let tg, c = box_detached_afternm k n m in Seq.append tg c

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m let box_detached (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (tag & c:bytes{length c = length m}) = let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None let box_open_detached_afternm (k:key) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = secretbox_open_detached k n t c let box_open_detached (pk:publickey) (sk:secretkey) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = let k = box_beforenm pk sk in match k with | Some k -> box_open_detached_afternm k n t c | None -> None

Spec.Box.fst

val box_easy_afternm (k: key) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : c: bytes{length c = size_tag + length m}

Spec.Box.box_easy_afternm

k: Spec.SecretBox.key -> n: Spec.SecretBox.nonce -> m: Lib.ByteSequence.bytes {Lib.Sequence.length m / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t} -> c: Lib.ByteSequence.bytes{Lib.Sequence.length c = Spec.SecretBox.size_tag + Lib.Sequence.length m}

Prims.Tot

val box_open_detached (pk: publickey) (sk: secretkey) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c})

let box_open_detached (pk:publickey) (sk:secretkey) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = let k = box_beforenm pk sk in match k with | Some k -> box_open_detached_afternm k n t c | None -> None

val box_open_detached (pk: publickey) (sk: secretkey) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c}) let box_open_detached (pk: publickey) (sk: secretkey) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c}) =

let k = box_beforenm pk sk in match k with | Some k -> box_open_detached_afternm k n t c | None -> None

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m let box_detached (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (tag & c:bytes{length c = length m}) = let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None let box_open_detached_afternm (k:key) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = secretbox_open_detached k n t c

Spec.Box.fst

val box_open_detached (pk: publickey) (sk: secretkey) (n: nonce) (t: tag) (c: bytes{length c / size_block <= max_size_t}) : option (m: bytes{length m = length c})

Spec.Box.box_open_detached

pk: Spec.Box.publickey -> sk: Spec.Box.secretkey -> n: Spec.SecretBox.nonce -> t: Spec.SecretBox.tag -> c: Lib.ByteSequence.bytes {Lib.Sequence.length c / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t} -> FStar.Pervasives.Native.option (m: Lib.ByteSequence.bytes{Lib.Sequence.length m = Lib.Sequence.length c})

Prims.Tot

val box_detached (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (tag & c: bytes{length c = length m})

let box_detached (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (tag & c:bytes{length c = length m}) = let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None

val box_detached (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (tag & c: bytes{length c = length m}) let box_detached (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (tag & c: bytes{length c = length m}) =

let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m

Spec.Box.fst

val box_detached (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (tag & c: bytes{length c = length m})

Spec.Box.box_detached

sk: Spec.Box.secretkey -> pk: Spec.Box.publickey -> n: Spec.SecretBox.nonce -> m: Lib.ByteSequence.bytes {Lib.Sequence.length m / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t} -> FStar.Pervasives.Native.option (Spec.SecretBox.tag * c: Lib.ByteSequence.bytes{Lib.Sequence.length c = Lib.Sequence.length m})

Prims.Tot

val box_easy (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (c: bytes{length c = size_tag + length m})

let box_easy (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (c:bytes{length c = size_tag + length m}) = let r = box_detached sk pk n m in match r with | Some (tg, c) -> Some (Seq.append tg c) | None -> None

val box_easy (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (c: bytes{length c = size_tag + length m}) let box_easy (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (c: bytes{length c = size_tag + length m}) =

let r = box_detached sk pk n m in match r with | Some (tg, c) -> Some (Seq.append tg c) | None -> None

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m let box_detached (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (tag & c:bytes{length c = length m}) = let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None let box_open_detached_afternm (k:key) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = secretbox_open_detached k n t c let box_open_detached (pk:publickey) (sk:secretkey) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = let k = box_beforenm pk sk in match k with | Some k -> box_open_detached_afternm k n t c | None -> None let box_easy_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : c:bytes{length c = size_tag + length m} = let (tg, c) = box_detached_afternm k n m in Seq.append tg c

Spec.Box.fst

val box_easy (sk: secretkey) (pk: publickey) (n: nonce) (m: bytes{length m / size_block <= max_size_t}) : option (c: bytes{length c = size_tag + length m})

Spec.Box.box_easy

sk: Spec.Box.secretkey -> pk: Spec.Box.publickey -> n: Spec.SecretBox.nonce -> m: Lib.ByteSequence.bytes {Lib.Sequence.length m / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t} -> FStar.Pervasives.Native.option (c: Lib.ByteSequence.bytes {Lib.Sequence.length c = Spec.SecretBox.size_tag + Lib.Sequence.length m})

Prims.Tot

val box_open_easy_afternm (k: key) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag})

let box_open_easy_afternm (k:key) (n:nonce) (c:bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m:bytes{length m = length c - size_tag}) = let tg = Seq.slice c 0 size_tag in let e = Seq.slice c size_tag (length c) in box_open_detached_afternm k n tg e

val box_open_easy_afternm (k: key) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag}) let box_open_easy_afternm (k: key) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag}) =

let tg = Seq.slice c 0 size_tag in let e = Seq.slice c size_tag (length c) in box_open_detached_afternm k n tg e

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m let box_detached (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (tag & c:bytes{length c = length m}) = let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None let box_open_detached_afternm (k:key) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = secretbox_open_detached k n t c let box_open_detached (pk:publickey) (sk:secretkey) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = let k = box_beforenm pk sk in match k with | Some k -> box_open_detached_afternm k n t c | None -> None let box_easy_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : c:bytes{length c = size_tag + length m} = let (tg, c) = box_detached_afternm k n m in Seq.append tg c let box_easy (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (c:bytes{length c = size_tag + length m}) = let r = box_detached sk pk n m in match r with | Some (tg, c) -> Some (Seq.append tg c) | None -> None

Spec.Box.fst

val box_open_easy_afternm (k: key) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag})

Spec.Box.box_open_easy_afternm

k: Spec.SecretBox.key -> n: Spec.SecretBox.nonce -> c: Lib.ByteSequence.bytes { Lib.Sequence.length c >= Spec.SecretBox.size_tag /\ (Lib.Sequence.length c - Spec.SecretBox.size_tag) / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t } -> FStar.Pervasives.Native.option (m: Lib.ByteSequence.bytes {Lib.Sequence.length m = Lib.Sequence.length c - Spec.SecretBox.size_tag})

Prims.Tot

val box_open_easy (pk: secretkey) (sk: publickey) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag})

let box_open_easy (pk:secretkey) (sk:publickey) (n:nonce) (c:bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m:bytes{length m = length c - size_tag}) = let tg = Seq.slice c 0 size_tag in let e = Seq.slice c size_tag (length c) in box_open_detached pk sk n tg e

val box_open_easy (pk: secretkey) (sk: publickey) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag}) let box_open_easy (pk: secretkey) (sk: publickey) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag}) =

let tg = Seq.slice c 0 size_tag in let e = Seq.slice c size_tag (length c) in box_open_detached pk sk n tg e

module Spec.Box open FStar.Mul open Lib.IntTypes open Lib.Sequence open Lib.ByteSequence open Spec.SecretBox #set-options "--z3rlimit 20 --max_fuel 0 --max_ifuel 0" (* Constants *) let size_publickey = 32 (* in bytes *) let size_secretkey = 32 (* in bytes *) type publickey = lbytes size_publickey type secretkey = lbytes size_secretkey let ecdh (pk:publickey) (sk:secretkey) : option secretkey = let shared = Spec.Curve25519.scalarmult sk pk in if not (lbytes_eq shared (create 32 (u8 0))) then Some shared else None let box_beforenm (pk:publickey) (sk:secretkey) : option key = let shared = ecdh pk sk in match shared with | Some shared -> Some (Spec.Salsa20.hsalsa20 shared (create 16 (u8 0))) | None -> None let box_detached_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : tag & c:bytes{length c = length m} = secretbox_detached k n m let box_detached (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (tag & c:bytes{length c = length m}) = let k = box_beforenm pk sk in match k with | Some k -> Some (box_detached_afternm k n m) | None -> None let box_open_detached_afternm (k:key) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = secretbox_open_detached k n t c let box_open_detached (pk:publickey) (sk:secretkey) (n:nonce) (t:tag) (c:bytes{length c / size_block <= max_size_t}) : option (m:bytes{length m = length c}) = let k = box_beforenm pk sk in match k with | Some k -> box_open_detached_afternm k n t c | None -> None let box_easy_afternm (k:key) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : c:bytes{length c = size_tag + length m} = let (tg, c) = box_detached_afternm k n m in Seq.append tg c let box_easy (sk:secretkey) (pk:publickey) (n:nonce) (m:bytes{length m / size_block <= max_size_t}) : option (c:bytes{length c = size_tag + length m}) = let r = box_detached sk pk n m in match r with | Some (tg, c) -> Some (Seq.append tg c) | None -> None let box_open_easy_afternm (k:key) (n:nonce) (c:bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m:bytes{length m = length c - size_tag}) = let tg = Seq.slice c 0 size_tag in let e = Seq.slice c size_tag (length c) in box_open_detached_afternm k n tg e

Spec.Box.fst

val box_open_easy (pk: secretkey) (sk: publickey) (n: nonce) (c: bytes{length c >= size_tag /\ (length c - size_tag) / size_block <= max_size_t}) : option (m: bytes{length m = length c - size_tag})

Spec.Box.box_open_easy

pk: Spec.Box.secretkey -> sk: Spec.Box.publickey -> n: Spec.SecretBox.nonce -> c: Lib.ByteSequence.bytes { Lib.Sequence.length c >= Spec.SecretBox.size_tag /\ (Lib.Sequence.length c - Spec.SecretBox.size_tag) / Spec.SecretBox.size_block <= Lib.IntTypes.max_size_t } -> FStar.Pervasives.Native.option (m: Lib.ByteSequence.bytes {Lib.Sequence.length m = Lib.Sequence.length c - Spec.SecretBox.size_tag})

Prims.Tot

val serialize32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (#s: serializer p) (s32: partial_serializer32 s) (sz: nat{sz < 4294967296}) : Tot (serializer32 (serialize_fldata_strong s sz))

let serialize32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (#s: serializer p) (s32: partial_serializer32 s) (sz: nat { sz < 4294967296 } ) : Tot (serializer32 (serialize_fldata_strong s sz)) = (fun (input: parse_fldata_strong_t s sz) -> s32 input)

val serialize32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (#s: serializer p) (s32: partial_serializer32 s) (sz: nat{sz < 4294967296}) : Tot (serializer32 (serialize_fldata_strong s sz)) let serialize32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (#s: serializer p) (s32: partial_serializer32 s) (sz: nat{sz < 4294967296}) : Tot (serializer32 (serialize_fldata_strong s sz)) =

(fun (input: parse_fldata_strong_t s sz) -> s32 input)

module LowParse.SLow.FLData include LowParse.Spec.FLData include LowParse.SLow.Combinators module B32 = LowParse.Bytes32 module U32 = FStar.UInt32 inline_for_extraction let parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (parser32 (parse_fldata p sz)) = (fun (input: bytes32) -> (( if U32.lt (B32.len input) sz32 then None else match p32 (B32.b32slice input 0ul sz32) with | Some (v, consumed) -> if consumed = sz32 then begin Some (v, consumed) end else None | None -> None ) <: (res: option (t * U32.t) { parser32_correct (parse_fldata p sz) input res } ))) inline_for_extraction let parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (parser32 (parse_fldata_strong s sz)) = (fun (input: bytes32) -> (( match parse32_fldata p32 sz sz32 input with | Some (v, consumed) -> assert ( parse_fldata_strong_correct s sz (B32.reveal input) (U32.v consumed) v; Seq.length (s v) == sz ); Some ((v <: parse_fldata_strong_t s sz), consumed) | None -> None ) <: (res: option (parse_fldata_strong_t s sz * U32.t) { parser32_correct (parse_fldata_strong s sz) input res } ))) inline_for_extraction let serialize32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (#s: serializer p) (s32: partial_serializer32 s) (sz: nat { sz < 4294967296 } )

LowParse.SLow.FLData.fst

val serialize32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (#s: serializer p) (s32: partial_serializer32 s) (sz: nat{sz < 4294967296}) : Tot (serializer32 (serialize_fldata_strong s sz))

LowParse.SLow.FLData.serialize32_fldata_strong

s32: LowParse.SLow.Base.partial_serializer32 s -> sz: Prims.nat{sz < 4294967296} -> LowParse.SLow.Base.serializer32 (LowParse.Spec.FLData.serialize_fldata_strong s sz)

Prims.Tot

val size32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (size32 (serialize_fldata_strong s sz))

let size32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (size32 (serialize_fldata_strong s sz)) = size32_constant (serialize_fldata_strong s sz) sz32 ()

val size32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (size32 (serialize_fldata_strong s sz)) let size32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (size32 (serialize_fldata_strong s sz)) =

size32_constant (serialize_fldata_strong s sz) sz32 ()

module LowParse.SLow.FLData include LowParse.Spec.FLData include LowParse.SLow.Combinators module B32 = LowParse.Bytes32 module U32 = FStar.UInt32 inline_for_extraction let parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (parser32 (parse_fldata p sz)) = (fun (input: bytes32) -> (( if U32.lt (B32.len input) sz32 then None else match p32 (B32.b32slice input 0ul sz32) with | Some (v, consumed) -> if consumed = sz32 then begin Some (v, consumed) end else None | None -> None ) <: (res: option (t * U32.t) { parser32_correct (parse_fldata p sz) input res } ))) inline_for_extraction let parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (parser32 (parse_fldata_strong s sz)) = (fun (input: bytes32) -> (( match parse32_fldata p32 sz sz32 input with | Some (v, consumed) -> assert ( parse_fldata_strong_correct s sz (B32.reveal input) (U32.v consumed) v; Seq.length (s v) == sz ); Some ((v <: parse_fldata_strong_t s sz), consumed) | None -> None ) <: (res: option (parse_fldata_strong_t s sz * U32.t) { parser32_correct (parse_fldata_strong s sz) input res } ))) inline_for_extraction let serialize32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (#s: serializer p) (s32: partial_serializer32 s) (sz: nat { sz < 4294967296 } ) : Tot (serializer32 (serialize_fldata_strong s sz)) = (fun (input: parse_fldata_strong_t s sz) -> s32 input) inline_for_extraction let size32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } )

LowParse.SLow.FLData.fst

val size32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (size32 (serialize_fldata_strong s sz))

LowParse.SLow.FLData.size32_fldata_strong

s: LowParse.Spec.Base.serializer p -> sz: Prims.nat -> sz32: FStar.UInt32.t{FStar.UInt32.v sz32 == sz} -> LowParse.SLow.Base.size32 (LowParse.Spec.FLData.serialize_fldata_strong s sz)

Prims.Tot

val parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata p sz))

let parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (parser32 (parse_fldata p sz)) = (fun (input: bytes32) -> (( if U32.lt (B32.len input) sz32 then None else match p32 (B32.b32slice input 0ul sz32) with | Some (v, consumed) -> if consumed = sz32 then begin Some (v, consumed) end else None | None -> None ) <: (res: option (t * U32.t) { parser32_correct (parse_fldata p sz) input res } )))

val parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata p sz)) let parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata p sz)) =

(fun (input: bytes32) -> ((if U32.lt (B32.len input) sz32 then None else match p32 (B32.b32slice input 0ul sz32) with | Some (v, consumed) -> if consumed = sz32 then Some (v, consumed) else None | None -> None) <: (res: option (t * U32.t) {parser32_correct (parse_fldata p sz) input res})))

module LowParse.SLow.FLData include LowParse.Spec.FLData include LowParse.SLow.Combinators module B32 = LowParse.Bytes32 module U32 = FStar.UInt32 inline_for_extraction let parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } )

LowParse.SLow.FLData.fst

val parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata p sz))

LowParse.SLow.FLData.parse32_fldata

p32: LowParse.SLow.Base.parser32 p -> sz: Prims.nat -> sz32: FStar.UInt32.t{FStar.UInt32.v sz32 == sz} -> LowParse.SLow.Base.parser32 (LowParse.Spec.FLData.parse_fldata p sz)

Prims.Tot

val parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata_strong s sz))

let parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (parser32 (parse_fldata_strong s sz)) = (fun (input: bytes32) -> (( match parse32_fldata p32 sz sz32 input with | Some (v, consumed) -> assert ( parse_fldata_strong_correct s sz (B32.reveal input) (U32.v consumed) v; Seq.length (s v) == sz ); Some ((v <: parse_fldata_strong_t s sz), consumed) | None -> None ) <: (res: option (parse_fldata_strong_t s sz * U32.t) { parser32_correct (parse_fldata_strong s sz) input res } )))

val parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata_strong s sz)) let parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata_strong s sz)) =

(fun (input: bytes32) -> ((match parse32_fldata p32 sz sz32 input with | Some (v, consumed) -> assert (parse_fldata_strong_correct s sz (B32.reveal input) (U32.v consumed) v; Seq.length (s v) == sz); Some ((v <: parse_fldata_strong_t s sz), consumed) | None -> None) <: (res: option (parse_fldata_strong_t s sz * U32.t) {parser32_correct (parse_fldata_strong s sz) input res})))

module LowParse.SLow.FLData include LowParse.Spec.FLData include LowParse.SLow.Combinators module B32 = LowParse.Bytes32 module U32 = FStar.UInt32 inline_for_extraction let parse32_fldata (#k: parser_kind) (#t: Type) (#p: parser k t) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } ) : Tot (parser32 (parse_fldata p sz)) = (fun (input: bytes32) -> (( if U32.lt (B32.len input) sz32 then None else match p32 (B32.b32slice input 0ul sz32) with | Some (v, consumed) -> if consumed = sz32 then begin Some (v, consumed) end else None | None -> None ) <: (res: option (t * U32.t) { parser32_correct (parse_fldata p sz) input res } ))) inline_for_extraction let parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t { U32.v sz32 == sz } )

LowParse.SLow.FLData.fst

val parse32_fldata_strong (#k: parser_kind) (#t: Type) (#p: parser k t) (s: serializer p) (p32: parser32 p) (sz: nat) (sz32: U32.t{U32.v sz32 == sz}) : Tot (parser32 (parse_fldata_strong s sz))

LowParse.SLow.FLData.parse32_fldata_strong

s: LowParse.Spec.Base.serializer p -> p32: LowParse.SLow.Base.parser32 p -> sz: Prims.nat -> sz32: FStar.UInt32.t{FStar.UInt32.v sz32 == sz} -> LowParse.SLow.Base.parser32 (LowParse.Spec.FLData.parse_fldata_strong s sz)

Prims.Tot

val pts_to (#a: Type) (#p: Preorder.preorder a) (r: ref a p) (f: perm) (v: a) : vprop

let pts_to (#a:Type) (#p:Preorder.preorder a) (r:ref a p) (f:perm) (v:a) : vprop = to_vprop (pts_to_sl r f v)

val pts_to (#a: Type) (#p: Preorder.preorder a) (r: ref a p) (f: perm) (v: a) : vprop let pts_to (#a: Type) (#p: Preorder.preorder a) (r: ref a p) (f: perm) (v: a) : vprop =

to_vprop (pts_to_sl r f v)

(* Copyright 2020 Microsoft Research Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. *) module Steel.GhostMonotonicHigherReference open FStar.PCM open FStar.Ghost open Steel.FractionalPermission open Steel.Memory open Steel.Effect.Atomic open Steel.Effect module Preorder = FStar.Preorder /// A library for Steel references that are monotonic with respect to a user-specified preorder. /// This library builds on top of Steel.HigherReference, and is specialized to values at universe 1. /// An abstract datatype for monotonic references [@@erasable] val ref (a:Type u#1) (p:Preorder.preorder a) : Type u#0 /// The standard points to separation logic predicate val pts_to_sl (#a:Type) (#p:Preorder.preorder a) (r:ref a p) (f:perm) (v:a) : slprop u#1 /// Lifting the standard points to predicate to vprop, with a non-informative selector [@@ __steel_reduce__]

Steel.GhostMonotonicHigherReference.fsti

val pts_to (#a: Type) (#p: Preorder.preorder a) (r: ref a p) (f: perm) (v: a) : vprop

Steel.GhostMonotonicHigherReference.pts_to

r: Steel.GhostMonotonicHigherReference.ref a p -> f: Steel.FractionalPermission.perm -> v: a -> Steel.Effect.Common.vprop

Prims.Tot

let property (a:Type) = a -> prop

let property (a: Type) =

a -> prop

(* Copyright 2020 Microsoft Research Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. *) module Steel.GhostMonotonicHigherReference open FStar.PCM open FStar.Ghost open Steel.FractionalPermission open Steel.Memory open Steel.Effect.Atomic open Steel.Effect module Preorder = FStar.Preorder /// A library for Steel references that are monotonic with respect to a user-specified preorder. /// This library builds on top of Steel.HigherReference, and is specialized to values at universe 1. /// An abstract datatype for monotonic references [@@erasable] val ref (a:Type u#1) (p:Preorder.preorder a) : Type u#0 /// The standard points to separation logic predicate val pts_to_sl (#a:Type) (#p:Preorder.preorder a) (r:ref a p) (f:perm) (v:a) : slprop u#1 /// Lifting the standard points to predicate to vprop, with a non-informative selector [@@ __steel_reduce__] unfold let pts_to (#a:Type) (#p:Preorder.preorder a) (r:ref a p) (f:perm) (v:a) : vprop = to_vprop (pts_to_sl r f v) /// Allocates a reference with value [x]. We have full permission on the newly /// allocated reference. val alloc (#opened: _) (#a:Type) (p:Preorder.preorder a) (v:a) : SteelGhostT (ref a p) opened emp (fun r -> pts_to r full_perm v) /// Writes value [x] in the reference [r], as long as we have full ownership of [r] val write (#opened: _) (#a:Type) (#p:Preorder.preorder a) (#v:a) (r:ref a p) (x:a) : SteelGhost unit opened (pts_to r full_perm v) (fun v -> pts_to r full_perm x) (requires fun _ -> p v x /\ True) (ensures fun _ _ _ -> True) /// A wrapper around a predicate that depends on a value of type [a]

Steel.GhostMonotonicHigherReference.fsti

val property : a: Type -> Type

Steel.GhostMonotonicHigherReference.property

a: Type -> Type

Prims.Tot

let stable_property (#a:Type) (p:Preorder.preorder a) = fact:property a { Preorder.stable fact p }

let stable_property (#a: Type) (p: Preorder.preorder a) =

fact: property a {Preorder.stable fact p}

(* Copyright 2020 Microsoft Research Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. *) module Steel.GhostMonotonicHigherReference open FStar.PCM open FStar.Ghost open Steel.FractionalPermission open Steel.Memory open Steel.Effect.Atomic open Steel.Effect module Preorder = FStar.Preorder /// A library for Steel references that are monotonic with respect to a user-specified preorder. /// This library builds on top of Steel.HigherReference, and is specialized to values at universe 1. /// An abstract datatype for monotonic references [@@erasable] val ref (a:Type u#1) (p:Preorder.preorder a) : Type u#0 /// The standard points to separation logic predicate val pts_to_sl (#a:Type) (#p:Preorder.preorder a) (r:ref a p) (f:perm) (v:a) : slprop u#1 /// Lifting the standard points to predicate to vprop, with a non-informative selector [@@ __steel_reduce__] unfold let pts_to (#a:Type) (#p:Preorder.preorder a) (r:ref a p) (f:perm) (v:a) : vprop = to_vprop (pts_to_sl r f v) /// Allocates a reference with value [x]. We have full permission on the newly /// allocated reference. val alloc (#opened: _) (#a:Type) (p:Preorder.preorder a) (v:a) : SteelGhostT (ref a p) opened emp (fun r -> pts_to r full_perm v) /// Writes value [x] in the reference [r], as long as we have full ownership of [r] val write (#opened: _) (#a:Type) (#p:Preorder.preorder a) (#v:a) (r:ref a p) (x:a) : SteelGhost unit opened (pts_to r full_perm v) (fun v -> pts_to r full_perm x) (requires fun _ -> p v x /\ True) (ensures fun _ _ _ -> True) /// A wrapper around a predicate that depends on a value of type [a] let property (a:Type) = a -> prop /// A wrapper around a property [fact] that has been witnessed to be true and stable /// with respect to preorder [p] val witnessed (#a:Type u#1) (#p:Preorder.preorder a) (r:ref a p) (fact:property a) : Type0 /// The type of properties depending on values of type [a], and that /// are stable with respect to the preorder [p]

Steel.GhostMonotonicHigherReference.fsti

val stable_property : p: FStar.Preorder.preorder a -> Type

Steel.GhostMonotonicHigherReference.stable_property

p: FStar.Preorder.preorder a -> Type

Prims.GTot

val deref_data (#a: _) (h: HS.mem) (c: B.pointer (cell a)) : GTot a

let deref_data #a (h: HS.mem) (c: B.pointer (cell a)): GTot a = (B.deref h c).data

val deref_data (#a: _) (h: HS.mem) (c: B.pointer (cell a)) : GTot a let deref_data #a (h: HS.mem) (c: B.pointer (cell a)) : GTot a =

(B.deref h c).data

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs /// Departing from LinkedList4 here. I prefer to bolt these into the invariant /// rather than requiring on some wizard lemmas from LowStar.Monotonic.Buffer to /// deduce these. val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_pairwise_disjoint #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n) val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_live_freeable #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.live h l /\ B.freeable l /\ cells_live_freeable h next (L.tl n) val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let invariant #a h l n = cells_live_freeable h l n /\ cells_pairwise_disjoint h l n /// Normally this would be automatic and writing a custom lemma for that stuff /// would be needed only when writing an fsti, however, as stated earlier, /// recursion makes everything more difficult and this absolutely needs to be in /// scope otherwise the modifies-clause theory cannot deduce disjointness of /// fresh allocations w.r.t. the footprint. let rec invariant_loc_in_footprint (#a: Type) (h: HS.mem) (l: t a) (n: list a): Lemma (requires well_formed h l n) (ensures B.loc_in (footprint h l n) h) (decreases n) [ SMTPat (invariant h l n) ] = if B.g_is_null l then () else let next = (B.deref h l).next in invariant_loc_in_footprint h next (L.tl n) /// Another absolutely essential lemma, for which interestingly the pattern /// "invariant h1 l n" does not work, but well_formed does... I guess that's /// alright. let rec frame (#a: Type) (l: t a) (n: list a) (r: B.loc) (h0 h1: HS.mem): Lemma (requires ( well_formed h0 l n /\ invariant h0 l n /\ B.loc_disjoint r (footprint h0 l n) /\ B.modifies r h0 h1 )) (ensures ( well_formed h1 l n /\ footprint h1 l n == footprint h0 l n /\ cells h1 l n == cells h0 l n /\ invariant h1 l n )) (decreases n) [ SMTPat (well_formed h1 l n); SMTPat (B.modifies r h0 h1) ] = if B.g_is_null l then () else frame (B.deref h0 l).next (L.tl n) r h0 h1 /// Lemmas for working with linked lists /// ------------------------------------ /// /// Since it's a recursive data structure, a lot of the automated reasoning from /// LowStar.Buffer doesn't work since it requires inductions. Some helpful /// properties are therefore proved here. let rec length_functional #a (h: HS.mem) (c: t a) (l1 l2: list a): Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [ SMTPat (well_formed h c l1); SMTPat (well_formed h c l2) ] = if B.g_is_null c then () else let { next=next } = B.get h c 0 in length_functional h next (G.hide (L.tl l1)) (G.hide (L.tl l2)) /// The footprint is based on loc_addr_of_buffer so that we can write a free /// operation that operates on the footprint. However, this invalidates most of /// the helper lemmas for disjointness that were present in the previous /// iteration of this module, named LinkedList4.fst. It's ok, we bake /// disjointness directly onto the invariant and it works just as well. /// Connection between ``cells`` and ``v`` /// -------------------------------------- /// Redefining some helpers. #push-options "--ifuel 1" let rec gmap #a #b (f: a -> GTot b) (xs: list a): GTot (list b) = match xs with | [] -> [] | x :: xs -> f x :: gmap f xs /// "As we all know", right folds are the easiest to work with because they /// follow the natural structure of recursion (left-folds are evil). let rec gfold_right #a #b (f: b -> a -> GTot b) (xs: list a) (acc: b): Ghost b (requires True) (ensures fun _ -> True) (decreases xs) = match xs with | [] -> acc | x :: xs -> f (gfold_right f xs acc) x #pop-options /// Connecting ``v`` and ``cells``. /// /// See ``tests/Wireguard.fst`` for why going through gmap is important and how /// to structure your definitions (should you need to reason about ``cells``) in /// a way that will make your life easier.

LowStar.Lib.LinkedList.fst

val deref_data (#a: _) (h: HS.mem) (c: B.pointer (cell a)) : GTot a

LowStar.Lib.LinkedList.deref_data

h: FStar.Monotonic.HyperStack.mem -> c: LowStar.Buffer.pointer (LowStar.Lib.LinkedList.cell a) -> Prims.GTot a

Prims.Ghost

val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

let invariant #a h l n = cells_live_freeable h l n /\ cells_pairwise_disjoint h l n

val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let invariant #a h l n =

cells_live_freeable h l n /\ cells_pairwise_disjoint h l n

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs /// Departing from LinkedList4 here. I prefer to bolt these into the invariant /// rather than requiring on some wizard lemmas from LowStar.Monotonic.Buffer to /// deduce these. val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_pairwise_disjoint #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n) val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_live_freeable #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.live h l /\ B.freeable l /\ cells_live_freeable h next (L.tl n) val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

LowStar.Lib.LinkedList.fst

val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

LowStar.Lib.LinkedList.invariant

h: FStar.Monotonic.HyperStack.mem -> l: LowStar.Lib.LinkedList.t a -> n: Prims.list a -> Prims.Ghost Type0

Prims.Ghost

val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

let rec cells_live_freeable #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.live h l /\ B.freeable l /\ cells_live_freeable h next (L.tl n)

val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_live_freeable #_ h l n =

if B.g_is_null l then True else let next = (B.deref h l).next in B.live h l /\ B.freeable l /\ cells_live_freeable h next (L.tl n)

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs /// Departing from LinkedList4 here. I prefer to bolt these into the invariant /// rather than requiring on some wizard lemmas from LowStar.Monotonic.Buffer to /// deduce these. val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_pairwise_disjoint #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n) val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

LowStar.Lib.LinkedList.fst

val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

LowStar.Lib.LinkedList.cells_live_freeable

h: FStar.Monotonic.HyperStack.mem -> l: LowStar.Lib.LinkedList.t a -> n: Prims.list a -> Prims.Ghost Type0

Prims.Ghost

val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

let rec cells_pairwise_disjoint #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n)

val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_pairwise_disjoint #_ h l n =

if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n)

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs /// Departing from LinkedList4 here. I prefer to bolt these into the invariant /// rather than requiring on some wizard lemmas from LowStar.Monotonic.Buffer to /// deduce these. val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

LowStar.Lib.LinkedList.fst

val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n)

LowStar.Lib.LinkedList.cells_pairwise_disjoint

h: FStar.Monotonic.HyperStack.mem -> l: LowStar.Lib.LinkedList.t a -> n: Prims.list a -> Prims.Ghost Type0

Prims.GTot

val well_formed (#a: _) (h: HS.mem) (c: t a) (l: list a) : GTot Type0 (decreases l)

let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) ))

val well_formed (#a: _) (h: HS.mem) (c: t a) (l: list a) : GTot Type0 (decreases l) let rec well_formed #a (h: HS.mem) (c: t a) (l: list a) : GTot Type0 (decreases l) =

B.live h c /\ (match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ (let { data = data ; next = next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q)))

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``.

LowStar.Lib.LinkedList.fst

val well_formed (#a: _) (h: HS.mem) (c: t a) (l: list a) : GTot Type0 (decreases l)

LowStar.Lib.LinkedList.well_formed

h: FStar.Monotonic.HyperStack.mem -> c: LowStar.Lib.LinkedList.t a -> l: Prims.list a -> Prims.GTot Type0

Prims.Ghost

val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n)

let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs

val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n =

if B.g_is_null l then B.loc_none else let { next = next } = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n)

LowStar.Lib.LinkedList.fst

val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n)

LowStar.Lib.LinkedList.footprint

h: FStar.Monotonic.HyperStack.mem -> l: LowStar.Lib.LinkedList.t a -> n: Prims.list a -> Prims.Ghost LowStar.Monotonic.Buffer.loc

Prims.GTot

val gmap (#a #b: _) (f: (a -> GTot b)) (xs: list a) : GTot (list b)

let rec gmap #a #b (f: a -> GTot b) (xs: list a): GTot (list b) = match xs with | [] -> [] | x :: xs -> f x :: gmap f xs

val gmap (#a #b: _) (f: (a -> GTot b)) (xs: list a) : GTot (list b) let rec gmap #a #b (f: (a -> GTot b)) (xs: list a) : GTot (list b) =

match xs with | [] -> [] | x :: xs -> f x :: gmap f xs

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs /// Departing from LinkedList4 here. I prefer to bolt these into the invariant /// rather than requiring on some wizard lemmas from LowStar.Monotonic.Buffer to /// deduce these. val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_pairwise_disjoint #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n) val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_live_freeable #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.live h l /\ B.freeable l /\ cells_live_freeable h next (L.tl n) val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let invariant #a h l n = cells_live_freeable h l n /\ cells_pairwise_disjoint h l n /// Normally this would be automatic and writing a custom lemma for that stuff /// would be needed only when writing an fsti, however, as stated earlier, /// recursion makes everything more difficult and this absolutely needs to be in /// scope otherwise the modifies-clause theory cannot deduce disjointness of /// fresh allocations w.r.t. the footprint. let rec invariant_loc_in_footprint (#a: Type) (h: HS.mem) (l: t a) (n: list a): Lemma (requires well_formed h l n) (ensures B.loc_in (footprint h l n) h) (decreases n) [ SMTPat (invariant h l n) ] = if B.g_is_null l then () else let next = (B.deref h l).next in invariant_loc_in_footprint h next (L.tl n) /// Another absolutely essential lemma, for which interestingly the pattern /// "invariant h1 l n" does not work, but well_formed does... I guess that's /// alright. let rec frame (#a: Type) (l: t a) (n: list a) (r: B.loc) (h0 h1: HS.mem): Lemma (requires ( well_formed h0 l n /\ invariant h0 l n /\ B.loc_disjoint r (footprint h0 l n) /\ B.modifies r h0 h1 )) (ensures ( well_formed h1 l n /\ footprint h1 l n == footprint h0 l n /\ cells h1 l n == cells h0 l n /\ invariant h1 l n )) (decreases n) [ SMTPat (well_formed h1 l n); SMTPat (B.modifies r h0 h1) ] = if B.g_is_null l then () else frame (B.deref h0 l).next (L.tl n) r h0 h1 /// Lemmas for working with linked lists /// ------------------------------------ /// /// Since it's a recursive data structure, a lot of the automated reasoning from /// LowStar.Buffer doesn't work since it requires inductions. Some helpful /// properties are therefore proved here. let rec length_functional #a (h: HS.mem) (c: t a) (l1 l2: list a): Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [ SMTPat (well_formed h c l1); SMTPat (well_formed h c l2) ] = if B.g_is_null c then () else let { next=next } = B.get h c 0 in length_functional h next (G.hide (L.tl l1)) (G.hide (L.tl l2)) /// The footprint is based on loc_addr_of_buffer so that we can write a free /// operation that operates on the footprint. However, this invalidates most of /// the helper lemmas for disjointness that were present in the previous /// iteration of this module, named LinkedList4.fst. It's ok, we bake /// disjointness directly onto the invariant and it works just as well. /// Connection between ``cells`` and ``v`` /// -------------------------------------- /// Redefining some helpers. #push-options "--ifuel 1"

LowStar.Lib.LinkedList.fst

val gmap (#a #b: _) (f: (a -> GTot b)) (xs: list a) : GTot (list b)

LowStar.Lib.LinkedList.gmap

f: (_: a -> Prims.GTot b) -> xs: Prims.list a -> Prims.GTot (Prims.list b)

Prims.Ghost

val cells (#a: _) (h: HS.mem) (c: t a) (l: list a) : Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l)

let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l)

val cells (#a: _) (h: HS.mem) (c: t a) (l: list a) : Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) let rec cells #a (h: HS.mem) (c: t a) (l: list a) : Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) =

if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l)

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l)

LowStar.Lib.LinkedList.fst

val cells (#a: _) (h: HS.mem) (c: t a) (l: list a) : Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l)

LowStar.Lib.LinkedList.cells

h: FStar.Monotonic.HyperStack.mem -> c: LowStar.Lib.LinkedList.t a -> l: Prims.list a -> Prims.Ghost (Prims.list (LowStar.Buffer.pointer (LowStar.Lib.LinkedList.cell a)))

Prims.Ghost

val gfold_right (#a #b: _) (f: (b -> a -> GTot b)) (xs: list a) (acc: b) : Ghost b (requires True) (ensures fun _ -> True) (decreases xs)

let rec gfold_right #a #b (f: b -> a -> GTot b) (xs: list a) (acc: b): Ghost b (requires True) (ensures fun _ -> True) (decreases xs) = match xs with | [] -> acc | x :: xs -> f (gfold_right f xs acc) x

val gfold_right (#a #b: _) (f: (b -> a -> GTot b)) (xs: list a) (acc: b) : Ghost b (requires True) (ensures fun _ -> True) (decreases xs) let rec gfold_right #a #b (f: (b -> a -> GTot b)) (xs: list a) (acc: b) : Ghost b (requires True) (ensures fun _ -> True) (decreases xs) =

match xs with | [] -> acc | x :: xs -> f (gfold_right f xs acc) x

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs /// Departing from LinkedList4 here. I prefer to bolt these into the invariant /// rather than requiring on some wizard lemmas from LowStar.Monotonic.Buffer to /// deduce these. val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_pairwise_disjoint #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n) val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_live_freeable #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.live h l /\ B.freeable l /\ cells_live_freeable h next (L.tl n) val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let invariant #a h l n = cells_live_freeable h l n /\ cells_pairwise_disjoint h l n /// Normally this would be automatic and writing a custom lemma for that stuff /// would be needed only when writing an fsti, however, as stated earlier, /// recursion makes everything more difficult and this absolutely needs to be in /// scope otherwise the modifies-clause theory cannot deduce disjointness of /// fresh allocations w.r.t. the footprint. let rec invariant_loc_in_footprint (#a: Type) (h: HS.mem) (l: t a) (n: list a): Lemma (requires well_formed h l n) (ensures B.loc_in (footprint h l n) h) (decreases n) [ SMTPat (invariant h l n) ] = if B.g_is_null l then () else let next = (B.deref h l).next in invariant_loc_in_footprint h next (L.tl n) /// Another absolutely essential lemma, for which interestingly the pattern /// "invariant h1 l n" does not work, but well_formed does... I guess that's /// alright. let rec frame (#a: Type) (l: t a) (n: list a) (r: B.loc) (h0 h1: HS.mem): Lemma (requires ( well_formed h0 l n /\ invariant h0 l n /\ B.loc_disjoint r (footprint h0 l n) /\ B.modifies r h0 h1 )) (ensures ( well_formed h1 l n /\ footprint h1 l n == footprint h0 l n /\ cells h1 l n == cells h0 l n /\ invariant h1 l n )) (decreases n) [ SMTPat (well_formed h1 l n); SMTPat (B.modifies r h0 h1) ] = if B.g_is_null l then () else frame (B.deref h0 l).next (L.tl n) r h0 h1 /// Lemmas for working with linked lists /// ------------------------------------ /// /// Since it's a recursive data structure, a lot of the automated reasoning from /// LowStar.Buffer doesn't work since it requires inductions. Some helpful /// properties are therefore proved here. let rec length_functional #a (h: HS.mem) (c: t a) (l1 l2: list a): Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [ SMTPat (well_formed h c l1); SMTPat (well_formed h c l2) ] = if B.g_is_null c then () else let { next=next } = B.get h c 0 in length_functional h next (G.hide (L.tl l1)) (G.hide (L.tl l2)) /// The footprint is based on loc_addr_of_buffer so that we can write a free /// operation that operates on the footprint. However, this invalidates most of /// the helper lemmas for disjointness that were present in the previous /// iteration of this module, named LinkedList4.fst. It's ok, we bake /// disjointness directly onto the invariant and it works just as well. /// Connection between ``cells`` and ``v`` /// -------------------------------------- /// Redefining some helpers. #push-options "--ifuel 1" let rec gmap #a #b (f: a -> GTot b) (xs: list a): GTot (list b) = match xs with | [] -> [] | x :: xs -> f x :: gmap f xs /// "As we all know", right folds are the easiest to work with because they /// follow the natural structure of recursion (left-folds are evil). let rec gfold_right #a #b (f: b -> a -> GTot b) (xs: list a) (acc: b): Ghost b (requires True) (ensures fun _ -> True) (decreases xs)

LowStar.Lib.LinkedList.fst

val gfold_right (#a #b: _) (f: (b -> a -> GTot b)) (xs: list a) (acc: b) : Ghost b (requires True) (ensures fun _ -> True) (decreases xs)

LowStar.Lib.LinkedList.gfold_right

f: (_: b -> _: a -> Prims.GTot b) -> xs: Prims.list a -> acc: b -> Prims.Ghost b

FStar.Pervasives.Lemma

val length_functional (#a: _) (h: HS.mem) (c: t a) (l1 l2: list a) : Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [SMTPat (well_formed h c l1); SMTPat (well_formed h c l2)]

let rec length_functional #a (h: HS.mem) (c: t a) (l1 l2: list a): Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [ SMTPat (well_formed h c l1); SMTPat (well_formed h c l2) ] = if B.g_is_null c then () else let { next=next } = B.get h c 0 in length_functional h next (G.hide (L.tl l1)) (G.hide (L.tl l2))

val length_functional (#a: _) (h: HS.mem) (c: t a) (l1 l2: list a) : Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [SMTPat (well_formed h c l1); SMTPat (well_formed h c l2)] let rec length_functional #a (h: HS.mem) (c: t a) (l1: list a) (l2: list a) : Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [SMTPat (well_formed h c l1); SMTPat (well_formed h c l2)] =

if B.g_is_null c then () else let { next = next } = B.get h c 0 in length_functional h next (G.hide (L.tl l1)) (G.hide (L.tl l2))

module LowStar.Lib.LinkedList /// This module, oftentimes referred to as LL1 in other parts of the /// documentation, provides a low-level view over a linked list. Unless you /// intend on modifying the structure of the linked list (e.g. removing cells) /// or iterating over each cell, your are probably better off using LL2. /// /// This module is intentionally not relying on a tight abstraction, to i) permit /// direct-style iteration by clients and ii) allow stating some SMTPat lemmas /// only on LL1 rather than replicating them in LL2 (going from LL2 to LL1 can /// happen automatically at the SMT level since LL2 does not have an fsti either). /// /// Some open questions relative to the design of this module: /// - should ``v`` be defined directly in terms of ``cells`` rather than have a /// recursive definition along with an equivalence lemma? /// - should ``footprint`` be defined directly in terms of ``cells`` rather than /// have a recursive definition along with an equivalence lemma? /// - is it worth the trouble defining a footprint? my intuition is that it's /// fine and allows some clients to do very precise reasoning -- other modules /// (e.g. AssocList), when establishing abstraction boundaries, can simplify /// things and get rid of the precise footprint reasoning in favor of a static /// region-based footprint /// /// Some remaining work items: /// - switch to C.Loops.while open LowStar.BufferOps module B = LowStar.Buffer module HS = FStar.HyperStack module G = FStar.Ghost module L = FStar.List.Tot module U32 = FStar.UInt32 module ST = FStar.HyperStack.ST open FStar.HyperStack.ST /// Breaking from my own recommendation here... using fuel 1 / ifuel 1 since /// everything does recursive list reasoning. #set-options "--__no_positivity --fuel 1 --ifuel 1" /// Definition of the Low* type /// --------------------------- noeq type t (a: Type0) = B.pointer_or_null (cell a) and cell (a: Type0) = { next: t a; data: a; } /// Unlike the canonical style that associates a ``v`` function to any stateful /// representation, we use a relation here. Writing a function is just /// impossible, since we can't prove termination of ``v`` owing to the fact that /// there may be an infinite number of cells in the heap. /// /// LL2 is the module that switches to the function style. /// /// Note: no need to use erased here for ``l`` since the function is already in ``GTot``. let rec well_formed #a (h: HS.mem) (c: t a) (l: list a): GTot Type0 (decreases l) = B.live h c /\ ( match l with | [] -> B.g_is_null c | a :: q -> B.length c == 1 /\ ( let { data=data; next=next } = B.get h c 0 in a == data /\ well_formed h next (G.hide q) )) /// Precise reasoning via the cells predicate /// ----------------------------------------- /// /// The modifies clauses are given either on the footprint of the list, or on a /// region that includes the footprint of the list (higher up the stack, e.g. /// LL2). This is good, but does not rule out "stupid" implementations that /// might re-allocate every single list cell when, say, doing a pop. /// /// For advanced usages which take pointers directly to individual list cells, /// it's important to rule out these cases. We thus define the ``cells`` /// predicate for that purpose. let rec cells #a (h: HS.mem) (c: t a) (l: list a): Ghost (list (B.pointer (cell a))) (requires well_formed h c l) (ensures fun _ -> True) (decreases l) = if B.g_is_null c then [] else c :: cells h (B.deref h c).next (List.Tot.tl l) /// A missing bit of automated reasoning /// ------------------------------------ /// This should be absolutely trivial, yet, because there's no pattern on /// null_unique, we have to do the case analysis and the decomposition /// ourselves. This is quite tedious, as it usually takes a while (at least it /// did for me!) to realize that this property does not hold automatically. /// /// I'm setting an SMTPat on this lemma because it's absolutely impossible to /// get any work done without it. let same_cells_same_pointer #a (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a): Lemma (requires ( well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures ( ll0 == ll1)) [ SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1) ] = if B.g_is_null ll0 && B.g_is_null ll1 then begin B.null_unique ll0; B.null_unique ll1 end else if not (B.g_is_null ll0) && not (B.g_is_null ll1) then begin () end else false_elim () /// Classic stateful reasoning lemmas /// --------------------------------- /// /// This essentially follows ``stateful``, the type class of a mutable piece of /// state defined using the modifies-theory of Low*v2 and equipped with the /// right lemmas to enable usage by clients. See /// hacl-star/code/streaming/Hacl.Streaming.Interface.fst for more context. val footprint: (#a: Type) -> (h: HS.mem) -> (l: t a) -> (n: list a) -> Ghost B.loc (requires (well_formed h l n)) (ensures (fun refs -> True)) (decreases n) let rec footprint #a h l n = if B.g_is_null l then B.loc_none else let {next = next} = B.get h l 0 in let refs = footprint h next (G.hide (L.tl n)) in B.loc_union (B.loc_addr_of_buffer l) refs /// Departing from LinkedList4 here. I prefer to bolt these into the invariant /// rather than requiring on some wizard lemmas from LowStar.Monotonic.Buffer to /// deduce these. val cells_pairwise_disjoint: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_pairwise_disjoint #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.loc_disjoint (B.loc_addr_of_buffer l) (footprint h next (L.tl n)) /\ cells_pairwise_disjoint h next (L.tl n) val cells_live_freeable: #a:Type -> h:HS.mem -> l:t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let rec cells_live_freeable #_ h l n = if B.g_is_null l then True else let next = (B.deref h l).next in B.live h l /\ B.freeable l /\ cells_live_freeable h next (L.tl n) val invariant: #a:Type -> h:HS.mem -> l: t a -> n:list a -> Ghost Type0 (requires well_formed h l n) (ensures fun _ -> True) (decreases n) let invariant #a h l n = cells_live_freeable h l n /\ cells_pairwise_disjoint h l n /// Normally this would be automatic and writing a custom lemma for that stuff /// would be needed only when writing an fsti, however, as stated earlier, /// recursion makes everything more difficult and this absolutely needs to be in /// scope otherwise the modifies-clause theory cannot deduce disjointness of /// fresh allocations w.r.t. the footprint. let rec invariant_loc_in_footprint (#a: Type) (h: HS.mem) (l: t a) (n: list a): Lemma (requires well_formed h l n) (ensures B.loc_in (footprint h l n) h) (decreases n) [ SMTPat (invariant h l n) ] = if B.g_is_null l then () else let next = (B.deref h l).next in invariant_loc_in_footprint h next (L.tl n) /// Another absolutely essential lemma, for which interestingly the pattern /// "invariant h1 l n" does not work, but well_formed does... I guess that's /// alright. let rec frame (#a: Type) (l: t a) (n: list a) (r: B.loc) (h0 h1: HS.mem): Lemma (requires ( well_formed h0 l n /\ invariant h0 l n /\ B.loc_disjoint r (footprint h0 l n) /\ B.modifies r h0 h1 )) (ensures ( well_formed h1 l n /\ footprint h1 l n == footprint h0 l n /\ cells h1 l n == cells h0 l n /\ invariant h1 l n )) (decreases n) [ SMTPat (well_formed h1 l n); SMTPat (B.modifies r h0 h1) ] = if B.g_is_null l then () else frame (B.deref h0 l).next (L.tl n) r h0 h1 /// Lemmas for working with linked lists /// ------------------------------------ /// /// Since it's a recursive data structure, a lot of the automated reasoning from /// LowStar.Buffer doesn't work since it requires inductions. Some helpful /// properties are therefore proved here. let rec length_functional #a (h: HS.mem) (c: t a) (l1 l2: list a): Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1))

LowStar.Lib.LinkedList.fst

val length_functional (#a: _) (h: HS.mem) (c: t a) (l1 l2: list a) : Lemma (requires (well_formed h c l1 /\ well_formed h c l2)) (ensures (l1 == l2)) (decreases (G.reveal l1)) [SMTPat (well_formed h c l1); SMTPat (well_formed h c l2)]

LowStar.Lib.LinkedList.length_functional

h: FStar.Monotonic.HyperStack.mem -> c: LowStar.Lib.LinkedList.t a -> l1: Prims.list a -> l2: Prims.list a -> FStar.Pervasives.Lemma (requires LowStar.Lib.LinkedList.well_formed h c l1 /\ LowStar.Lib.LinkedList.well_formed h c l2) (ensures l1 == l2) (decreases FStar.Ghost.reveal (FStar.Ghost.hide l1)) [ SMTPat (LowStar.Lib.LinkedList.well_formed h c l1); SMTPat (LowStar.Lib.LinkedList.well_formed h c l2) ]

FStar.Pervasives.Lemma

val same_cells_same_pointer (#a: _) (h0 h1: HS.mem) (ll0 ll1: t a) (l0 l1: list a) : Lemma (requires (well_formed h0 ll0 l0 /\ well_formed h1 ll1 l1 /\ cells h0 ll0 l0 == cells h1 ll1 l1)) (ensures (ll0 == ll1)) [SMTPat (cells h0 ll0 l0); SMTPat (cells h1 ll1 l1)]