Datasets:

Reset23

/

the-stack-v2-c

like 0

21a1c1dff3c703e4bb12e102ab73d45f989b912e

6a2096c97357b1d66e0c5838cbbdb8cfefb19c27

/up1.01/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h

ce80f14b823c77009df720e009646309548a18e6

no_license

NovarLo/upprj

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d1fdebe19476f3d94adba2e9e1c5b11d536a9143

refs/heads/master

UTF-8

C

h

/* * ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.h * @author MCD Application Team * @version V1.1.0 * @date 19-June-2014 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_PCD_EX_H #define __STM32F4xx_HAL_PCD_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" /* * @addtogroup STM32F4xx_HAL_Driver * @{ */ /* * @addtogroup PCDEx * @{ */ /* Exported functions --------------------------------------------------------*/ /* Peripheral Extended functions *********************************************/ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); /* * * @} */ /* * * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_PCD_EX_H */ /* *********************** (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/other_tasks/wt_cpp_api/call_simple_function/rtwtypes.h

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no_license

AlexG31/ProjectSwiper

fb6de85eaabd8264e803e79dbf2bea5760132d60

c9f88004c31ef0e37a04a30c01603e09e0333616

refs/heads/master

UTF-8

C

h

/* * File: rtwtypes.h * * MATLAB Coder version : 2.6 * C/C++ source code generated on : 11-Nov-2016 14:17:02 */ #ifndef __RTWTYPES_H__ #define __RTWTYPES_H__ #ifndef __TMWTYPES__ #define __TMWTYPES__ /*=======================================================================* * Target hardware information * Device type: Generic->MATLAB Host Computer * Number of bits: char: 8 short: 16 int: 32 * long: 64 long long: 64 * native word size: 64 * Byte ordering: LittleEndian * Signed integer division rounds to: Zero * Shift right on a signed integer as arithmetic shift: on *=======================================================================*/ /*=======================================================================* * Fixed width word size data types: * * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * * real32_T, real64_T - 32 and 64 bit floating point numbers * *=======================================================================*/ typedef signed char int8_T; typedef unsigned char uint8_T; typedef short int16_T; typedef unsigned short uint16_T; typedef int int32_T; typedef unsigned int uint32_T; typedef long int64_T; typedef unsigned long uint64_T; typedef float real32_T; typedef double real64_T; /*===========================================================================* * Generic type definitions: real_T, time_T, boolean_T, int_T, uint_T, * * ulong_T, ulonglong_T, char_T and byte_T. * *===========================================================================*/ typedef double real_T; typedef double time_T; typedef unsigned char boolean_T; typedef int int_T; typedef unsigned int uint_T; typedef unsigned long ulong_T; typedef unsigned long long ulonglong_T; typedef char char_T; typedef char_T byte_T; /*===========================================================================* * Complex number type definitions * *===========================================================================*/ #define CREAL_T typedef struct { real32_T re; real32_T im; } creal32_T; typedef struct { real64_T re; real64_T im; } creal64_T; typedef struct { real_T re; real_T im; } creal_T; typedef struct { int8_T re; int8_T im; } cint8_T; typedef struct { uint8_T re; uint8_T im; } cuint8_T; typedef struct { int16_T re; int16_T im; } cint16_T; typedef struct { uint16_T re; uint16_T im; } cuint16_T; typedef struct { int32_T re; int32_T im; } cint32_T; typedef struct { uint32_T re; uint32_T im; } cuint32_T; typedef struct { int64_T re; int64_T im; } cint64_T; typedef struct { uint64_T re; uint64_T im; } cuint64_T; /*=======================================================================* * Min and Max: * * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * *=======================================================================*/ #define MAX_int8_T ((int8_T)(127)) #define MIN_int8_T ((int8_T)(-128)) #define MAX_uint8_T ((uint8_T)(255)) #define MIN_uint8_T ((uint8_T)(0)) #define MAX_int16_T ((int16_T)(32767)) #define MIN_int16_T ((int16_T)(-32768)) #define MAX_uint16_T ((uint16_T)(65535)) #define MIN_uint16_T ((uint16_T)(0)) #define MAX_int32_T ((int32_T)(2147483647)) #define MIN_int32_T ((int32_T)(-2147483647-1)) #define MAX_uint32_T ((uint32_T)(0xFFFFFFFFU)) #define MIN_uint32_T ((uint32_T)(0)) #define MAX_int64_T ((int64_T)(9223372036854775807L)) #define MIN_int64_T ((int64_T)(-9223372036854775807L-1L)) #define MAX_uint64_T ((uint64_T)(0xFFFFFFFFFFFFFFFFUL)) #define MIN_uint64_T ((uint64_T)(0UL)) /* Logical type definitions */ #if !defined(__cplusplus) && !defined(__true_false_are_keywords) # ifndef false # define false (0U) # endif # ifndef true # define true (1U) # endif #endif /* * Maximum length of a MATLAB identifier (function/variable) * including the null-termination character. Referenced by * rt_logging.c and rt_matrx.c. */ #define TMW_NAME_LENGTH_MAX 64 #endif #endif /* * File trailer for rtwtypes.h * * [EOF] */

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/usdmayautils/AL/usdmaya/utils/Api.h

ad294c3d6e0776eacfb942d13fd6dbe46b857b95

permissive

wengn/AL_USDMaya

a0385d98697bd6568759d9176c0f7aa004b89e1b

5c4ccd64be53554c3734a1406a0a5dc7240d9275

refs/heads/master

NOASSERTION

C++

UTF-8

C

h

// // Copyright 2017 Animal Logic // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License.// // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // #if defined _WIN32 || defined __CYGWIN__ #ifdef AL_USDMAYA_UTILS_EXPORT #ifdef __GNUC__ #define AL_USDMAYA_UTILS_PUBLIC __attribute__ ((dllexport)) #else #define AL_USDMAYA_UTILS_PUBLIC __declspec(dllexport) #endif #else #ifdef __GNUC__ #define AL_USDMAYA_UTILS_PUBLIC __attribute__ ((dllimport)) #else #define AL_USDMAYA_UTILS_PUBLIC __declspec(dllimport) #endif #endif #define AL_USDMAYA_UTILS_LOCAL #else #if __GNUC__ >= 4 #define AL_USDMAYA_UTILS_PUBLIC __attribute__ ((visibility ("default"))) #define AL_USDMAYA_UTILS_LOCAL __attribute__ ((visibility ("hidden"))) #else #define AL_USDMAYA_UTILS_PUBLIC #define AL_USDMAYA_UTILS_LOCAL #endif #endif

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/POW.c

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no_license

snehasss/snehana

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refs/heads/master

UTF-8

C

c

#include <stdio.h> int power_of_2(unsigned int); int b[32] = {0}, j = 0, n, i, count = 0; void main() { unsigned int num; printf("enter value\n"); scanf("%d", &num); power_of_2(num); if (count == 1) printf("YES\n"); else printf("NO\n"); } int power_of_2(unsigned int num) { while (num != 0) { n = num % 2; if (n == 1) count++; num = num / 2; } }

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/module/module/hello/hello.c

23322eb90d18d57470e7c6f71030f11f12b56892

no_license

99003159/Embedded-Linux

4d704f43adbdf310f899370ec6a44aae533c0a4a

fffec02999afb24a13180eb1ff2bfaa491bd2f6b

refs/heads/master

UTF-8

C

c

//hello.c #include<linux/init.h> #include<linux/module.h> #include<linux/kernel.h> int choice=1; int*ptr=NULL; module_param(choice,int,S_IRUGO); void noinline do_write(void) { int i,dummy=0; for(i=1;i<=10;i++) //dummy code dummy+=i; *ptr = 100; //suspected code printk("end of do_write\n"); } void noinline do_read(void) { int val,i,dummy; for(i=1;i<=10;i++) //dummy code dummy+=i; val = *ptr; //suspected code printk("val is %d\n",*ptr); } static int __init hello_init(void) { //init_module printk("Hello World..welcome\n"); if(choice==1) do_write(); else do_read(); return 0; } static void __exit hello_exit(void) { printk("Bye,Leaving the world\n"); } module_init(hello_init); module_exit(hello_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Sriram"); MODULE_DESCRIPTION("A simple module");

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/shell_src/checker_v3.c

53f37c5387e1df13b87a4d2ebeb4ecb77bdb2457

no_license

omarmdh/42sh_alias_builting

f949fb8e1ca1b555fa859eb134d41c1374c21003

d8b83387c5bf060e59a8d61676bf177aa5d52f8e

refs/heads/main

UTF-8

C

c

/* ************************************************************************** */ /* */ /* ::: :::::::: */ /* checker_v3.c :+: :+: :+: */ /* +:+ +:+ +:+ */ /* By: hiantrin <[email protected]> +#+ +:+ +#+ */ /* +#+#+#+#+#+ +#+ */ /* Created: 2020/10/23 03:26:27 by hiantrin #+# #+# */ /* Updated: 2020/10/31 19:09:49 by ommadhi ### ########.fr */ /* */ /* ************************************************************************** */ #include "../includes/sh.h" void help_to_finish_the_pipe(char **line) { char *new; char *str; int i; i = 0; new = NULL; while (!i || search_no_espace(new) == 0) { i++; ft_strdel(&new); new = my_readline(&g_his, "> "); } if (!new && i) ft_strdel(&line[0]); str = line[0]; line[0] = ft_strjoin(line[0], new); free(new); free(str); } int ft_filter_2eme(int len, char *cont, int index) { len++; while (cont[len]) { if (cont[len] == 92) len++; else if (cont[len] == index) return (len); if (cont[len] != '\0') len++; } return (0); } char *read_quote(char *cont, int index) { char *lire; char *tmp; char *tmp2; lire = NULL; if (index == 39) lire = my_readline(&g_his, "quote>"); else lire = my_readline(&g_his, "dquote>"); if (!lire) { ft_strdel(&cont); return (NULL); } tmp = ft_strjoin(cont, "\n"); tmp2 = ft_strjoin(tmp, lire); free(cont); ft_strdel(&tmp); ft_strdel(&lire); return (tmp2); } char *ft_filter_quote(char *cont, int c) { int resul; int len; len = 0; resul = 0; while (cont[len]) { if (cont[len] == 92) len++; else if (cont[len] == 34 || cont[len] == 39) { c = ((int)cont[len]); if ((resul = ft_filter_2eme(len, cont, c)) == 0) cont = read_quote(cont, c); if (!cont) return (NULL); len = -1; if (resul != 0) len = resul; } if (cont[len] != '\0' || len == -1) len++; } return (cont); }

c84f66bcda8619484708cdb90e107c651de10bcf

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/ti_tools/edma3_lld_02_11_10_09/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c

eb4007698522a5a45ea10e319664cea8d423785d

no_license

pamsimochen/hardwork

5e05154fac35a0aacc0f8b64c21b2ca767fd4a3d

1e0a4cafdd1722eb58c4261bad68e602352f2079

refs/heads/master

UTF-8

C

c

/* * sample_tda2xx_cfg.c * * SoC specific EDMA3 hardware related information like number of transfer * controllers, various interrupt ids etc. It is used while interrupts * enabling / disabling. It needs to be ported for different SoCs. * * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include <ti/sdo/edma3/drv/edma3_drv.h> #ifdef BUILD_TDA2XX_IPU #include <ti/sysbios/family/arm/ducati/Core.h> #endif /* Number of EDMA3 controllers present in the system */ #define NUM_EDMA3_INSTANCES 2u const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; /* Number of DSPs present in the system */ #define NUM_DSPS 1u const unsigned int numDsps = NUM_DSPS; /* Determine the processor id by reading DNUM register. */ /* Statically allocate the region numbers with cores. */ int myCoreNum; #define PID0_ADDRESS 0xE00FFFE0 #define CORE_ID_C0 0x0 #define CORE_ID_C1 0x1 unsigned short determineProcId() { unsigned short regionNo = numEdma3Instances; #ifdef BUILD_TDA2XX_DSP extern __cregister volatile unsigned int DNUM; #endif myCoreNum = numDsps; #ifdef BUILD_TDA2XX_MPU asm (" push {r0-r2} \n\t" " MRC p15, 0, r0, c0, c0, 5\n\t" " LDR r1, =myCoreNum\n\t" " STR r0, [r1]\n\t" " pop {r0-r2}\n\t"); if((myCoreNum & 0x03) == 1) regionNo = 1; else regionNo = 0; #elif defined(BUILD_TDA2XX_IPU) myCoreNum = (*(unsigned int *)(PID0_ADDRESS)); if(Core_getIpuId() == 1){ if(myCoreNum == CORE_ID_C0) regionNo = 4; else if (myCoreNum == CORE_ID_C1) regionNo = 5; } if(Core_getIpuId() == 2){ if(myCoreNum == CORE_ID_C0) regionNo = 6; else if (myCoreNum == CORE_ID_C1) regionNo = 7; } #elif defined BUILD_TDA2XX_DSP myCoreNum = DNUM; if(myCoreNum == 0) regionNo = 2; else regionNo = 3; #endif return regionNo; } signed char* getGlobalAddr(signed char* addr) { return (addr); /* The address is already a global address */ } unsigned short isGblConfigRequired(unsigned int dspNum) { (void) dspNum; return 1; } /* Semaphore handles */ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; /** Number of PaRAM Sets available */ #define EDMA3_NUM_PARAMSET (512u) /** Number of TCCS available */ #define EDMA3_NUM_TCC (64u) /** Number of DMA Channels available */ #define EDMA3_NUM_DMA_CHANNELS (64u) /** Number of QDMA Channels available */ #define EDMA3_NUM_QDMA_CHANNELS (8u) /** Number of Event Queues available */ #define EDMA3_NUM_EVTQUE (4u) /** Number of Transfer Controllers available */ #define EDMA3_NUM_TC (2u) /** Number of Regions */ #define EDMA3_NUM_REGIONS (8u) /** Interrupt no. for Transfer Completion */ #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u) #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u) #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u) #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u) /** Based on the interrupt number to be mapped define the XBAR instance number */ #define COMPLETION_INT_A15_XBAR_INST_NO (29u) #define COMPLETION_INT_DSP_XBAR_INST_NO (7u) #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u) #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u) /** Interrupt no. for CC Error */ #define EDMA3_CC_ERROR_INT_A15 (67u) #define EDMA3_CC_ERROR_INT_DSP (39u) #define EDMA3_CC_ERROR_INT_IPU (35u) /** Based on the interrupt number to be mapped define the XBAR instance number */ #define CC_ERROR_INT_A15_XBAR_INST_NO (30u) #define CC_ERROR_INT_DSP_XBAR_INST_NO (8u) #define CC_ERROR_INT_IPU_XBAR_INST_NO (13u) /** Interrupt no. for TCs Error */ #define EDMA3_TC0_ERROR_INT_A15 (68u) #define EDMA3_TC0_ERROR_INT_DSP (40u) #define EDMA3_TC0_ERROR_INT_IPU (36u) #define EDMA3_TC1_ERROR_INT_A15 (69u) #define EDMA3_TC1_ERROR_INT_DSP (41u) #define EDMA3_TC1_ERROR_INT_IPU (37u) /** Based on the interrupt number to be mapped define the XBAR instance number */ #define TC0_ERROR_INT_A15_XBAR_INST_NO (31u) #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u) #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u) #define TC1_ERROR_INT_A15_XBAR_INST_NO (32u) #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u) #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u) #ifdef BUILD_TDA2XX_MPU #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO #elif defined BUILD_TDA2XX_DSP #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO #elif defined BUILD_TDA2XX_IPU #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU_XBAR_INST_NO #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO #else #define EDMA3_CC_XFER_COMPLETION_INT (0u) #define EDMA3_CC_ERROR_INT (0u) #define CC_ERROR_INT_XBAR_INST_NO (0u) #define EDMA3_TC0_ERROR_INT (0u) #define EDMA3_TC1_ERROR_INT (0u) #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO #endif #define EDMA3_TC2_ERROR_INT (0u) #define EDMA3_TC3_ERROR_INT (0u) #define EDMA3_TC4_ERROR_INT (0u) #define EDMA3_TC5_ERROR_INT (0u) #define EDMA3_TC6_ERROR_INT (0u) #define EDMA3_TC7_ERROR_INT (0u) #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19u) #define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20u) #define DSP1_EDMA3_CC_ERROR_INT (27u) #define DSP1_EDMA3_TC0_ERROR_INT (28u) #define DSP1_EDMA3_TC1_ERROR_INT (29u) /** XBAR interrupt source index numbers for EDMA interrupts */ #define XBAR_EDMA_TPCC_IRQ_REGION0 (361u) #define XBAR_EDMA_TPCC_IRQ_REGION1 (362u) #define XBAR_EDMA_TPCC_IRQ_REGION2 (363u) #define XBAR_EDMA_TPCC_IRQ_REGION3 (364u) #define XBAR_EDMA_TPCC_IRQ_REGION4 (365u) #define XBAR_EDMA_TPCC_IRQ_REGION5 (366u) #define XBAR_EDMA_TPCC_IRQ_REGION6 (367u) #define XBAR_EDMA_TPCC_IRQ_REGION7 (368u) #define XBAR_EDMA_TPCC_IRQ_ERR (359u) #define XBAR_EDMA_TC0_IRQ_ERR (370u) #define XBAR_EDMA_TC1_IRQ_ERR (371u) /** * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different * ECM events (SoC specific). These ECM events come * under ECM block XXX (handling those specific ECM events). Normally, block * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) * is mapped to a specific HWI_INT YYY in the tcf file. * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding * to transfer completion interrupt. * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding * to CC error interrupts. * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding * to TC error interrupts. */ /* EDMA 0 */ #define EDMA3_HWI_INT_XFER_COMP (7u) #define EDMA3_HWI_INT_CC_ERR (7u) #define EDMA3_HWI_INT_TC0_ERR (10u) #define EDMA3_HWI_INT_TC1_ERR (10u) #define EDMA3_HWI_INT_TC2_ERR (10u) #define EDMA3_HWI_INT_TC3_ERR (10u) /** * \brief Mapping of DMA channels 0-31 to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. * 1: Mapped * 0: Not mapped * * This mapping will be used to allocate DMA channels when user passes * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory * copy). The same mapping is used to allocate the TCC when user passes * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). * * For Vayu Since the xbar can be used to map event to any EDMA channel, * If the application is assigning events to other channel this variable * should be modified * * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ /* 31 0 */ #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3FC0C06Eu) /* TBD */ #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFu) /* TBD */ /** * \brief Mapping of DMA channels 32-63 to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. * 1: Mapped * 0: Not mapped * * This mapping will be used to allocate DMA channels when user passes * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory * copy). The same mapping is used to allocate the TCC when user passes * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). * * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0xF3FFFFFCu) /* TBD */ #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */ /* Variable which will be used internally for referring number of Event Queues*/ unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = { EDMA3_NUM_EVTQUE, }; /* Variable which will be used internally for referring number of TCs. */ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = { EDMA3_NUM_TC, }; /** * Variable which will be used internally for referring transfer completion * interrupt. */ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { { EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_DSP, EDMA3_CC_XFER_COMPLETION_INT_DSP, EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1, EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1, }, { 0u, 0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, DSP2_EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, }, }; /** These are the Xbar instance numbers corresponding to interrupt numbers */ unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { { COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO, COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO, COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO, }, }; /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */ unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { { XBAR_EDMA_TPCC_IRQ_REGION0, XBAR_EDMA_TPCC_IRQ_REGION1, XBAR_EDMA_TPCC_IRQ_REGION2, XBAR_EDMA_TPCC_IRQ_REGION3, XBAR_EDMA_TPCC_IRQ_REGION4, XBAR_EDMA_TPCC_IRQ_REGION5, XBAR_EDMA_TPCC_IRQ_REGION6, XBAR_EDMA_TPCC_IRQ_REGION7, } }; /** * Variable which will be used internally for referring channel controller's * error interrupt. */ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = { EDMA3_CC_ERROR_INT,DSP1_EDMA3_CC_ERROR_INT, }; unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = { CC_ERROR_INT_XBAR_INST_NO, }; unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = { XBAR_EDMA_TPCC_IRQ_ERR, }; /** * Variable which will be used internally for referring transfer controllers' * error interrupts. */ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = { { EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT, EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT, EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT, EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT, }, { EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT, EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT, EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT, DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT, } }; unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] = { { TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO, 0u, 0u, 0u, 0u, 0u, 0u, } }; unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] = { { XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR, 0u, 0u, 0u, 0u, 0u, 0u, } }; /** * Variables which will be used internally for referring the hardware interrupt * for various EDMA3 interrupts. */ unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = { EDMA3_HWI_INT_XFER_COMP, EDMA3_HWI_INT_XFER_COMP, }; unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = { EDMA3_HWI_INT_CC_ERR, EDMA3_HWI_INT_CC_ERR, }; unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = { { EDMA3_HWI_INT_TC0_ERR, EDMA3_HWI_INT_TC1_ERR, EDMA3_HWI_INT_TC2_ERR, EDMA3_HWI_INT_TC3_ERR }, { EDMA3_HWI_INT_TC0_ERR, EDMA3_HWI_INT_TC1_ERR, EDMA3_HWI_INT_TC2_ERR, EDMA3_HWI_INT_TC3_ERR } }; /** * \brief Base address as seen from the different cores may be different * And is defined based on the core */ #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP)) #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000)) #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000)) #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000)) #elif (defined BUILD_TDA2XX_IPU) #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000)) #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000)) #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000)) #else #define EDMA3_CC_BASE_ADDR ((void *)(0x0)) #define EDMA3_TC0_BASE_ADDR ((void *)(0x0)) #define EDMA3_TC1_BASE_ADDR ((void *)(0x0)) #endif #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000)) #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000)) #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000)) /* Driver Object Initialization Configuration */ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = { { /* EDMA3 INSTANCE# 0 */ /** Total number of DMA Channels supported by the EDMA3 Controller */ EDMA3_NUM_DMA_CHANNELS, /** Total number of QDMA Channels supported by the EDMA3 Controller */ EDMA3_NUM_QDMA_CHANNELS, /** Total number of TCCs supported by the EDMA3 Controller */ EDMA3_NUM_TCC, /** Total number of PaRAM Sets supported by the EDMA3 Controller */ EDMA3_NUM_PARAMSET, /** Total number of Event Queues in the EDMA3 Controller */ EDMA3_NUM_EVTQUE, /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/ EDMA3_NUM_TC, /** Number of Regions on this EDMA3 controller */ EDMA3_NUM_REGIONS, /** * \brief Channel mapping existence * A value of 0 (No channel mapping) implies that there is fixed association * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ 1u, /** Existence of memory protection feature */ 0u, /** Global Register Region of CC Registers */ EDMA3_CC_BASE_ADDR, /** Transfer Controller (TC) Registers */ { EDMA3_TC0_BASE_ADDR, EDMA3_TC1_BASE_ADDR, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL }, /** Interrupt no. for Transfer Completion */ EDMA3_CC_XFER_COMPLETION_INT, /** Interrupt no. for CC Error */ EDMA3_CC_ERROR_INT, /** Interrupt no. for TCs Error */ { EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT, EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT, EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT, EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT }, /** * \brief EDMA3 TC priority setting * * User can program the priority of the Event Queues * at a system-wide level. This means that the user can set the * priority of an IO initiated by either of the TCs (Transfer Controllers) * relative to IO initiated by the other bus masters on the * device (ARM, DSP, USB, etc) */ { 0u, 1u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Threshold level of number of events * that can be queued up in the Event queues. EDMA3CC error register * (CCERR) will indicate whether or not at any instant of time the * number of events queued up in any of the event queues exceeds * or equals the threshold/watermark value that is set * in the queue watermark threshold register (QWMTHRA). */ { 16u, 16u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Default Burst Size (DBS) of TCs. * An optimally-sized command is defined by the transfer controller * default burst size (DBS). Different TCs can have different * DBS values. It is defined in Bytes. */ { 16u, 16u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief Mapping from each DMA channel to a Parameter RAM set, * if it exists, otherwise of no use. */ { EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP }, /** * \brief Mapping from each DMA channel to a TCC. This specific * TCC code will be returned when the transfer is completed * on the mapped channel. */ { EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, }, /** * \brief Mapping of DMA channels to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. */ { EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA } }, { /* EDMA3 INSTANCE# 1 */ /** Total number of DMA Channels supported by the EDMA3 Controller */ EDMA3_NUM_DMA_CHANNELS, /** Total number of QDMA Channels supported by the EDMA3 Controller */ EDMA3_NUM_QDMA_CHANNELS, /** Total number of TCCs supported by the EDMA3 Controller */ EDMA3_NUM_TCC, /** Total number of PaRAM Sets supported by the EDMA3 Controller */ EDMA3_NUM_PARAMSET, /** Total number of Event Queues in the EDMA3 Controller */ EDMA3_NUM_EVTQUE, /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/ EDMA3_NUM_TC, /** Number of Regions on this EDMA3 controller */ EDMA3_NUM_REGIONS, /** * \brief Channel mapping existence * A value of 0 (No channel mapping) implies that there is fixed association * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ 1u, /** Existence of memory protection feature */ 0u, /** Global Register Region of CC Registers */ DSP1_EDMA3_CC_BASE_ADDR, /** Transfer Controller (TC) Registers */ { DSP1_EDMA3_TC0_BASE_ADDR, DSP1_EDMA3_TC1_BASE_ADDR, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL }, /** Interrupt no. for Transfer Completion */ DSP1_EDMA3_CC_XFER_COMPLETION_INT, /** Interrupt no. for CC Error */ DSP1_EDMA3_CC_ERROR_INT, /** Interrupt no. for TCs Error */ { DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT, EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT, EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT, EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT }, /** * \brief EDMA3 TC priority setting * * User can program the priority of the Event Queues * at a system-wide level. This means that the user can set the * priority of an IO initiated by either of the TCs (Transfer Controllers) * relative to IO initiated by the other bus masters on the * device (ARM, DSP, USB, etc) */ { 0u, 1u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Threshold level of number of events * that can be queued up in the Event queues. EDMA3CC error register * (CCERR) will indicate whether or not at any instant of time the * number of events queued up in any of the event queues exceeds * or equals the threshold/watermark value that is set * in the queue watermark threshold register (QWMTHRA). */ { 16u, 16u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Default Burst Size (DBS) of TCs. * An optimally-sized command is defined by the transfer controller * default burst size (DBS). Different TCs can have different * DBS values. It is defined in Bytes. */ { 16u, 16u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief Mapping from each DMA channel to a Parameter RAM set, * if it exists, otherwise of no use. */ { EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP }, /** * \brief Mapping from each DMA channel to a TCC. This specific * TCC code will be returned when the transfer is completed * on the mapped channel. */ { EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, }, /** * \brief Mapping of DMA channels to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. */ { EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA } }, }; /** * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict * * Only Resources owned by a perticular core are allocated by Driver * Reserved resources are not allocated if requested for any available resource */ /* Driver Instance Initialization Configuration */ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { /* EDMA3 INSTANCE# 0 */ { /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 1 (Associated to MPU core 1) */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 2 (Associated to any DSP1)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 3 (Associated to any DSP2)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, }, /* EDMA3 INSTANCE# 1 DSP1 EDMA*/ { /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 1 (Not Associated to any core supported) */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFu, 0xFFFFFFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA}, /* resvdQdmaChannels */ /* 31 0 */ {0x00u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00u, 0x00u}, }, /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, }, }; /* Driver Instance Cross bar event to channel map Initialization Configuration */ EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { /* EDMA3 INSTANCE# 0 */ { /* Event to channel map for region 0 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 1 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 2 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 3 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 4 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 5 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 6 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 7 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, } }; /* End of File */

4545e288ed63a16bc4f956788934cd4e33ea7e52

dd80a584130ef1a0333429ba76c1cee0eb40df73

/prebuilts/ndk/5/platforms/android-9/arch-arm/usr/include/asm/dma-mapping.h

53393e561d34081f1f95c0231c64a2d79d5dc308

permissive

karunmatharu/Android-4.4-Pay-by-Data

466f4e169ede13c5835424c78e8c30ce58f885c1

fcb778e92d4aad525ef7a995660580f948d40bc9

refs/heads/master

MIT

UTF-8

C

h

../../../../../../platforms/android-8/arch-arm/usr/include/asm/dma-mapping.h

6400bf335eb96acaa94545c6c44652f0813d1792

91a882547e393d4c4946a6c2c99186b5f72122dd

/Source/XPSP1/NT/net/rras/ipx/rtrmgr/test/testmib.c

4e7d446cb0a8d4d3c81289793a4dc598688f2d8b

no_license

IAmAnubhavSaini/cryptoAlgorithm-nt5src

94f9b46f101b983954ac6e453d0cf8d02aa76fc7

d9e1cdeec650b9d6d3ce63f9f0abe50dabfaf9e2

refs/heads/master

UTF-8

C

c

#include <nt.h> #include <ntrtl.h> #include <nturtl.h> #include <ntddser.h> #include <windows.h> #include <stdio.h> #include <stdlib.h> #include <memory.h> #include <malloc.h> #include <rasman.h> #include <dim.h> #include <routprot.h> #include <ipxrtdef.h> // [pmay] this will no longer be neccessary when the ipx router // is converted to use MprInfo api's. typedef RTR_INFO_BLOCK_HEADER IPX_INFO_BLOCK_HEADER, *PIPX_INFO_BLOCK_HEADER; VOID PrintInterface(PIPX_INTERFACE ifp); VOID PrintRipInterface(PRIP_INTERFACE ifp); typedef struct _RPNAM { ULONG prot; PUCHAR namep; } RPNAM, *PRPNAM; RPNAM ProtName[] = { { IPX_PROTOCOL_LOCAL, "LOCAL" }, { IPX_PROTOCOL_STATIC, "STATIC" }, { IPX_PROTOCOL_RIP, "RIP" }, { IPX_PROTOCOL_SAP, "SAP" } }; #define MAX_IPX_PROTOCOLS sizeof(ProtName)/sizeof(RPNAM) IPX_INTERFACE IpxIf; VOID GetIpxInterface(PDIM_ROUTER_INTERFACE dimifp) { ULONG ii; DWORD rc; IPX_MIB_GET_INPUT_DATA MibGetInputData; DWORD IfSize; IfSize = sizeof(IPX_INTERFACE); printf("Enter interface index:"); scanf("%d", &ii); MibGetInputData.TableId = IPX_INTERFACE_TABLE; MibGetInputData.MibIndex.InterfaceTableIndex.InterfaceIndex = ii; rc = (*(dimifp->MIBEntryGet))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &IfSize, &IpxIf); if(rc != NO_ERROR) { printf("MibEntryGet: failed rc = %d\n", rc); return; } PrintInterface(&IpxIf); } VOID GetRipInterface(PDIM_ROUTER_INTERFACE dimifp) { DWORD rc; ULONG IfSize; RIP_MIB_GET_INPUT_DATA RipMibGetInputData; RIP_INTERFACE RipIf; printf("Enter interface index:"); scanf("%d", &RipMibGetInputData.InterfaceIndex); RipMibGetInputData.TableId = RIP_INTERFACE_TABLE; rc = (*(dimifp->MIBEntryGet))( IPX_PROTOCOL_RIP, sizeof(RIP_MIB_GET_INPUT_DATA), &RipMibGetInputData, &IfSize, &RipIf); if(rc != NO_ERROR) { printf("MibEntryGet: failed rc = %d\n", rc); return; } PrintRipInterface(&RipIf); } VOID GetRipFilters(PDIM_ROUTER_INTERFACE dimifp) { DWORD rc; ULONG GlobalInfoSize, i; RIP_MIB_GET_INPUT_DATA RipMibGetInputData; PRIP_GLOBAL_INFO RipGlobalInfop; PRIP_ROUTE_FILTER_INFO rfip; char *action; RipMibGetInputData.TableId = RIP_GLOBAL_INFO_ENTRY; rc = (*(dimifp->MIBEntryGet))( IPX_PROTOCOL_RIP, sizeof(RIP_MIB_GET_INPUT_DATA), &RipMibGetInputData, &GlobalInfoSize, NULL); if(rc != ERROR_INSUFFICIENT_BUFFER) { printf("MibEntryGet: failed rc = %d\n", rc); return; } RipGlobalInfop = GlobalAlloc(GPTR, GlobalInfoSize); rc = (*(dimifp->MIBEntryGet))( IPX_PROTOCOL_RIP, sizeof(RIP_MIB_GET_INPUT_DATA), &RipMibGetInputData, &GlobalInfoSize, RipGlobalInfop); if(rc != NO_ERROR) { printf("MibEntryGet: failed rc = %d\n", rc); return; } if(RipGlobalInfop->RouteFiltersCount == 0) { printf("No Filters\n"); return; } if(RipGlobalInfop->RouteFilterAction == IPX_ROUTE_FILTER_ADVERTISE) { action = "ADVERTISE"; } else { action = "SUPPRESS"; } printf("There are %d RIP filters configured for %s\n", RipGlobalInfop->RouteFiltersCount, action); for(i=0, rfip=RipGlobalInfop->RouteFilter; i<RipGlobalInfop->RouteFiltersCount; i++, rfip++) { printf("Route filter # %d Network %.2x%.2x%.2x%.2x\n", i, rfip->Network[0], rfip->Network[1], rfip->Network[2], rfip->Network[3]); } GlobalFree(RipGlobalInfop); } VOID PrintInterface(PIPX_INTERFACE ifp) { char *iftype; char *admin; char *oper; switch(ifp->InterfaceType) { case IF_TYPE_WAN_WORKSTATION: iftype ="WAN WORKSTATION"; break; case IF_TYPE_WAN_ROUTER: iftype = "WAN ROUTER"; break; case IF_TYPE_LAN: iftype = "LAN"; break; case IF_TYPE_INTERNAL: iftype = "INTERNAL"; break; default: iftype = "UNKNOWN"; break; } switch(ifp->AdminState) { case ADMIN_STATE_ENABLED: admin = "ENABLED"; break; case ADMIN_STATE_DISABLED: admin = "DISABLED"; break; default: admin = "UNKNOWN"; break; } switch(ifp->IfStats.IfOperState) { case OPER_STATE_UP: oper = "UP"; break; case OPER_STATE_DOWN: oper = "DOWN"; break; case OPER_STATE_SLEEPING: oper = "SLEEPING"; break; default: oper = "UNKNOWN"; break; } printf("\n"); printf("Interface Index: %d\n", ifp->InterfaceIndex); printf("Name: %s\n", ifp->InterfaceName); printf("Type: %s\n", iftype); printf("Network Number: %.2x%.2x%.2x%.2x\n", ifp->NetNumber[0], ifp->NetNumber[1], ifp->NetNumber[2], ifp->NetNumber[3]); printf("Admin State: %s\n", admin); printf("Oper State: %s\n\n", oper); } #define REPORT_RIP_CONFIG_STATE(report, config) \ switch((config)) {\ case ADMIN_STATE_ENABLED:\ (report) = "ENABLED";\ break;\ case ADMIN_STATE_DISABLED:\ (report) = "DISABLED";\ break;\ default:\ (report) = "UNKNOWN";\ break;\ } VOID PrintRipInterface(PRIP_INTERFACE ifp) { char *admin; char *oper; char *filtering; char *supply; char *listen; char *update; REPORT_RIP_CONFIG_STATE(admin, ifp->RipIfInfo.AdminState); REPORT_RIP_CONFIG_STATE(supply, ifp->RipIfInfo.Supply); REPORT_RIP_CONFIG_STATE(listen, ifp->RipIfInfo.Listen); REPORT_RIP_CONFIG_STATE(filtering, ifp->RipIfInfo.EnableGlobalFiltering); switch(ifp->RipIfStats.RipIfOperState) { case OPER_STATE_UP: oper = "UP"; break; case OPER_STATE_DOWN: oper = "DOWN"; break; case OPER_STATE_SLEEPING: oper = "SLEEPING"; break; default: oper = "UNKNOWN"; break; } switch(ifp->RipIfInfo.UpdateMode) { case IPX_STANDARD_UPDATE: update = "STANDARD"; break; case IPX_NO_UPDATE: update = "NO UPDATE"; break; case IPX_AUTO_STATIC_UPDATE: update = "AUTO-STATIC"; break; default: break; } printf("\n"); printf("Interface Index: %d\n", ifp->InterfaceIndex); printf("Admin State: %s\n", admin); printf("Oper State: %s\n", oper); printf("Supply RIP advertisments: %s\n", supply); printf("Listen to RIP advertisments: %s\n", listen); printf("Enable Global RIP Filtering: %s\n", filtering); printf("Update Mode: %s\n", update); printf("RIP packets recv: %d\n", ifp->RipIfStats.RipIfInputPackets); printf("RIP packets sent: %d\n\n", ifp->RipIfStats.RipIfOutputPackets); } VOID EnumerateIpxInterfaces(PDIM_ROUTER_INTERFACE dimifp) { DWORD rc; IPX_MIB_GET_INPUT_DATA MibGetInputData; DWORD IfSize; IfSize = sizeof(IPX_INTERFACE); MibGetInputData.TableId = IPX_INTERFACE_TABLE; MibGetInputData.MibIndex.InterfaceTableIndex.InterfaceIndex = 0; rc = (*(dimifp->MIBEntryGetFirst))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &IfSize, &IpxIf); if(rc != NO_ERROR) { printf("MIBEntryGetFirst: failed rc = %d\n", rc); return; } PrintInterface(&IpxIf); for(;;) { MibGetInputData.MibIndex.InterfaceTableIndex.InterfaceIndex = IpxIf.InterfaceIndex; rc = (*(dimifp->MIBEntryGetNext))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &IfSize, &IpxIf); if(rc != NO_ERROR) { printf("EnumerateIpxInterfaces: MIBEntryGetNext failed rc= 0x%x\n", rc); return; } PrintInterface(&IpxIf); } } IPX_ROUTE Route; VOID PrintRoute(VOID); VOID EnumerateAllBestRoutes(PDIM_ROUTER_INTERFACE dimifp) { DWORD rc; IPX_MIB_GET_INPUT_DATA MibGetInputData; DWORD RtSize; RtSize = sizeof(IPX_ROUTE); MibGetInputData.TableId = IPX_DEST_TABLE; memset(MibGetInputData.MibIndex.RoutingTableIndex.Network, 0, 4); rc = (*(dimifp->MIBEntryGetFirst))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &RtSize, &Route); if(rc != NO_ERROR) { printf("MIBEntryGetFirst: failed rc = %d\n", rc); return; } PrintRoute(); for(;;) { memcpy(MibGetInputData.MibIndex.RoutingTableIndex.Network, Route.Network, 4); rc = (*(dimifp->MIBEntryGetNext))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &RtSize, &Route); if(rc != NO_ERROR) { printf("MIBEntryGetNext failed rc= 0x%x\n", rc); return; } PrintRoute(); } } VOID PrintRoute(VOID) { int i; PUCHAR pn = "BOGUS"; for(i=0; i<MAX_IPX_PROTOCOLS; i++) { if(ProtName[i].prot == Route.Protocol) { pn = ProtName[i].namep; break; } } printf("Route: if # 0x%x, prot %s net %.2x%.2x%.2x%.2x ticks %d hops %d nexthop %.2x%.2x%.2x%.2x%.2x%.2x\n", Route.InterfaceIndex, pn, Route.Network[0], Route.Network[1], Route.Network[2], Route.Network[3], Route.TickCount, Route.HopCount, Route.NextHopMacAddress[0], Route.NextHopMacAddress[1], Route.NextHopMacAddress[2], Route.NextHopMacAddress[3], Route.NextHopMacAddress[4], Route.NextHopMacAddress[5]); } VOID EnumerateStaticRoutes(PDIM_ROUTER_INTERFACE dimifp) { DWORD rc; IPX_MIB_GET_INPUT_DATA MibGetInputData; DWORD RtSize; RtSize = sizeof(IPX_ROUTE); MibGetInputData.TableId = IPX_STATIC_ROUTE_TABLE; MibGetInputData.MibIndex.StaticRoutesTableIndex.InterfaceIndex = 0; memset(MibGetInputData.MibIndex.StaticRoutesTableIndex.Network, 0, 4); rc = (*(dimifp->MIBEntryGetFirst))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &RtSize, &Route); if(rc != NO_ERROR) { printf("MIBEntryGetFirst: failed rc = %d\n", rc); return; } PrintRoute(); for(;;) { memcpy(MibGetInputData.MibIndex.StaticRoutesTableIndex.Network, Route.Network, 4); MibGetInputData.MibIndex.StaticRoutesTableIndex.InterfaceIndex = Route.InterfaceIndex; rc = (*(dimifp->MIBEntryGetNext))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &RtSize, &Route); if(rc != NO_ERROR) { printf("MIBEntryGetNext failed rc= 0x%x\n", rc); return; } PrintRoute(); } } IPX_SERVICE Service; VOID PrintService(VOID) { int i; PUCHAR pn = "BOGUS"; for(i=0; i<MAX_IPX_PROTOCOLS; i++) { if(ProtName[i].prot == Service.Protocol) { pn = ProtName[i].namep; break; } } printf("Service if # %d prot %s type %d name %s\n", Service.InterfaceIndex, pn, Service.Server.Type, Service.Server.Name); } VOID EnumerateAllServers(PDIM_ROUTER_INTERFACE dimifp) { DWORD rc; IPX_MIB_GET_INPUT_DATA MibGetInputData; DWORD SvSize; SvSize = sizeof(IPX_SERVICE); MibGetInputData.TableId = IPX_SERV_TABLE; MibGetInputData.MibIndex.ServicesTableIndex.ServiceType = 0; memset(MibGetInputData.MibIndex.ServicesTableIndex.ServiceName, 0, 48); rc = (*(dimifp->MIBEntryGetFirst))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &SvSize, &Service); if(rc != NO_ERROR) { printf("MIBEntryGetFirst: failed rc = %d\n", rc); return; } PrintService(); for(;;) { MibGetInputData.MibIndex.ServicesTableIndex.ServiceType = Service.Server.Type; memcpy(MibGetInputData.MibIndex.ServicesTableIndex.ServiceName, Service.Server.Name, 48); rc = (*(dimifp->MIBEntryGetNext))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &SvSize, &Service); if(rc != NO_ERROR) { printf("MIBEntryGetNext failed rc= 0x%x\n", rc); return; } PrintService(); } } VOID EnumerateAllServersOfType(PDIM_ROUTER_INTERFACE dimifp, USHORT Type) { DWORD rc; IPX_MIB_GET_INPUT_DATA MibGetInputData; DWORD SvSize; SvSize = sizeof(IPX_SERVICE); MibGetInputData.TableId = IPX_SERV_TABLE; MibGetInputData.MibIndex.ServicesTableIndex.ServiceType = Type; memset(MibGetInputData.MibIndex.ServicesTableIndex.ServiceName, ' ', 40); for(;;) { rc = (*(dimifp->MIBEntryGetNext))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &SvSize, &Service); if(rc != NO_ERROR) { printf("MIBEntryGetNext failed rc= 0x%x\n", rc); return; } if(Service.Server.Type != Type) { return; } PrintService(); memcpy(MibGetInputData.MibIndex.ServicesTableIndex.ServiceName, Service.Server.Name, 48); } } VOID EnumerateStaticServers(PDIM_ROUTER_INTERFACE dimifp) { DWORD rc; IPX_MIB_GET_INPUT_DATA MibGetInputData; DWORD SvSize; SvSize = sizeof(IPX_SERVICE); MibGetInputData.TableId = IPX_STATIC_SERV_TABLE; MibGetInputData.MibIndex.StaticServicesTableIndex.InterfaceIndex = 0; MibGetInputData.MibIndex.StaticServicesTableIndex.ServiceType = 0; memset(MibGetInputData.MibIndex.ServicesTableIndex.ServiceName, 0, 48); rc = (*(dimifp->MIBEntryGetFirst))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &SvSize, &Service); if(rc != NO_ERROR) { printf("MIBEntryGetFirst: failed rc = %d\n", rc); return; } PrintService(); for(;;) { MibGetInputData.MibIndex.StaticServicesTableIndex.InterfaceIndex = Service.InterfaceIndex; MibGetInputData.MibIndex.StaticServicesTableIndex.ServiceType = Service.Server.Type; memcpy(MibGetInputData.MibIndex.StaticServicesTableIndex.ServiceName, Service.Server.Name, 48); rc = (*(dimifp->MIBEntryGetNext))( IPX_PROTOCOL_BASE, sizeof(IPX_MIB_GET_INPUT_DATA), &MibGetInputData, &SvSize, &Service); if(rc != NO_ERROR) { printf("MIBEntryGetNext failed rc= 0x%x\n", rc); return; } PrintService(); } } VOID TestMib(PDIM_ROUTER_INTERFACE dimifp) { int i; int Type; for(;;) { printf(" MIB TEST OPTIONS MENU:\n"); printf("1. MIB TEST - Get IPX interface\n"); printf("2. MIB TEST - Enumerate IPX Interfaces\n"); printf("3. MIB TEST - Enumerate all best routes\n"); printf("4. MIB TEST - Enumerate static routes\n"); printf("5. MIB TEST - Enumerate all servers\n"); printf("6. MIB TEST - Enumerate all servers of the specified type\n"); printf("7. MIB TEST - Enumerate all static servers\n"); printf("8. MIB TEST - Get RIP Interface\n"); printf("9. MIB TEST - Get RIP Filters\n"); printf("99. MIB TEST - return to main menu\n"); printf("Enter your option:"); scanf("%d", &i); switch(i) { case 1: GetIpxInterface(dimifp); break; case 2: EnumerateIpxInterfaces(dimifp); break; case 3: EnumerateAllBestRoutes(dimifp); break; case 4: EnumerateStaticRoutes(dimifp); break; case 5: EnumerateAllServers(dimifp); break; case 6: printf("Enter server type:"); scanf("%d", &Type); EnumerateAllServersOfType(dimifp, (USHORT)Type); break; case 7: EnumerateStaticServers(dimifp); break; case 8: GetRipInterface(dimifp); break; case 9: GetRipFilters(dimifp); break; case 99: return; default: break; } } }

422eb73957425f561d27ce186db9a140dda405ca

24d856d98c85a319d53be2768ccc176a50873fa3

/eglibc-2.15/sysdeps/unix/sysv/linux/sparc/sparc32/kernel_stat.h

a0da019c5f3a667b40e96c0b63c8145909b558db

permissive

dozenow/shortcut

a4803b59c95e72a01d73bb30acaae45cf76b0367

b140082a44c58f05af3495259c1beaaa9a63560b

refs/heads/jumpstart-php

BSD-2-Clause

C

UTF-8

C

h

/* Definition of `struct stat' used in the kernel */ struct kernel_stat { unsigned short int st_dev; unsigned long int st_ino; unsigned short int st_mode; short int st_nlink; unsigned short int st_uid; unsigned short int st_gid; unsigned short int st_rdev; long int st_size; struct timespec st_atim; struct timespec st_mtim; struct timespec st_ctim; long int st_blksize; long int st_blocks; unsigned long int __unused4; unsigned long int __unused5; }; #define _HAVE___UNUSED4 #define _HAVE___UNUSED5 #define _HAVE_STAT___UNUSED4 #define _HAVE_STAT___UNUSED5 #define _HAVE_STAT___PAD1 #define _HAVE_STAT___PAD2 #define _HAVE_STAT64___UNUSED4 #define _HAVE_STAT64___UNUSED5 #define _HAVE_STAT64___PAD2 #define _HAVE_STAT_NSEC #define _HAVE_STAT64_NSEC

jflinn

f7caf241f81655b975b0d1581dc0370a7c7cceab

83a73ae20e36c3259b24da5a08750dc34e299d9d

/FreqCountBD_wrapper/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_2/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h

aae3aef0ce0469373eb05e02e6083bd265b5fbd9

permissive

renorega/workspace

96819bd51903eddb87978bc0934f7495321cb8b0

a655702e48c26d3278f8f42954adb1d133a64e9e

refs/heads/main

MIT

UTF-8

C

h

/******************************************************************************* * Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved. * SPDX-License-Identifier: MIT *******************************************************************************/ #ifndef __XPMC_XPPU_H__ #define __XPMC_XPPU_H__ #ifdef __cplusplus extern "C" { #endif /** * XpmcXppu Base Address */ #define XPMC_XPPU_BASEADDR 0xF1310000UL /** * Register: XpmcXppuCtrl */ #define XPMC_XPPU_CTRL ( ( XPMC_XPPU_BASEADDR ) + 0x00000000UL ) #define XPMC_XPPU_CTRL_RSTVAL 0x00000000UL #define XPMC_XPPU_CTRL_HIDE_EN_SHIFT 3UL #define XPMC_XPPU_CTRL_HIDE_EN_WIDTH 1UL #define XPMC_XPPU_CTRL_HIDE_EN_MASK 0x00000008UL #define XPMC_XPPU_CTRL_HIDE_EN_DEFVAL 0x0UL #define XPMC_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL #define XPMC_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL #define XPMC_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL #define XPMC_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL #define XPMC_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL #define XPMC_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL #define XPMC_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL #define XPMC_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL #define XPMC_XPPU_CTRL_EN_SHIFT 0UL #define XPMC_XPPU_CTRL_EN_WIDTH 1UL #define XPMC_XPPU_CTRL_EN_MASK 0x00000001UL #define XPMC_XPPU_CTRL_EN_DEFVAL 0x0UL /** * Register: XpmcXppuErrSts1 */ #define XPMC_XPPU_ERR_STS1 ( ( XPMC_XPPU_BASEADDR ) + 0x00000004UL ) #define XPMC_XPPU_ERR_STS1_RSTVAL 0x00000000UL #define XPMC_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL #define XPMC_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL #define XPMC_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL #define XPMC_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL /** * Register: XpmcXppuErrSts2 */ #define XPMC_XPPU_ERR_STS2 ( ( XPMC_XPPU_BASEADDR ) + 0x00000008UL ) #define XPMC_XPPU_ERR_STS2_RSTVAL 0x00000000UL #define XPMC_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL #define XPMC_XPPU_ERR_STS2_AXI_ID_WIDTH 10UL #define XPMC_XPPU_ERR_STS2_AXI_ID_MASK 0x000003ffUL #define XPMC_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL /** * Register: XpmcXppuItr */ #define XPMC_XPPU_ITR ( ( XPMC_XPPU_BASEADDR ) + 0x0000000CUL ) #define XPMC_XPPU_ITR_RSTVAL 0x00000000UL #define XPMC_XPPU_ITR_APER_PARITY_SHIFT 7UL #define XPMC_XPPU_ITR_APER_PARITY_WIDTH 1UL #define XPMC_XPPU_ITR_APER_PARITY_MASK 0x00000080UL #define XPMC_XPPU_ITR_APER_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_ITR_APER_TZ_SHIFT 6UL #define XPMC_XPPU_ITR_APER_TZ_WIDTH 1UL #define XPMC_XPPU_ITR_APER_TZ_MASK 0x00000040UL #define XPMC_XPPU_ITR_APER_TZ_DEFVAL 0x0UL #define XPMC_XPPU_ITR_APER_PERM_SHIFT 5UL #define XPMC_XPPU_ITR_APER_PERM_WIDTH 1UL #define XPMC_XPPU_ITR_APER_PERM_MASK 0x00000020UL #define XPMC_XPPU_ITR_APER_PERM_DEFVAL 0x0UL #define XPMC_XPPU_ITR_MID_PARITY_SHIFT 3UL #define XPMC_XPPU_ITR_MID_PARITY_WIDTH 1UL #define XPMC_XPPU_ITR_MID_PARITY_MASK 0x00000008UL #define XPMC_XPPU_ITR_MID_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_ITR_MID_RO_SHIFT 2UL #define XPMC_XPPU_ITR_MID_RO_WIDTH 1UL #define XPMC_XPPU_ITR_MID_RO_MASK 0x00000004UL #define XPMC_XPPU_ITR_MID_RO_DEFVAL 0x0UL #define XPMC_XPPU_ITR_MID_MISS_SHIFT 1UL #define XPMC_XPPU_ITR_MID_MISS_WIDTH 1UL #define XPMC_XPPU_ITR_MID_MISS_MASK 0x00000002UL #define XPMC_XPPU_ITR_MID_MISS_DEFVAL 0x0UL #define XPMC_XPPU_ITR_INV_APB_SHIFT 0UL #define XPMC_XPPU_ITR_INV_APB_WIDTH 1UL #define XPMC_XPPU_ITR_INV_APB_MASK 0x00000001UL #define XPMC_XPPU_ITR_INV_APB_DEFVAL 0x0UL /** * Register: XpmcXppuIsr */ #define XPMC_XPPU_ISR ( ( XPMC_XPPU_BASEADDR ) + 0x00000010UL ) #define XPMC_XPPU_ISR_RSTVAL 0x00000000UL #define XPMC_XPPU_ISR_APER_PARITY_SHIFT 7UL #define XPMC_XPPU_ISR_APER_PARITY_WIDTH 1UL #define XPMC_XPPU_ISR_APER_PARITY_MASK 0x00000080UL #define XPMC_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_ISR_APER_TZ_SHIFT 6UL #define XPMC_XPPU_ISR_APER_TZ_WIDTH 1UL #define XPMC_XPPU_ISR_APER_TZ_MASK 0x00000040UL #define XPMC_XPPU_ISR_APER_TZ_DEFVAL 0x0UL #define XPMC_XPPU_ISR_APER_PERM_SHIFT 5UL #define XPMC_XPPU_ISR_APER_PERM_WIDTH 1UL #define XPMC_XPPU_ISR_APER_PERM_MASK 0x00000020UL #define XPMC_XPPU_ISR_APER_PERM_DEFVAL 0x0UL #define XPMC_XPPU_ISR_MID_PARITY_SHIFT 3UL #define XPMC_XPPU_ISR_MID_PARITY_WIDTH 1UL #define XPMC_XPPU_ISR_MID_PARITY_MASK 0x00000008UL #define XPMC_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_ISR_MID_RO_SHIFT 2UL #define XPMC_XPPU_ISR_MID_RO_WIDTH 1UL #define XPMC_XPPU_ISR_MID_RO_MASK 0x00000004UL #define XPMC_XPPU_ISR_MID_RO_DEFVAL 0x0UL #define XPMC_XPPU_ISR_MID_MISS_SHIFT 1UL #define XPMC_XPPU_ISR_MID_MISS_WIDTH 1UL #define XPMC_XPPU_ISR_MID_MISS_MASK 0x00000002UL #define XPMC_XPPU_ISR_MID_MISS_DEFVAL 0x0UL #define XPMC_XPPU_ISR_INV_APB_SHIFT 0UL #define XPMC_XPPU_ISR_INV_APB_WIDTH 1UL #define XPMC_XPPU_ISR_INV_APB_MASK 0x00000001UL #define XPMC_XPPU_ISR_INV_APB_DEFVAL 0x0UL /** * Register: XpmcXppuImr */ #define XPMC_XPPU_IMR ( ( XPMC_XPPU_BASEADDR ) + 0x00000014UL ) #define XPMC_XPPU_IMR_RSTVAL 0x000000efUL #define XPMC_XPPU_IMR_APER_PARITY_SHIFT 7UL #define XPMC_XPPU_IMR_APER_PARITY_WIDTH 1UL #define XPMC_XPPU_IMR_APER_PARITY_MASK 0x00000080UL #define XPMC_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL #define XPMC_XPPU_IMR_APER_TZ_SHIFT 6UL #define XPMC_XPPU_IMR_APER_TZ_WIDTH 1UL #define XPMC_XPPU_IMR_APER_TZ_MASK 0x00000040UL #define XPMC_XPPU_IMR_APER_TZ_DEFVAL 0x1UL #define XPMC_XPPU_IMR_APER_PERM_SHIFT 5UL #define XPMC_XPPU_IMR_APER_PERM_WIDTH 1UL #define XPMC_XPPU_IMR_APER_PERM_MASK 0x00000020UL #define XPMC_XPPU_IMR_APER_PERM_DEFVAL 0x1UL #define XPMC_XPPU_IMR_MID_PARITY_SHIFT 3UL #define XPMC_XPPU_IMR_MID_PARITY_WIDTH 1UL #define XPMC_XPPU_IMR_MID_PARITY_MASK 0x00000008UL #define XPMC_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL #define XPMC_XPPU_IMR_MID_RO_SHIFT 2UL #define XPMC_XPPU_IMR_MID_RO_WIDTH 1UL #define XPMC_XPPU_IMR_MID_RO_MASK 0x00000004UL #define XPMC_XPPU_IMR_MID_RO_DEFVAL 0x1UL #define XPMC_XPPU_IMR_MID_MISS_SHIFT 1UL #define XPMC_XPPU_IMR_MID_MISS_WIDTH 1UL #define XPMC_XPPU_IMR_MID_MISS_MASK 0x00000002UL #define XPMC_XPPU_IMR_MID_MISS_DEFVAL 0x1UL #define XPMC_XPPU_IMR_INV_APB_SHIFT 0UL #define XPMC_XPPU_IMR_INV_APB_WIDTH 1UL #define XPMC_XPPU_IMR_INV_APB_MASK 0x00000001UL #define XPMC_XPPU_IMR_INV_APB_DEFVAL 0x1UL /** * Register: XpmcXppuIen */ #define XPMC_XPPU_IEN ( ( XPMC_XPPU_BASEADDR ) + 0x00000018UL ) #define XPMC_XPPU_IEN_RSTVAL 0x00000000UL #define XPMC_XPPU_IEN_APER_PARITY_SHIFT 7UL #define XPMC_XPPU_IEN_APER_PARITY_WIDTH 1UL #define XPMC_XPPU_IEN_APER_PARITY_MASK 0x00000080UL #define XPMC_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_IEN_APER_TZ_SHIFT 6UL #define XPMC_XPPU_IEN_APER_TZ_WIDTH 1UL #define XPMC_XPPU_IEN_APER_TZ_MASK 0x00000040UL #define XPMC_XPPU_IEN_APER_TZ_DEFVAL 0x0UL #define XPMC_XPPU_IEN_APER_PERM_SHIFT 5UL #define XPMC_XPPU_IEN_APER_PERM_WIDTH 1UL #define XPMC_XPPU_IEN_APER_PERM_MASK 0x00000020UL #define XPMC_XPPU_IEN_APER_PERM_DEFVAL 0x0UL #define XPMC_XPPU_IEN_MID_PARITY_SHIFT 3UL #define XPMC_XPPU_IEN_MID_PARITY_WIDTH 1UL #define XPMC_XPPU_IEN_MID_PARITY_MASK 0x00000008UL #define XPMC_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_IEN_MID_RO_SHIFT 2UL #define XPMC_XPPU_IEN_MID_RO_WIDTH 1UL #define XPMC_XPPU_IEN_MID_RO_MASK 0x00000004UL #define XPMC_XPPU_IEN_MID_RO_DEFVAL 0x0UL #define XPMC_XPPU_IEN_MID_MISS_SHIFT 1UL #define XPMC_XPPU_IEN_MID_MISS_WIDTH 1UL #define XPMC_XPPU_IEN_MID_MISS_MASK 0x00000002UL #define XPMC_XPPU_IEN_MID_MISS_DEFVAL 0x0UL #define XPMC_XPPU_IEN_INV_APB_SHIFT 0UL #define XPMC_XPPU_IEN_INV_APB_WIDTH 1UL #define XPMC_XPPU_IEN_INV_APB_MASK 0x00000001UL #define XPMC_XPPU_IEN_INV_APB_DEFVAL 0x0UL /** * Register: XpmcXppuIds */ #define XPMC_XPPU_IDS ( ( XPMC_XPPU_BASEADDR ) + 0x0000001CUL ) #define XPMC_XPPU_IDS_RSTVAL 0x00000000UL #define XPMC_XPPU_IDS_APER_PARITY_SHIFT 7UL #define XPMC_XPPU_IDS_APER_PARITY_WIDTH 1UL #define XPMC_XPPU_IDS_APER_PARITY_MASK 0x00000080UL #define XPMC_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_IDS_APER_TZ_SHIFT 6UL #define XPMC_XPPU_IDS_APER_TZ_WIDTH 1UL #define XPMC_XPPU_IDS_APER_TZ_MASK 0x00000040UL #define XPMC_XPPU_IDS_APER_TZ_DEFVAL 0x0UL #define XPMC_XPPU_IDS_APER_PERM_SHIFT 5UL #define XPMC_XPPU_IDS_APER_PERM_WIDTH 1UL #define XPMC_XPPU_IDS_APER_PERM_MASK 0x00000020UL #define XPMC_XPPU_IDS_APER_PERM_DEFVAL 0x0UL #define XPMC_XPPU_IDS_MID_PARITY_SHIFT 3UL #define XPMC_XPPU_IDS_MID_PARITY_WIDTH 1UL #define XPMC_XPPU_IDS_MID_PARITY_MASK 0x00000008UL #define XPMC_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_IDS_MID_RO_SHIFT 2UL #define XPMC_XPPU_IDS_MID_RO_WIDTH 1UL #define XPMC_XPPU_IDS_MID_RO_MASK 0x00000004UL #define XPMC_XPPU_IDS_MID_RO_DEFVAL 0x0UL #define XPMC_XPPU_IDS_MID_MISS_SHIFT 1UL #define XPMC_XPPU_IDS_MID_MISS_WIDTH 1UL #define XPMC_XPPU_IDS_MID_MISS_MASK 0x00000002UL #define XPMC_XPPU_IDS_MID_MISS_DEFVAL 0x0UL #define XPMC_XPPU_IDS_INV_APB_SHIFT 0UL #define XPMC_XPPU_IDS_INV_APB_WIDTH 1UL #define XPMC_XPPU_IDS_INV_APB_MASK 0x00000001UL #define XPMC_XPPU_IDS_INV_APB_DEFVAL 0x0UL /** * Register: XpmcXppuLock */ #define XPMC_XPPU_LOCK ( ( XPMC_XPPU_BASEADDR ) + 0x00000020UL ) #define XPMC_XPPU_LOCK_RSTVAL 0x00000000UL #define XPMC_XPPU_LOCK_REGWRDIS_SHIFT 0UL #define XPMC_XPPU_LOCK_REGWRDIS_WIDTH 1UL #define XPMC_XPPU_LOCK_REGWRDIS_MASK 0x00000001UL #define XPMC_XPPU_LOCK_REGWRDIS_DEFVAL 0x0UL /** * Register: XpmcXppuMMasterIds */ #define XPMC_XPPU_M_MASTER_IDS ( ( XPMC_XPPU_BASEADDR ) + 0x0000003CUL ) #define XPMC_XPPU_M_MASTER_IDS_RSTVAL 0x00000014UL #define XPMC_XPPU_M_MASTER_IDS_NO_SHIFT 0UL #define XPMC_XPPU_M_MASTER_IDS_NO_WIDTH 32UL #define XPMC_XPPU_M_MASTER_IDS_NO_MASK 0xffffffffUL #define XPMC_XPPU_M_MASTER_IDS_NO_DEFVAL 0x14UL /** * Register: XpmcXppuMAperture64kb */ #define XPMC_XPPU_M_APERTURE_64KB ( ( XPMC_XPPU_BASEADDR ) + 0x00000044UL ) #define XPMC_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL #define XPMC_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL #define XPMC_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL #define XPMC_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL #define XPMC_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL /** * Register: XpmcXppuMAperture1mb */ #define XPMC_XPPU_M_APERTURE_1MB ( ( XPMC_XPPU_BASEADDR ) + 0x00000048UL ) #define XPMC_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL #define XPMC_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL #define XPMC_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL #define XPMC_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL #define XPMC_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL /** * Register: XpmcXppuMAperture512mb */ #define XPMC_XPPU_M_APERTURE_512MB ( ( XPMC_XPPU_BASEADDR ) + 0x0000004CUL ) #define XPMC_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL #define XPMC_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL #define XPMC_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL #define XPMC_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL #define XPMC_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL /** * Register: XpmcXppuBase64kb */ #define XPMC_XPPU_BASE_64KB ( ( XPMC_XPPU_BASEADDR ) + 0x00000054UL ) #define XPMC_XPPU_BASE_64KB_RSTVAL 0xff000000UL #define XPMC_XPPU_BASE_64KB_ADDR_SHIFT 0UL #define XPMC_XPPU_BASE_64KB_ADDR_WIDTH 32UL #define XPMC_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL #define XPMC_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL /** * Register: XpmcXppuBase1mb */ #define XPMC_XPPU_BASE_1MB ( ( XPMC_XPPU_BASEADDR ) + 0x00000058UL ) #define XPMC_XPPU_BASE_1MB_RSTVAL 0xfe000000UL #define XPMC_XPPU_BASE_1MB_ADDR_SHIFT 0UL #define XPMC_XPPU_BASE_1MB_ADDR_WIDTH 32UL #define XPMC_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL #define XPMC_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL /** * Register: XpmcXppuBase512mb */ #define XPMC_XPPU_BASE_512MB ( ( XPMC_XPPU_BASEADDR ) + 0x0000005CUL ) #define XPMC_XPPU_BASE_512MB_RSTVAL 0xe0000000UL #define XPMC_XPPU_BASE_512MB_ADDR_SHIFT 0UL #define XPMC_XPPU_BASE_512MB_ADDR_WIDTH 32UL #define XPMC_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL #define XPMC_XPPU_BASE_512MB_ADDR_DEFVAL 0xe0000000UL /** * Register: XpmcXppuMasterId00 */ #define XPMC_XPPU_MASTER_ID00 ( ( XPMC_XPPU_BASEADDR ) + 0x00000100UL ) #define XPMC_XPPU_MASTER_ID00_RSTVAL 0x03ff0238UL #define XPMC_XPPU_MASTER_ID00_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID00_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID00_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID00_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID00_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID00_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID00_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID00_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID00_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID00_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID00_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID00_MIDM_DEFVAL 0x3ffUL #define XPMC_XPPU_MASTER_ID00_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID00_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID00_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID00_MID_DEFVAL 0x238UL /** * Register: XpmcXppuMasterId01 */ #define XPMC_XPPU_MASTER_ID01 ( ( XPMC_XPPU_BASEADDR ) + 0x00000104UL ) #define XPMC_XPPU_MASTER_ID01_RSTVAL 0x83ff0200UL #define XPMC_XPPU_MASTER_ID01_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID01_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID01_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID01_MIDP_DEFVAL 0x1UL #define XPMC_XPPU_MASTER_ID01_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID01_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID01_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID01_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID01_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID01_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID01_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID01_MIDM_DEFVAL 0x3ffUL #define XPMC_XPPU_MASTER_ID01_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID01_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID01_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID01_MID_DEFVAL 0x200UL /** * Register: XpmcXppuMasterId02 */ #define XPMC_XPPU_MASTER_ID02 ( ( XPMC_XPPU_BASEADDR ) + 0x00000108UL ) #define XPMC_XPPU_MASTER_ID02_RSTVAL 0x03ff0204UL #define XPMC_XPPU_MASTER_ID02_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID02_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID02_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID02_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID02_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID02_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID02_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID02_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID02_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID02_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID02_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID02_MIDM_DEFVAL 0x3ffUL #define XPMC_XPPU_MASTER_ID02_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID02_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID02_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID02_MID_DEFVAL 0x204UL /** * Register: XpmcXppuMasterId03 */ #define XPMC_XPPU_MASTER_ID03 ( ( XPMC_XPPU_BASEADDR ) + 0x0000010CUL ) #define XPMC_XPPU_MASTER_ID03_RSTVAL 0x83f00260UL #define XPMC_XPPU_MASTER_ID03_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID03_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID03_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID03_MIDP_DEFVAL 0x1UL #define XPMC_XPPU_MASTER_ID03_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID03_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID03_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID03_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID03_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID03_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID03_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID03_MIDM_DEFVAL 0x3f0UL #define XPMC_XPPU_MASTER_ID03_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID03_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID03_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID03_MID_DEFVAL 0x260UL /** * Register: XpmcXppuMasterId04 */ #define XPMC_XPPU_MASTER_ID04 ( ( XPMC_XPPU_BASEADDR ) + 0x00000110UL ) #define XPMC_XPPU_MASTER_ID04_RSTVAL 0x83ff0260UL #define XPMC_XPPU_MASTER_ID04_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID04_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID04_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID04_MIDP_DEFVAL 0x1UL #define XPMC_XPPU_MASTER_ID04_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID04_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID04_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID04_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID04_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID04_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID04_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID04_MIDM_DEFVAL 0x3ffUL #define XPMC_XPPU_MASTER_ID04_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID04_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID04_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID04_MID_DEFVAL 0x260UL /** * Register: XpmcXppuMasterId05 */ #define XPMC_XPPU_MASTER_ID05 ( ( XPMC_XPPU_BASEADDR ) + 0x00000114UL ) #define XPMC_XPPU_MASTER_ID05_RSTVAL 0x03ff0261UL #define XPMC_XPPU_MASTER_ID05_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID05_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID05_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID05_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID05_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID05_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID05_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID05_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID05_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID05_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID05_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID05_MIDM_DEFVAL 0x3ffUL #define XPMC_XPPU_MASTER_ID05_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID05_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID05_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID05_MID_DEFVAL 0x261UL /** * Register: XpmcXppuMasterId06 */ #define XPMC_XPPU_MASTER_ID06 ( ( XPMC_XPPU_BASEADDR ) + 0x00000118UL ) #define XPMC_XPPU_MASTER_ID06_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID06_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID06_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID06_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID06_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID06_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID06_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID06_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID06_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID06_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID06_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID06_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID06_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID06_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID06_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID06_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID06_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId07 */ #define XPMC_XPPU_MASTER_ID07 ( ( XPMC_XPPU_BASEADDR ) + 0x0000011CUL ) #define XPMC_XPPU_MASTER_ID07_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID07_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID07_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID07_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID07_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID07_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID07_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID07_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID07_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID07_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID07_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID07_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID07_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID07_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID07_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID07_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID07_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId08 */ #define XPMC_XPPU_MASTER_ID08 ( ( XPMC_XPPU_BASEADDR ) + 0x00000120UL ) #define XPMC_XPPU_MASTER_ID08_RSTVAL 0x83ff0247UL #define XPMC_XPPU_MASTER_ID08_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID08_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID08_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID08_MIDP_DEFVAL 0x1UL #define XPMC_XPPU_MASTER_ID08_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID08_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID08_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID08_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID08_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID08_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID08_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID08_MIDM_DEFVAL 0x3ffUL #define XPMC_XPPU_MASTER_ID08_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID08_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID08_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID08_MID_DEFVAL 0x247UL /** * Register: XpmcXppuMasterId09 */ #define XPMC_XPPU_MASTER_ID09 ( ( XPMC_XPPU_BASEADDR ) + 0x00000124UL ) #define XPMC_XPPU_MASTER_ID09_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID09_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID09_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID09_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID09_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID09_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID09_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID09_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID09_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID09_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID09_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID09_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID09_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID09_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID09_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID09_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID09_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId10 */ #define XPMC_XPPU_MASTER_ID10 ( ( XPMC_XPPU_BASEADDR ) + 0x00000128UL ) #define XPMC_XPPU_MASTER_ID10_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID10_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID10_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID10_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID10_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID10_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID10_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID10_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID10_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID10_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID10_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID10_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID10_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID10_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID10_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID10_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID10_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId11 */ #define XPMC_XPPU_MASTER_ID11 ( ( XPMC_XPPU_BASEADDR ) + 0x0000012CUL ) #define XPMC_XPPU_MASTER_ID11_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID11_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID11_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID11_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID11_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID11_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID11_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID11_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID11_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID11_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID11_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID11_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID11_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID11_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID11_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID11_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID11_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId12 */ #define XPMC_XPPU_MASTER_ID12 ( ( XPMC_XPPU_BASEADDR ) + 0x00000130UL ) #define XPMC_XPPU_MASTER_ID12_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID12_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID12_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID12_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID12_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID12_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID12_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID12_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID12_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID12_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID12_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID12_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID12_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID12_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID12_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID12_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID12_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId13 */ #define XPMC_XPPU_MASTER_ID13 ( ( XPMC_XPPU_BASEADDR ) + 0x00000134UL ) #define XPMC_XPPU_MASTER_ID13_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID13_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID13_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID13_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID13_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID13_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID13_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID13_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID13_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID13_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID13_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID13_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID13_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID13_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID13_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID13_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID13_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId14 */ #define XPMC_XPPU_MASTER_ID14 ( ( XPMC_XPPU_BASEADDR ) + 0x00000138UL ) #define XPMC_XPPU_MASTER_ID14_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID14_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID14_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID14_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID14_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID14_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID14_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID14_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID14_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID14_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID14_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID14_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID14_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID14_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID14_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID14_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID14_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId15 */ #define XPMC_XPPU_MASTER_ID15 ( ( XPMC_XPPU_BASEADDR ) + 0x0000013CUL ) #define XPMC_XPPU_MASTER_ID15_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID15_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID15_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID15_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID15_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID15_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID15_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID15_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID15_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID15_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID15_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID15_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID15_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID15_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID15_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID15_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID15_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId16 */ #define XPMC_XPPU_MASTER_ID16 ( ( XPMC_XPPU_BASEADDR ) + 0x00000140UL ) #define XPMC_XPPU_MASTER_ID16_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID16_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID16_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID16_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID16_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID16_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID16_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID16_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID16_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID16_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID16_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID16_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID16_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID16_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID16_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID16_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID16_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId17 */ #define XPMC_XPPU_MASTER_ID17 ( ( XPMC_XPPU_BASEADDR ) + 0x00000144UL ) #define XPMC_XPPU_MASTER_ID17_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID17_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID17_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID17_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID17_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID17_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID17_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID17_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID17_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID17_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID17_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID17_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID17_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID17_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID17_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID17_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID17_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId18 */ #define XPMC_XPPU_MASTER_ID18 ( ( XPMC_XPPU_BASEADDR ) + 0x00000148UL ) #define XPMC_XPPU_MASTER_ID18_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID18_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID18_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID18_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID18_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID18_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID18_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID18_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID18_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID18_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID18_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID18_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID18_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID18_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID18_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID18_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID18_MID_DEFVAL 0x0UL /** * Register: XpmcXppuMasterId19 */ #define XPMC_XPPU_MASTER_ID19 ( ( XPMC_XPPU_BASEADDR ) + 0x0000014CUL ) #define XPMC_XPPU_MASTER_ID19_RSTVAL 0x00000000UL #define XPMC_XPPU_MASTER_ID19_MIDP_SHIFT 31UL #define XPMC_XPPU_MASTER_ID19_MIDP_WIDTH 1UL #define XPMC_XPPU_MASTER_ID19_MIDP_MASK 0x80000000UL #define XPMC_XPPU_MASTER_ID19_MIDP_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID19_MIDR_SHIFT 30UL #define XPMC_XPPU_MASTER_ID19_MIDR_WIDTH 1UL #define XPMC_XPPU_MASTER_ID19_MIDR_MASK 0x40000000UL #define XPMC_XPPU_MASTER_ID19_MIDR_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID19_MIDM_SHIFT 16UL #define XPMC_XPPU_MASTER_ID19_MIDM_WIDTH 10UL #define XPMC_XPPU_MASTER_ID19_MIDM_MASK 0x03ff0000UL #define XPMC_XPPU_MASTER_ID19_MIDM_DEFVAL 0x0UL #define XPMC_XPPU_MASTER_ID19_MID_SHIFT 0UL #define XPMC_XPPU_MASTER_ID19_MID_WIDTH 10UL #define XPMC_XPPU_MASTER_ID19_MID_MASK 0x000003ffUL #define XPMC_XPPU_MASTER_ID19_MID_DEFVAL 0x0UL /** * Register: XpmcXppuEnPermCheckReg00 */ #define XPMC_XPPU_EN_PERM_CHECK_REG00 ( ( XPMC_XPPU_BASEADDR ) + 0x00000150UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG00_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG00_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG00_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG00_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG00_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg01 */ #define XPMC_XPPU_EN_PERM_CHECK_REG01 ( ( XPMC_XPPU_BASEADDR ) + 0x00000154UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG01_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG01_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG01_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG01_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG01_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg02 */ #define XPMC_XPPU_EN_PERM_CHECK_REG02 ( ( XPMC_XPPU_BASEADDR ) + 0x00000158UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG02_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG02_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG02_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG02_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG02_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg03 */ #define XPMC_XPPU_EN_PERM_CHECK_REG03 ( ( XPMC_XPPU_BASEADDR ) + 0x0000015CUL ) #define XPMC_XPPU_EN_PERM_CHECK_REG03_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG03_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG03_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG03_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG03_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg04 */ #define XPMC_XPPU_EN_PERM_CHECK_REG04 ( ( XPMC_XPPU_BASEADDR ) + 0x00000160UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG04_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG04_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG04_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG04_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG04_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg05 */ #define XPMC_XPPU_EN_PERM_CHECK_REG05 ( ( XPMC_XPPU_BASEADDR ) + 0x00000164UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG05_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG05_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG05_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG05_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG05_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg06 */ #define XPMC_XPPU_EN_PERM_CHECK_REG06 ( ( XPMC_XPPU_BASEADDR ) + 0x00000168UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG06_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG06_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG06_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG06_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG06_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg07 */ #define XPMC_XPPU_EN_PERM_CHECK_REG07 ( ( XPMC_XPPU_BASEADDR ) + 0x0000016CUL ) #define XPMC_XPPU_EN_PERM_CHECK_REG07_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG07_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG07_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG07_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG07_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg08 */ #define XPMC_XPPU_EN_PERM_CHECK_REG08 ( ( XPMC_XPPU_BASEADDR ) + 0x00000170UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG08_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG08_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG08_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG08_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG08_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg09 */ #define XPMC_XPPU_EN_PERM_CHECK_REG09 ( ( XPMC_XPPU_BASEADDR ) + 0x00000174UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG09_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG09_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG09_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG09_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG09_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg10 */ #define XPMC_XPPU_EN_PERM_CHECK_REG10 ( ( XPMC_XPPU_BASEADDR ) + 0x00000178UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG10_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG10_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG10_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG10_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG10_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg11 */ #define XPMC_XPPU_EN_PERM_CHECK_REG11 ( ( XPMC_XPPU_BASEADDR ) + 0x0000017CUL ) #define XPMC_XPPU_EN_PERM_CHECK_REG11_RSTVAL 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG11_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG11_WIDTH 32UL #define XPMC_XPPU_EN_PERM_CHECK_REG11_MASK 0xffffffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG11_DEFVAL 0xffffffffUL /** * Register: XpmcXppuEnPermCheckReg12 */ #define XPMC_XPPU_EN_PERM_CHECK_REG12 ( ( XPMC_XPPU_BASEADDR ) + 0x00000180UL ) #define XPMC_XPPU_EN_PERM_CHECK_REG12_RSTVAL 0x000fffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG12_SHIFT 0UL #define XPMC_XPPU_EN_PERM_CHECK_REG12_WIDTH 20UL #define XPMC_XPPU_EN_PERM_CHECK_REG12_MASK 0x000fffffUL #define XPMC_XPPU_EN_PERM_CHECK_REG12_DEFVAL 0xfffffUL /** * Register: XpmcXppuAperperm000 */ #define XPMC_XPPU_APERPERM_000 ( ( XPMC_XPPU_BASEADDR ) + 0x00001000UL ) #define XPMC_XPPU_APERPERM_000_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_000_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_000_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_000_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_000_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_000_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_000_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_000_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_000_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_000_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_000_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_000_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_000_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm001 */ #define XPMC_XPPU_APERPERM_001 ( ( XPMC_XPPU_BASEADDR ) + 0x00001004UL ) #define XPMC_XPPU_APERPERM_001_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_001_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_001_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_001_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_001_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_001_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_001_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_001_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_001_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_001_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_001_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_001_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_001_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm002 */ #define XPMC_XPPU_APERPERM_002 ( ( XPMC_XPPU_BASEADDR ) + 0x00001008UL ) #define XPMC_XPPU_APERPERM_002_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_002_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_002_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_002_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_002_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_002_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_002_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_002_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_002_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_002_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_002_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_002_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_002_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm003 */ #define XPMC_XPPU_APERPERM_003 ( ( XPMC_XPPU_BASEADDR ) + 0x0000100CUL ) #define XPMC_XPPU_APERPERM_003_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_003_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_003_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_003_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_003_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_003_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_003_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_003_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_003_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_003_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_003_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_003_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_003_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm004 */ #define XPMC_XPPU_APERPERM_004 ( ( XPMC_XPPU_BASEADDR ) + 0x00001010UL ) #define XPMC_XPPU_APERPERM_004_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_004_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_004_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_004_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_004_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_004_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_004_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_004_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_004_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_004_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_004_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_004_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_004_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm005 */ #define XPMC_XPPU_APERPERM_005 ( ( XPMC_XPPU_BASEADDR ) + 0x00001014UL ) #define XPMC_XPPU_APERPERM_005_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_005_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_005_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_005_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_005_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_005_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_005_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_005_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_005_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_005_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_005_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_005_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_005_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm006 */ #define XPMC_XPPU_APERPERM_006 ( ( XPMC_XPPU_BASEADDR ) + 0x00001018UL ) #define XPMC_XPPU_APERPERM_006_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_006_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_006_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_006_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_006_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_006_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_006_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_006_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_006_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_006_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_006_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_006_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_006_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm007 */ #define XPMC_XPPU_APERPERM_007 ( ( XPMC_XPPU_BASEADDR ) + 0x0000101CUL ) #define XPMC_XPPU_APERPERM_007_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_007_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_007_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_007_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_007_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_007_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_007_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_007_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_007_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_007_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_007_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_007_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_007_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm008 */ #define XPMC_XPPU_APERPERM_008 ( ( XPMC_XPPU_BASEADDR ) + 0x00001020UL ) #define XPMC_XPPU_APERPERM_008_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_008_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_008_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_008_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_008_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_008_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_008_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_008_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_008_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_008_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_008_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_008_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_008_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm009 */ #define XPMC_XPPU_APERPERM_009 ( ( XPMC_XPPU_BASEADDR ) + 0x00001024UL ) #define XPMC_XPPU_APERPERM_009_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_009_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_009_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_009_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_009_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_009_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_009_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_009_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_009_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_009_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_009_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_009_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_009_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm010 */ #define XPMC_XPPU_APERPERM_010 ( ( XPMC_XPPU_BASEADDR ) + 0x00001028UL ) #define XPMC_XPPU_APERPERM_010_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_010_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_010_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_010_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_010_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_010_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_010_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_010_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_010_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_010_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_010_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_010_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_010_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm011 */ #define XPMC_XPPU_APERPERM_011 ( ( XPMC_XPPU_BASEADDR ) + 0x0000102CUL ) #define XPMC_XPPU_APERPERM_011_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_011_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_011_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_011_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_011_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_011_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_011_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_011_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_011_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_011_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_011_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_011_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_011_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm012 */ #define XPMC_XPPU_APERPERM_012 ( ( XPMC_XPPU_BASEADDR ) + 0x00001030UL ) #define XPMC_XPPU_APERPERM_012_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_012_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_012_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_012_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_012_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_012_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_012_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_012_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_012_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_012_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_012_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_012_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_012_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm013 */ #define XPMC_XPPU_APERPERM_013 ( ( XPMC_XPPU_BASEADDR ) + 0x00001034UL ) #define XPMC_XPPU_APERPERM_013_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_013_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_013_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_013_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_013_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_013_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_013_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_013_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_013_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_013_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_013_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_013_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_013_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm014 */ #define XPMC_XPPU_APERPERM_014 ( ( XPMC_XPPU_BASEADDR ) + 0x00001038UL ) #define XPMC_XPPU_APERPERM_014_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_014_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_014_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_014_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_014_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_014_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_014_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_014_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_014_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_014_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_014_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_014_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_014_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm015 */ #define XPMC_XPPU_APERPERM_015 ( ( XPMC_XPPU_BASEADDR ) + 0x0000103CUL ) #define XPMC_XPPU_APERPERM_015_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_015_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_015_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_015_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_015_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_015_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_015_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_015_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_015_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_015_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_015_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_015_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_015_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm016 */ #define XPMC_XPPU_APERPERM_016 ( ( XPMC_XPPU_BASEADDR ) + 0x00001040UL ) #define XPMC_XPPU_APERPERM_016_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_016_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_016_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_016_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_016_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_016_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_016_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_016_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_016_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_016_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_016_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_016_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_016_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm017 */ #define XPMC_XPPU_APERPERM_017 ( ( XPMC_XPPU_BASEADDR ) + 0x00001044UL ) #define XPMC_XPPU_APERPERM_017_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_017_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_017_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_017_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_017_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_017_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_017_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_017_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_017_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_017_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_017_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_017_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_017_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm018 */ #define XPMC_XPPU_APERPERM_018 ( ( XPMC_XPPU_BASEADDR ) + 0x00001048UL ) #define XPMC_XPPU_APERPERM_018_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_018_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_018_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_018_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_018_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_018_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_018_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_018_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_018_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_018_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_018_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_018_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_018_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm019 */ #define XPMC_XPPU_APERPERM_019 ( ( XPMC_XPPU_BASEADDR ) + 0x0000104CUL ) #define XPMC_XPPU_APERPERM_019_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_019_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_019_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_019_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_019_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_019_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_019_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_019_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_019_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_019_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_019_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_019_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_019_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm020 */ #define XPMC_XPPU_APERPERM_020 ( ( XPMC_XPPU_BASEADDR ) + 0x00001050UL ) #define XPMC_XPPU_APERPERM_020_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_020_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_020_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_020_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_020_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_020_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_020_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_020_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_020_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_020_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_020_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_020_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_020_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm021 */ #define XPMC_XPPU_APERPERM_021 ( ( XPMC_XPPU_BASEADDR ) + 0x00001054UL ) #define XPMC_XPPU_APERPERM_021_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_021_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_021_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_021_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_021_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_021_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_021_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_021_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_021_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_021_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_021_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_021_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_021_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm022 */ #define XPMC_XPPU_APERPERM_022 ( ( XPMC_XPPU_BASEADDR ) + 0x00001058UL ) #define XPMC_XPPU_APERPERM_022_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_022_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_022_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_022_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_022_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_022_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_022_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_022_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_022_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_022_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_022_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_022_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_022_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm023 */ #define XPMC_XPPU_APERPERM_023 ( ( XPMC_XPPU_BASEADDR ) + 0x0000105CUL ) #define XPMC_XPPU_APERPERM_023_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_023_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_023_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_023_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_023_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_023_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_023_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_023_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_023_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_023_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_023_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_023_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_023_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm024 */ #define XPMC_XPPU_APERPERM_024 ( ( XPMC_XPPU_BASEADDR ) + 0x00001060UL ) #define XPMC_XPPU_APERPERM_024_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_024_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_024_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_024_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_024_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_024_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_024_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_024_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_024_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_024_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_024_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_024_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_024_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm025 */ #define XPMC_XPPU_APERPERM_025 ( ( XPMC_XPPU_BASEADDR ) + 0x00001064UL ) #define XPMC_XPPU_APERPERM_025_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_025_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_025_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_025_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_025_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_025_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_025_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_025_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_025_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_025_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_025_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_025_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_025_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm026 */ #define XPMC_XPPU_APERPERM_026 ( ( XPMC_XPPU_BASEADDR ) + 0x00001068UL ) #define XPMC_XPPU_APERPERM_026_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_026_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_026_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_026_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_026_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_026_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_026_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_026_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_026_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_026_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_026_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_026_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_026_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm027 */ #define XPMC_XPPU_APERPERM_027 ( ( XPMC_XPPU_BASEADDR ) + 0x0000106CUL ) #define XPMC_XPPU_APERPERM_027_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_027_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_027_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_027_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_027_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_027_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_027_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_027_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_027_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_027_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_027_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_027_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_027_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm028 */ #define XPMC_XPPU_APERPERM_028 ( ( XPMC_XPPU_BASEADDR ) + 0x00001070UL ) #define XPMC_XPPU_APERPERM_028_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_028_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_028_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_028_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_028_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_028_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_028_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_028_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_028_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_028_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_028_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_028_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_028_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm029 */ #define XPMC_XPPU_APERPERM_029 ( ( XPMC_XPPU_BASEADDR ) + 0x00001074UL ) #define XPMC_XPPU_APERPERM_029_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_029_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_029_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_029_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_029_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_029_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_029_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_029_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_029_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_029_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_029_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_029_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_029_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm030 */ #define XPMC_XPPU_APERPERM_030 ( ( XPMC_XPPU_BASEADDR ) + 0x00001078UL ) #define XPMC_XPPU_APERPERM_030_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_030_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_030_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_030_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_030_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_030_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_030_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_030_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_030_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_030_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_030_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_030_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_030_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm031 */ #define XPMC_XPPU_APERPERM_031 ( ( XPMC_XPPU_BASEADDR ) + 0x0000107CUL ) #define XPMC_XPPU_APERPERM_031_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_031_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_031_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_031_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_031_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_031_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_031_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_031_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_031_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_031_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_031_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_031_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_031_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm032 */ #define XPMC_XPPU_APERPERM_032 ( ( XPMC_XPPU_BASEADDR ) + 0x00001080UL ) #define XPMC_XPPU_APERPERM_032_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_032_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_032_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_032_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_032_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_032_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_032_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_032_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_032_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_032_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_032_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_032_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_032_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm033 */ #define XPMC_XPPU_APERPERM_033 ( ( XPMC_XPPU_BASEADDR ) + 0x00001084UL ) #define XPMC_XPPU_APERPERM_033_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_033_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_033_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_033_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_033_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_033_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_033_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_033_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_033_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_033_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_033_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_033_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_033_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm034 */ #define XPMC_XPPU_APERPERM_034 ( ( XPMC_XPPU_BASEADDR ) + 0x00001088UL ) #define XPMC_XPPU_APERPERM_034_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_034_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_034_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_034_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_034_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_034_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_034_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_034_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_034_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_034_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_034_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_034_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_034_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm035 */ #define XPMC_XPPU_APERPERM_035 ( ( XPMC_XPPU_BASEADDR ) + 0x0000108CUL ) #define XPMC_XPPU_APERPERM_035_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_035_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_035_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_035_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_035_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_035_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_035_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_035_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_035_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_035_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_035_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_035_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_035_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm036 */ #define XPMC_XPPU_APERPERM_036 ( ( XPMC_XPPU_BASEADDR ) + 0x00001090UL ) #define XPMC_XPPU_APERPERM_036_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_036_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_036_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_036_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_036_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_036_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_036_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_036_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_036_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_036_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_036_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_036_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_036_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm037 */ #define XPMC_XPPU_APERPERM_037 ( ( XPMC_XPPU_BASEADDR ) + 0x00001094UL ) #define XPMC_XPPU_APERPERM_037_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_037_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_037_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_037_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_037_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_037_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_037_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_037_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_037_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_037_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_037_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_037_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_037_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm038 */ #define XPMC_XPPU_APERPERM_038 ( ( XPMC_XPPU_BASEADDR ) + 0x00001098UL ) #define XPMC_XPPU_APERPERM_038_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_038_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_038_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_038_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_038_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_038_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_038_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_038_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_038_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_038_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_038_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_038_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_038_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm039 */ #define XPMC_XPPU_APERPERM_039 ( ( XPMC_XPPU_BASEADDR ) + 0x0000109CUL ) #define XPMC_XPPU_APERPERM_039_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_039_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_039_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_039_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_039_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_039_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_039_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_039_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_039_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_039_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_039_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_039_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_039_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm040 */ #define XPMC_XPPU_APERPERM_040 ( ( XPMC_XPPU_BASEADDR ) + 0x000010A0UL ) #define XPMC_XPPU_APERPERM_040_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_040_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_040_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_040_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_040_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_040_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_040_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_040_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_040_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_040_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_040_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_040_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_040_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm041 */ #define XPMC_XPPU_APERPERM_041 ( ( XPMC_XPPU_BASEADDR ) + 0x000010A4UL ) #define XPMC_XPPU_APERPERM_041_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_041_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_041_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_041_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_041_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_041_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_041_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_041_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_041_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_041_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_041_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_041_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_041_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm042 */ #define XPMC_XPPU_APERPERM_042 ( ( XPMC_XPPU_BASEADDR ) + 0x000010A8UL ) #define XPMC_XPPU_APERPERM_042_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_042_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_042_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_042_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_042_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_042_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_042_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_042_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_042_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_042_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_042_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_042_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_042_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm043 */ #define XPMC_XPPU_APERPERM_043 ( ( XPMC_XPPU_BASEADDR ) + 0x000010ACUL ) #define XPMC_XPPU_APERPERM_043_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_043_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_043_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_043_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_043_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_043_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_043_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_043_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_043_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_043_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_043_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_043_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_043_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm044 */ #define XPMC_XPPU_APERPERM_044 ( ( XPMC_XPPU_BASEADDR ) + 0x000010B0UL ) #define XPMC_XPPU_APERPERM_044_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_044_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_044_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_044_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_044_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_044_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_044_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_044_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_044_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_044_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_044_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_044_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_044_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm045 */ #define XPMC_XPPU_APERPERM_045 ( ( XPMC_XPPU_BASEADDR ) + 0x000010B4UL ) #define XPMC_XPPU_APERPERM_045_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_045_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_045_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_045_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_045_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_045_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_045_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_045_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_045_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_045_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_045_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_045_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_045_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm046 */ #define XPMC_XPPU_APERPERM_046 ( ( XPMC_XPPU_BASEADDR ) + 0x000010B8UL ) #define XPMC_XPPU_APERPERM_046_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_046_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_046_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_046_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_046_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_046_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_046_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_046_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_046_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_046_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_046_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_046_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_046_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm047 */ #define XPMC_XPPU_APERPERM_047 ( ( XPMC_XPPU_BASEADDR ) + 0x000010BCUL ) #define XPMC_XPPU_APERPERM_047_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_047_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_047_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_047_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_047_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_047_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_047_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_047_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_047_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_047_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_047_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_047_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_047_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm048 */ #define XPMC_XPPU_APERPERM_048 ( ( XPMC_XPPU_BASEADDR ) + 0x000010C0UL ) #define XPMC_XPPU_APERPERM_048_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_048_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_048_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_048_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_048_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_048_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_048_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_048_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_048_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_048_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_048_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_048_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_048_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm049 */ #define XPMC_XPPU_APERPERM_049 ( ( XPMC_XPPU_BASEADDR ) + 0x000010C4UL ) #define XPMC_XPPU_APERPERM_049_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_049_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_049_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_049_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_049_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_049_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_049_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_049_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_049_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_049_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_049_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_049_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_049_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm050 */ #define XPMC_XPPU_APERPERM_050 ( ( XPMC_XPPU_BASEADDR ) + 0x000010C8UL ) #define XPMC_XPPU_APERPERM_050_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_050_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_050_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_050_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_050_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_050_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_050_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_050_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_050_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_050_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_050_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_050_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_050_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm051 */ #define XPMC_XPPU_APERPERM_051 ( ( XPMC_XPPU_BASEADDR ) + 0x000010CCUL ) #define XPMC_XPPU_APERPERM_051_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_051_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_051_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_051_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_051_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_051_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_051_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_051_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_051_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_051_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_051_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_051_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_051_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm052 */ #define XPMC_XPPU_APERPERM_052 ( ( XPMC_XPPU_BASEADDR ) + 0x000010D0UL ) #define XPMC_XPPU_APERPERM_052_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_052_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_052_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_052_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_052_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_052_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_052_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_052_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_052_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_052_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_052_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_052_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_052_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm053 */ #define XPMC_XPPU_APERPERM_053 ( ( XPMC_XPPU_BASEADDR ) + 0x000010D4UL ) #define XPMC_XPPU_APERPERM_053_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_053_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_053_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_053_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_053_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_053_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_053_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_053_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_053_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_053_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_053_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_053_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_053_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm054 */ #define XPMC_XPPU_APERPERM_054 ( ( XPMC_XPPU_BASEADDR ) + 0x000010D8UL ) #define XPMC_XPPU_APERPERM_054_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_054_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_054_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_054_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_054_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_054_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_054_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_054_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_054_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_054_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_054_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_054_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_054_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm055 */ #define XPMC_XPPU_APERPERM_055 ( ( XPMC_XPPU_BASEADDR ) + 0x000010DCUL ) #define XPMC_XPPU_APERPERM_055_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_055_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_055_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_055_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_055_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_055_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_055_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_055_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_055_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_055_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_055_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_055_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_055_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm056 */ #define XPMC_XPPU_APERPERM_056 ( ( XPMC_XPPU_BASEADDR ) + 0x000010E0UL ) #define XPMC_XPPU_APERPERM_056_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_056_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_056_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_056_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_056_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_056_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_056_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_056_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_056_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_056_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_056_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_056_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_056_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm057 */ #define XPMC_XPPU_APERPERM_057 ( ( XPMC_XPPU_BASEADDR ) + 0x000010E4UL ) #define XPMC_XPPU_APERPERM_057_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_057_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_057_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_057_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_057_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_057_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_057_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_057_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_057_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_057_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_057_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_057_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_057_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm058 */ #define XPMC_XPPU_APERPERM_058 ( ( XPMC_XPPU_BASEADDR ) + 0x000010E8UL ) #define XPMC_XPPU_APERPERM_058_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_058_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_058_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_058_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_058_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_058_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_058_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_058_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_058_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_058_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_058_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_058_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_058_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm059 */ #define XPMC_XPPU_APERPERM_059 ( ( XPMC_XPPU_BASEADDR ) + 0x000010ECUL ) #define XPMC_XPPU_APERPERM_059_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_059_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_059_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_059_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_059_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_059_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_059_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_059_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_059_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_059_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_059_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_059_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_059_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm060 */ #define XPMC_XPPU_APERPERM_060 ( ( XPMC_XPPU_BASEADDR ) + 0x000010F0UL ) #define XPMC_XPPU_APERPERM_060_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_060_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_060_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_060_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_060_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_060_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_060_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_060_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_060_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_060_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_060_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_060_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_060_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm061 */ #define XPMC_XPPU_APERPERM_061 ( ( XPMC_XPPU_BASEADDR ) + 0x000010F4UL ) #define XPMC_XPPU_APERPERM_061_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_061_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_061_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_061_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_061_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_061_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_061_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_061_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_061_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_061_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_061_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_061_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_061_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm062 */ #define XPMC_XPPU_APERPERM_062 ( ( XPMC_XPPU_BASEADDR ) + 0x000010F8UL ) #define XPMC_XPPU_APERPERM_062_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_062_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_062_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_062_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_062_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_062_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_062_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_062_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_062_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_062_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_062_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_062_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_062_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm063 */ #define XPMC_XPPU_APERPERM_063 ( ( XPMC_XPPU_BASEADDR ) + 0x000010FCUL ) #define XPMC_XPPU_APERPERM_063_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_063_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_063_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_063_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_063_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_063_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_063_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_063_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_063_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_063_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_063_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_063_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_063_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm064 */ #define XPMC_XPPU_APERPERM_064 ( ( XPMC_XPPU_BASEADDR ) + 0x00001100UL ) #define XPMC_XPPU_APERPERM_064_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_064_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_064_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_064_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_064_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_064_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_064_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_064_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_064_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_064_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_064_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_064_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_064_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm065 */ #define XPMC_XPPU_APERPERM_065 ( ( XPMC_XPPU_BASEADDR ) + 0x00001104UL ) #define XPMC_XPPU_APERPERM_065_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_065_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_065_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_065_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_065_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_065_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_065_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_065_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_065_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_065_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_065_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_065_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_065_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm066 */ #define XPMC_XPPU_APERPERM_066 ( ( XPMC_XPPU_BASEADDR ) + 0x00001108UL ) #define XPMC_XPPU_APERPERM_066_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_066_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_066_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_066_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_066_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_066_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_066_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_066_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_066_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_066_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_066_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_066_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_066_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm067 */ #define XPMC_XPPU_APERPERM_067 ( ( XPMC_XPPU_BASEADDR ) + 0x0000110CUL ) #define XPMC_XPPU_APERPERM_067_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_067_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_067_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_067_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_067_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_067_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_067_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_067_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_067_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_067_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_067_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_067_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_067_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm068 */ #define XPMC_XPPU_APERPERM_068 ( ( XPMC_XPPU_BASEADDR ) + 0x00001110UL ) #define XPMC_XPPU_APERPERM_068_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_068_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_068_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_068_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_068_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_068_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_068_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_068_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_068_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_068_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_068_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_068_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_068_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm069 */ #define XPMC_XPPU_APERPERM_069 ( ( XPMC_XPPU_BASEADDR ) + 0x00001114UL ) #define XPMC_XPPU_APERPERM_069_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_069_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_069_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_069_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_069_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_069_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_069_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_069_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_069_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_069_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_069_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_069_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_069_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm070 */ #define XPMC_XPPU_APERPERM_070 ( ( XPMC_XPPU_BASEADDR ) + 0x00001118UL ) #define XPMC_XPPU_APERPERM_070_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_070_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_070_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_070_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_070_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_070_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_070_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_070_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_070_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_070_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_070_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_070_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_070_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm071 */ #define XPMC_XPPU_APERPERM_071 ( ( XPMC_XPPU_BASEADDR ) + 0x0000111CUL ) #define XPMC_XPPU_APERPERM_071_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_071_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_071_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_071_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_071_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_071_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_071_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_071_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_071_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_071_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_071_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_071_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_071_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm072 */ #define XPMC_XPPU_APERPERM_072 ( ( XPMC_XPPU_BASEADDR ) + 0x00001120UL ) #define XPMC_XPPU_APERPERM_072_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_072_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_072_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_072_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_072_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_072_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_072_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_072_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_072_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_072_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_072_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_072_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_072_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm073 */ #define XPMC_XPPU_APERPERM_073 ( ( XPMC_XPPU_BASEADDR ) + 0x00001124UL ) #define XPMC_XPPU_APERPERM_073_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_073_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_073_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_073_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_073_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_073_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_073_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_073_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_073_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_073_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_073_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_073_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_073_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm074 */ #define XPMC_XPPU_APERPERM_074 ( ( XPMC_XPPU_BASEADDR ) + 0x00001128UL ) #define XPMC_XPPU_APERPERM_074_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_074_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_074_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_074_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_074_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_074_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_074_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_074_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_074_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_074_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_074_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_074_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_074_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm075 */ #define XPMC_XPPU_APERPERM_075 ( ( XPMC_XPPU_BASEADDR ) + 0x0000112CUL ) #define XPMC_XPPU_APERPERM_075_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_075_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_075_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_075_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_075_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_075_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_075_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_075_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_075_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_075_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_075_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_075_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_075_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm076 */ #define XPMC_XPPU_APERPERM_076 ( ( XPMC_XPPU_BASEADDR ) + 0x00001130UL ) #define XPMC_XPPU_APERPERM_076_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_076_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_076_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_076_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_076_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_076_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_076_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_076_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_076_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_076_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_076_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_076_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_076_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm077 */ #define XPMC_XPPU_APERPERM_077 ( ( XPMC_XPPU_BASEADDR ) + 0x00001134UL ) #define XPMC_XPPU_APERPERM_077_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_077_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_077_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_077_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_077_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_077_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_077_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_077_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_077_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_077_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_077_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_077_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_077_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm078 */ #define XPMC_XPPU_APERPERM_078 ( ( XPMC_XPPU_BASEADDR ) + 0x00001138UL ) #define XPMC_XPPU_APERPERM_078_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_078_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_078_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_078_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_078_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_078_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_078_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_078_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_078_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_078_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_078_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_078_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_078_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm079 */ #define XPMC_XPPU_APERPERM_079 ( ( XPMC_XPPU_BASEADDR ) + 0x0000113CUL ) #define XPMC_XPPU_APERPERM_079_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_079_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_079_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_079_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_079_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_079_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_079_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_079_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_079_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_079_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_079_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_079_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_079_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm080 */ #define XPMC_XPPU_APERPERM_080 ( ( XPMC_XPPU_BASEADDR ) + 0x00001140UL ) #define XPMC_XPPU_APERPERM_080_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_080_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_080_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_080_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_080_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_080_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_080_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_080_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_080_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_080_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_080_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_080_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_080_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm081 */ #define XPMC_XPPU_APERPERM_081 ( ( XPMC_XPPU_BASEADDR ) + 0x00001144UL ) #define XPMC_XPPU_APERPERM_081_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_081_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_081_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_081_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_081_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_081_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_081_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_081_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_081_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_081_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_081_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_081_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_081_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm082 */ #define XPMC_XPPU_APERPERM_082 ( ( XPMC_XPPU_BASEADDR ) + 0x00001148UL ) #define XPMC_XPPU_APERPERM_082_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_082_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_082_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_082_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_082_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_082_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_082_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_082_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_082_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_082_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_082_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_082_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_082_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm083 */ #define XPMC_XPPU_APERPERM_083 ( ( XPMC_XPPU_BASEADDR ) + 0x0000114CUL ) #define XPMC_XPPU_APERPERM_083_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_083_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_083_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_083_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_083_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_083_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_083_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_083_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_083_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_083_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_083_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_083_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_083_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm084 */ #define XPMC_XPPU_APERPERM_084 ( ( XPMC_XPPU_BASEADDR ) + 0x00001150UL ) #define XPMC_XPPU_APERPERM_084_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_084_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_084_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_084_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_084_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_084_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_084_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_084_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_084_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_084_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_084_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_084_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_084_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm085 */ #define XPMC_XPPU_APERPERM_085 ( ( XPMC_XPPU_BASEADDR ) + 0x00001154UL ) #define XPMC_XPPU_APERPERM_085_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_085_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_085_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_085_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_085_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_085_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_085_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_085_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_085_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_085_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_085_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_085_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_085_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm086 */ #define XPMC_XPPU_APERPERM_086 ( ( XPMC_XPPU_BASEADDR ) + 0x00001158UL ) #define XPMC_XPPU_APERPERM_086_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_086_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_086_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_086_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_086_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_086_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_086_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_086_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_086_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_086_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_086_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_086_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_086_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm087 */ #define XPMC_XPPU_APERPERM_087 ( ( XPMC_XPPU_BASEADDR ) + 0x0000115CUL ) #define XPMC_XPPU_APERPERM_087_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_087_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_087_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_087_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_087_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_087_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_087_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_087_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_087_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_087_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_087_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_087_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_087_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm088 */ #define XPMC_XPPU_APERPERM_088 ( ( XPMC_XPPU_BASEADDR ) + 0x00001160UL ) #define XPMC_XPPU_APERPERM_088_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_088_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_088_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_088_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_088_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_088_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_088_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_088_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_088_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_088_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_088_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_088_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_088_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm089 */ #define XPMC_XPPU_APERPERM_089 ( ( XPMC_XPPU_BASEADDR ) + 0x00001164UL ) #define XPMC_XPPU_APERPERM_089_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_089_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_089_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_089_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_089_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_089_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_089_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_089_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_089_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_089_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_089_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_089_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_089_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm090 */ #define XPMC_XPPU_APERPERM_090 ( ( XPMC_XPPU_BASEADDR ) + 0x00001168UL ) #define XPMC_XPPU_APERPERM_090_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_090_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_090_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_090_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_090_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_090_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_090_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_090_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_090_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_090_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_090_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_090_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_090_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm091 */ #define XPMC_XPPU_APERPERM_091 ( ( XPMC_XPPU_BASEADDR ) + 0x0000116CUL ) #define XPMC_XPPU_APERPERM_091_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_091_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_091_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_091_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_091_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_091_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_091_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_091_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_091_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_091_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_091_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_091_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_091_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm092 */ #define XPMC_XPPU_APERPERM_092 ( ( XPMC_XPPU_BASEADDR ) + 0x00001170UL ) #define XPMC_XPPU_APERPERM_092_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_092_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_092_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_092_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_092_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_092_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_092_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_092_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_092_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_092_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_092_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_092_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_092_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm093 */ #define XPMC_XPPU_APERPERM_093 ( ( XPMC_XPPU_BASEADDR ) + 0x00001174UL ) #define XPMC_XPPU_APERPERM_093_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_093_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_093_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_093_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_093_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_093_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_093_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_093_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_093_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_093_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_093_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_093_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_093_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm094 */ #define XPMC_XPPU_APERPERM_094 ( ( XPMC_XPPU_BASEADDR ) + 0x00001178UL ) #define XPMC_XPPU_APERPERM_094_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_094_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_094_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_094_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_094_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_094_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_094_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_094_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_094_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_094_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_094_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_094_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_094_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm095 */ #define XPMC_XPPU_APERPERM_095 ( ( XPMC_XPPU_BASEADDR ) + 0x0000117CUL ) #define XPMC_XPPU_APERPERM_095_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_095_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_095_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_095_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_095_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_095_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_095_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_095_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_095_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_095_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_095_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_095_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_095_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm096 */ #define XPMC_XPPU_APERPERM_096 ( ( XPMC_XPPU_BASEADDR ) + 0x00001180UL ) #define XPMC_XPPU_APERPERM_096_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_096_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_096_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_096_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_096_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_096_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_096_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_096_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_096_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_096_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_096_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_096_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_096_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm097 */ #define XPMC_XPPU_APERPERM_097 ( ( XPMC_XPPU_BASEADDR ) + 0x00001184UL ) #define XPMC_XPPU_APERPERM_097_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_097_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_097_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_097_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_097_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_097_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_097_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_097_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_097_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_097_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_097_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_097_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_097_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm098 */ #define XPMC_XPPU_APERPERM_098 ( ( XPMC_XPPU_BASEADDR ) + 0x00001188UL ) #define XPMC_XPPU_APERPERM_098_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_098_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_098_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_098_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_098_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_098_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_098_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_098_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_098_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_098_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_098_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_098_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_098_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm099 */ #define XPMC_XPPU_APERPERM_099 ( ( XPMC_XPPU_BASEADDR ) + 0x0000118CUL ) #define XPMC_XPPU_APERPERM_099_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_099_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_099_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_099_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_099_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_099_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_099_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_099_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_099_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_099_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_099_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_099_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_099_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm100 */ #define XPMC_XPPU_APERPERM_100 ( ( XPMC_XPPU_BASEADDR ) + 0x00001190UL ) #define XPMC_XPPU_APERPERM_100_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_100_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_100_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_100_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_100_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_100_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_100_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_100_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_100_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_100_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_100_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_100_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_100_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm101 */ #define XPMC_XPPU_APERPERM_101 ( ( XPMC_XPPU_BASEADDR ) + 0x00001194UL ) #define XPMC_XPPU_APERPERM_101_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_101_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_101_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_101_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_101_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_101_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_101_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_101_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_101_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_101_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_101_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_101_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_101_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm102 */ #define XPMC_XPPU_APERPERM_102 ( ( XPMC_XPPU_BASEADDR ) + 0x00001198UL ) #define XPMC_XPPU_APERPERM_102_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_102_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_102_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_102_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_102_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_102_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_102_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_102_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_102_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_102_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_102_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_102_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_102_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm103 */ #define XPMC_XPPU_APERPERM_103 ( ( XPMC_XPPU_BASEADDR ) + 0x0000119CUL ) #define XPMC_XPPU_APERPERM_103_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_103_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_103_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_103_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_103_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_103_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_103_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_103_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_103_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_103_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_103_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_103_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_103_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm104 */ #define XPMC_XPPU_APERPERM_104 ( ( XPMC_XPPU_BASEADDR ) + 0x000011A0UL ) #define XPMC_XPPU_APERPERM_104_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_104_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_104_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_104_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_104_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_104_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_104_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_104_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_104_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_104_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_104_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_104_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_104_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm105 */ #define XPMC_XPPU_APERPERM_105 ( ( XPMC_XPPU_BASEADDR ) + 0x000011A4UL ) #define XPMC_XPPU_APERPERM_105_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_105_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_105_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_105_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_105_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_105_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_105_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_105_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_105_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_105_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_105_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_105_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_105_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm106 */ #define XPMC_XPPU_APERPERM_106 ( ( XPMC_XPPU_BASEADDR ) + 0x000011A8UL ) #define XPMC_XPPU_APERPERM_106_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_106_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_106_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_106_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_106_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_106_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_106_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_106_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_106_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_106_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_106_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_106_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_106_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm107 */ #define XPMC_XPPU_APERPERM_107 ( ( XPMC_XPPU_BASEADDR ) + 0x000011ACUL ) #define XPMC_XPPU_APERPERM_107_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_107_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_107_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_107_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_107_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_107_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_107_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_107_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_107_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_107_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_107_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_107_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_107_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm108 */ #define XPMC_XPPU_APERPERM_108 ( ( XPMC_XPPU_BASEADDR ) + 0x000011B0UL ) #define XPMC_XPPU_APERPERM_108_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_108_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_108_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_108_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_108_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_108_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_108_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_108_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_108_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_108_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_108_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_108_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_108_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm109 */ #define XPMC_XPPU_APERPERM_109 ( ( XPMC_XPPU_BASEADDR ) + 0x000011B4UL ) #define XPMC_XPPU_APERPERM_109_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_109_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_109_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_109_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_109_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_109_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_109_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_109_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_109_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_109_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_109_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_109_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_109_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm110 */ #define XPMC_XPPU_APERPERM_110 ( ( XPMC_XPPU_BASEADDR ) + 0x000011B8UL ) #define XPMC_XPPU_APERPERM_110_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_110_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_110_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_110_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_110_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_110_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_110_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_110_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_110_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_110_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_110_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_110_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_110_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm111 */ #define XPMC_XPPU_APERPERM_111 ( ( XPMC_XPPU_BASEADDR ) + 0x000011BCUL ) #define XPMC_XPPU_APERPERM_111_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_111_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_111_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_111_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_111_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_111_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_111_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_111_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_111_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_111_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_111_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_111_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_111_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm112 */ #define XPMC_XPPU_APERPERM_112 ( ( XPMC_XPPU_BASEADDR ) + 0x000011C0UL ) #define XPMC_XPPU_APERPERM_112_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_112_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_112_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_112_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_112_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_112_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_112_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_112_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_112_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_112_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_112_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_112_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_112_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm113 */ #define XPMC_XPPU_APERPERM_113 ( ( XPMC_XPPU_BASEADDR ) + 0x000011C4UL ) #define XPMC_XPPU_APERPERM_113_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_113_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_113_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_113_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_113_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_113_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_113_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_113_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_113_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_113_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_113_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_113_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_113_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm114 */ #define XPMC_XPPU_APERPERM_114 ( ( XPMC_XPPU_BASEADDR ) + 0x000011C8UL ) #define XPMC_XPPU_APERPERM_114_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_114_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_114_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_114_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_114_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_114_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_114_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_114_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_114_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_114_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_114_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_114_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_114_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm115 */ #define XPMC_XPPU_APERPERM_115 ( ( XPMC_XPPU_BASEADDR ) + 0x000011CCUL ) #define XPMC_XPPU_APERPERM_115_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_115_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_115_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_115_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_115_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_115_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_115_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_115_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_115_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_115_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_115_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_115_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_115_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm116 */ #define XPMC_XPPU_APERPERM_116 ( ( XPMC_XPPU_BASEADDR ) + 0x000011D0UL ) #define XPMC_XPPU_APERPERM_116_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_116_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_116_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_116_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_116_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_116_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_116_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_116_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_116_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_116_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_116_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_116_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_116_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm117 */ #define XPMC_XPPU_APERPERM_117 ( ( XPMC_XPPU_BASEADDR ) + 0x000011D4UL ) #define XPMC_XPPU_APERPERM_117_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_117_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_117_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_117_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_117_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_117_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_117_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_117_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_117_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_117_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_117_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_117_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_117_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm118 */ #define XPMC_XPPU_APERPERM_118 ( ( XPMC_XPPU_BASEADDR ) + 0x000011D8UL ) #define XPMC_XPPU_APERPERM_118_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_118_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_118_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_118_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_118_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_118_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_118_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_118_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_118_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_118_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_118_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_118_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_118_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm119 */ #define XPMC_XPPU_APERPERM_119 ( ( XPMC_XPPU_BASEADDR ) + 0x000011DCUL ) #define XPMC_XPPU_APERPERM_119_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_119_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_119_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_119_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_119_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_119_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_119_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_119_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_119_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_119_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_119_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_119_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_119_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm120 */ #define XPMC_XPPU_APERPERM_120 ( ( XPMC_XPPU_BASEADDR ) + 0x000011E0UL ) #define XPMC_XPPU_APERPERM_120_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_120_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_120_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_120_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_120_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_120_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_120_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_120_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_120_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_120_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_120_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_120_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_120_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm121 */ #define XPMC_XPPU_APERPERM_121 ( ( XPMC_XPPU_BASEADDR ) + 0x000011E4UL ) #define XPMC_XPPU_APERPERM_121_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_121_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_121_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_121_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_121_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_121_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_121_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_121_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_121_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_121_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_121_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_121_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_121_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm122 */ #define XPMC_XPPU_APERPERM_122 ( ( XPMC_XPPU_BASEADDR ) + 0x000011E8UL ) #define XPMC_XPPU_APERPERM_122_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_122_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_122_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_122_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_122_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_122_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_122_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_122_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_122_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_122_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_122_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_122_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_122_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm123 */ #define XPMC_XPPU_APERPERM_123 ( ( XPMC_XPPU_BASEADDR ) + 0x000011ECUL ) #define XPMC_XPPU_APERPERM_123_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_123_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_123_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_123_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_123_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_123_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_123_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_123_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_123_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_123_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_123_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_123_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_123_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm124 */ #define XPMC_XPPU_APERPERM_124 ( ( XPMC_XPPU_BASEADDR ) + 0x000011F0UL ) #define XPMC_XPPU_APERPERM_124_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_124_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_124_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_124_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_124_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_124_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_124_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_124_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_124_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_124_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_124_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_124_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_124_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm125 */ #define XPMC_XPPU_APERPERM_125 ( ( XPMC_XPPU_BASEADDR ) + 0x000011F4UL ) #define XPMC_XPPU_APERPERM_125_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_125_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_125_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_125_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_125_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_125_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_125_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_125_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_125_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_125_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_125_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_125_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_125_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm126 */ #define XPMC_XPPU_APERPERM_126 ( ( XPMC_XPPU_BASEADDR ) + 0x000011F8UL ) #define XPMC_XPPU_APERPERM_126_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_126_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_126_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_126_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_126_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_126_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_126_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_126_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_126_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_126_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_126_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_126_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_126_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm127 */ #define XPMC_XPPU_APERPERM_127 ( ( XPMC_XPPU_BASEADDR ) + 0x000011FCUL ) #define XPMC_XPPU_APERPERM_127_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_127_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_127_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_127_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_127_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_127_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_127_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_127_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_127_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_127_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_127_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_127_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_127_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm128 */ #define XPMC_XPPU_APERPERM_128 ( ( XPMC_XPPU_BASEADDR ) + 0x00001200UL ) #define XPMC_XPPU_APERPERM_128_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_128_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_128_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_128_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_128_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_128_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_128_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_128_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_128_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_128_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_128_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_128_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_128_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm129 */ #define XPMC_XPPU_APERPERM_129 ( ( XPMC_XPPU_BASEADDR ) + 0x00001204UL ) #define XPMC_XPPU_APERPERM_129_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_129_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_129_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_129_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_129_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_129_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_129_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_129_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_129_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_129_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_129_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_129_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_129_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm130 */ #define XPMC_XPPU_APERPERM_130 ( ( XPMC_XPPU_BASEADDR ) + 0x00001208UL ) #define XPMC_XPPU_APERPERM_130_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_130_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_130_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_130_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_130_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_130_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_130_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_130_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_130_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_130_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_130_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_130_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_130_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm131 */ #define XPMC_XPPU_APERPERM_131 ( ( XPMC_XPPU_BASEADDR ) + 0x0000120CUL ) #define XPMC_XPPU_APERPERM_131_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_131_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_131_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_131_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_131_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_131_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_131_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_131_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_131_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_131_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_131_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_131_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_131_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm132 */ #define XPMC_XPPU_APERPERM_132 ( ( XPMC_XPPU_BASEADDR ) + 0x00001210UL ) #define XPMC_XPPU_APERPERM_132_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_132_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_132_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_132_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_132_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_132_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_132_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_132_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_132_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_132_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_132_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_132_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_132_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm133 */ #define XPMC_XPPU_APERPERM_133 ( ( XPMC_XPPU_BASEADDR ) + 0x00001214UL ) #define XPMC_XPPU_APERPERM_133_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_133_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_133_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_133_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_133_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_133_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_133_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_133_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_133_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_133_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_133_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_133_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_133_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm134 */ #define XPMC_XPPU_APERPERM_134 ( ( XPMC_XPPU_BASEADDR ) + 0x00001218UL ) #define XPMC_XPPU_APERPERM_134_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_134_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_134_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_134_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_134_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_134_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_134_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_134_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_134_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_134_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_134_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_134_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_134_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm135 */ #define XPMC_XPPU_APERPERM_135 ( ( XPMC_XPPU_BASEADDR ) + 0x0000121CUL ) #define XPMC_XPPU_APERPERM_135_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_135_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_135_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_135_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_135_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_135_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_135_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_135_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_135_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_135_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_135_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_135_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_135_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm136 */ #define XPMC_XPPU_APERPERM_136 ( ( XPMC_XPPU_BASEADDR ) + 0x00001220UL ) #define XPMC_XPPU_APERPERM_136_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_136_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_136_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_136_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_136_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_136_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_136_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_136_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_136_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_136_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_136_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_136_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_136_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm137 */ #define XPMC_XPPU_APERPERM_137 ( ( XPMC_XPPU_BASEADDR ) + 0x00001224UL ) #define XPMC_XPPU_APERPERM_137_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_137_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_137_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_137_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_137_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_137_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_137_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_137_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_137_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_137_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_137_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_137_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_137_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm138 */ #define XPMC_XPPU_APERPERM_138 ( ( XPMC_XPPU_BASEADDR ) + 0x00001228UL ) #define XPMC_XPPU_APERPERM_138_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_138_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_138_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_138_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_138_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_138_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_138_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_138_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_138_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_138_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_138_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_138_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_138_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm139 */ #define XPMC_XPPU_APERPERM_139 ( ( XPMC_XPPU_BASEADDR ) + 0x0000122CUL ) #define XPMC_XPPU_APERPERM_139_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_139_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_139_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_139_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_139_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_139_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_139_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_139_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_139_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_139_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_139_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_139_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_139_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm140 */ #define XPMC_XPPU_APERPERM_140 ( ( XPMC_XPPU_BASEADDR ) + 0x00001230UL ) #define XPMC_XPPU_APERPERM_140_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_140_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_140_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_140_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_140_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_140_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_140_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_140_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_140_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_140_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_140_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_140_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_140_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm141 */ #define XPMC_XPPU_APERPERM_141 ( ( XPMC_XPPU_BASEADDR ) + 0x00001234UL ) #define XPMC_XPPU_APERPERM_141_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_141_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_141_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_141_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_141_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_141_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_141_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_141_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_141_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_141_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_141_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_141_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_141_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm142 */ #define XPMC_XPPU_APERPERM_142 ( ( XPMC_XPPU_BASEADDR ) + 0x00001238UL ) #define XPMC_XPPU_APERPERM_142_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_142_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_142_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_142_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_142_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_142_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_142_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_142_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_142_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_142_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_142_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_142_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_142_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm143 */ #define XPMC_XPPU_APERPERM_143 ( ( XPMC_XPPU_BASEADDR ) + 0x0000123CUL ) #define XPMC_XPPU_APERPERM_143_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_143_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_143_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_143_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_143_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_143_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_143_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_143_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_143_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_143_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_143_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_143_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_143_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm144 */ #define XPMC_XPPU_APERPERM_144 ( ( XPMC_XPPU_BASEADDR ) + 0x00001240UL ) #define XPMC_XPPU_APERPERM_144_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_144_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_144_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_144_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_144_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_144_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_144_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_144_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_144_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_144_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_144_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_144_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_144_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm145 */ #define XPMC_XPPU_APERPERM_145 ( ( XPMC_XPPU_BASEADDR ) + 0x00001244UL ) #define XPMC_XPPU_APERPERM_145_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_145_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_145_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_145_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_145_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_145_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_145_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_145_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_145_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_145_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_145_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_145_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_145_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm146 */ #define XPMC_XPPU_APERPERM_146 ( ( XPMC_XPPU_BASEADDR ) + 0x00001248UL ) #define XPMC_XPPU_APERPERM_146_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_146_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_146_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_146_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_146_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_146_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_146_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_146_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_146_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_146_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_146_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_146_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_146_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm147 */ #define XPMC_XPPU_APERPERM_147 ( ( XPMC_XPPU_BASEADDR ) + 0x0000124CUL ) #define XPMC_XPPU_APERPERM_147_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_147_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_147_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_147_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_147_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_147_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_147_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_147_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_147_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_147_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_147_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_147_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_147_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm148 */ #define XPMC_XPPU_APERPERM_148 ( ( XPMC_XPPU_BASEADDR ) + 0x00001250UL ) #define XPMC_XPPU_APERPERM_148_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_148_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_148_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_148_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_148_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_148_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_148_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_148_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_148_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_148_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_148_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_148_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_148_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm149 */ #define XPMC_XPPU_APERPERM_149 ( ( XPMC_XPPU_BASEADDR ) + 0x00001254UL ) #define XPMC_XPPU_APERPERM_149_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_149_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_149_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_149_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_149_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_149_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_149_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_149_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_149_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_149_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_149_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_149_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_149_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm150 */ #define XPMC_XPPU_APERPERM_150 ( ( XPMC_XPPU_BASEADDR ) + 0x00001258UL ) #define XPMC_XPPU_APERPERM_150_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_150_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_150_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_150_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_150_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_150_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_150_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_150_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_150_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_150_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_150_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_150_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_150_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm151 */ #define XPMC_XPPU_APERPERM_151 ( ( XPMC_XPPU_BASEADDR ) + 0x0000125CUL ) #define XPMC_XPPU_APERPERM_151_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_151_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_151_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_151_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_151_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_151_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_151_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_151_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_151_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_151_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_151_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_151_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_151_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm152 */ #define XPMC_XPPU_APERPERM_152 ( ( XPMC_XPPU_BASEADDR ) + 0x00001260UL ) #define XPMC_XPPU_APERPERM_152_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_152_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_152_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_152_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_152_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_152_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_152_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_152_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_152_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_152_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_152_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_152_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_152_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm153 */ #define XPMC_XPPU_APERPERM_153 ( ( XPMC_XPPU_BASEADDR ) + 0x00001264UL ) #define XPMC_XPPU_APERPERM_153_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_153_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_153_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_153_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_153_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_153_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_153_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_153_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_153_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_153_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_153_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_153_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_153_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm154 */ #define XPMC_XPPU_APERPERM_154 ( ( XPMC_XPPU_BASEADDR ) + 0x00001268UL ) #define XPMC_XPPU_APERPERM_154_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_154_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_154_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_154_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_154_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_154_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_154_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_154_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_154_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_154_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_154_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_154_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_154_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm155 */ #define XPMC_XPPU_APERPERM_155 ( ( XPMC_XPPU_BASEADDR ) + 0x0000126CUL ) #define XPMC_XPPU_APERPERM_155_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_155_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_155_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_155_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_155_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_155_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_155_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_155_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_155_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_155_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_155_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_155_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_155_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm156 */ #define XPMC_XPPU_APERPERM_156 ( ( XPMC_XPPU_BASEADDR ) + 0x00001270UL ) #define XPMC_XPPU_APERPERM_156_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_156_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_156_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_156_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_156_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_156_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_156_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_156_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_156_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_156_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_156_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_156_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_156_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm157 */ #define XPMC_XPPU_APERPERM_157 ( ( XPMC_XPPU_BASEADDR ) + 0x00001274UL ) #define XPMC_XPPU_APERPERM_157_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_157_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_157_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_157_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_157_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_157_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_157_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_157_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_157_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_157_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_157_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_157_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_157_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm158 */ #define XPMC_XPPU_APERPERM_158 ( ( XPMC_XPPU_BASEADDR ) + 0x00001278UL ) #define XPMC_XPPU_APERPERM_158_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_158_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_158_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_158_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_158_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_158_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_158_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_158_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_158_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_158_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_158_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_158_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_158_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm159 */ #define XPMC_XPPU_APERPERM_159 ( ( XPMC_XPPU_BASEADDR ) + 0x0000127CUL ) #define XPMC_XPPU_APERPERM_159_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_159_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_159_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_159_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_159_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_159_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_159_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_159_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_159_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_159_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_159_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_159_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_159_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm160 */ #define XPMC_XPPU_APERPERM_160 ( ( XPMC_XPPU_BASEADDR ) + 0x00001280UL ) #define XPMC_XPPU_APERPERM_160_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_160_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_160_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_160_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_160_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_160_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_160_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_160_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_160_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_160_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_160_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_160_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_160_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm161 */ #define XPMC_XPPU_APERPERM_161 ( ( XPMC_XPPU_BASEADDR ) + 0x00001284UL ) #define XPMC_XPPU_APERPERM_161_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_161_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_161_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_161_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_161_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_161_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_161_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_161_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_161_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_161_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_161_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_161_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_161_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm162 */ #define XPMC_XPPU_APERPERM_162 ( ( XPMC_XPPU_BASEADDR ) + 0x00001288UL ) #define XPMC_XPPU_APERPERM_162_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_162_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_162_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_162_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_162_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_162_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_162_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_162_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_162_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_162_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_162_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_162_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_162_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm163 */ #define XPMC_XPPU_APERPERM_163 ( ( XPMC_XPPU_BASEADDR ) + 0x0000128CUL ) #define XPMC_XPPU_APERPERM_163_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_163_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_163_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_163_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_163_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_163_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_163_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_163_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_163_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_163_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_163_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_163_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_163_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm164 */ #define XPMC_XPPU_APERPERM_164 ( ( XPMC_XPPU_BASEADDR ) + 0x00001290UL ) #define XPMC_XPPU_APERPERM_164_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_164_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_164_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_164_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_164_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_164_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_164_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_164_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_164_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_164_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_164_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_164_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_164_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm165 */ #define XPMC_XPPU_APERPERM_165 ( ( XPMC_XPPU_BASEADDR ) + 0x00001294UL ) #define XPMC_XPPU_APERPERM_165_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_165_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_165_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_165_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_165_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_165_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_165_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_165_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_165_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_165_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_165_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_165_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_165_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm166 */ #define XPMC_XPPU_APERPERM_166 ( ( XPMC_XPPU_BASEADDR ) + 0x00001298UL ) #define XPMC_XPPU_APERPERM_166_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_166_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_166_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_166_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_166_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_166_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_166_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_166_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_166_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_166_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_166_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_166_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_166_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm167 */ #define XPMC_XPPU_APERPERM_167 ( ( XPMC_XPPU_BASEADDR ) + 0x0000129CUL ) #define XPMC_XPPU_APERPERM_167_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_167_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_167_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_167_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_167_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_167_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_167_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_167_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_167_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_167_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_167_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_167_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_167_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm168 */ #define XPMC_XPPU_APERPERM_168 ( ( XPMC_XPPU_BASEADDR ) + 0x000012A0UL ) #define XPMC_XPPU_APERPERM_168_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_168_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_168_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_168_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_168_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_168_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_168_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_168_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_168_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_168_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_168_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_168_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_168_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm169 */ #define XPMC_XPPU_APERPERM_169 ( ( XPMC_XPPU_BASEADDR ) + 0x000012A4UL ) #define XPMC_XPPU_APERPERM_169_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_169_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_169_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_169_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_169_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_169_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_169_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_169_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_169_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_169_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_169_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_169_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_169_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm170 */ #define XPMC_XPPU_APERPERM_170 ( ( XPMC_XPPU_BASEADDR ) + 0x000012A8UL ) #define XPMC_XPPU_APERPERM_170_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_170_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_170_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_170_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_170_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_170_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_170_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_170_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_170_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_170_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_170_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_170_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_170_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm171 */ #define XPMC_XPPU_APERPERM_171 ( ( XPMC_XPPU_BASEADDR ) + 0x000012ACUL ) #define XPMC_XPPU_APERPERM_171_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_171_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_171_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_171_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_171_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_171_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_171_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_171_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_171_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_171_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_171_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_171_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_171_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm172 */ #define XPMC_XPPU_APERPERM_172 ( ( XPMC_XPPU_BASEADDR ) + 0x000012B0UL ) #define XPMC_XPPU_APERPERM_172_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_172_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_172_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_172_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_172_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_172_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_172_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_172_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_172_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_172_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_172_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_172_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_172_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm173 */ #define XPMC_XPPU_APERPERM_173 ( ( XPMC_XPPU_BASEADDR ) + 0x000012B4UL ) #define XPMC_XPPU_APERPERM_173_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_173_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_173_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_173_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_173_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_173_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_173_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_173_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_173_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_173_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_173_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_173_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_173_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm174 */ #define XPMC_XPPU_APERPERM_174 ( ( XPMC_XPPU_BASEADDR ) + 0x000012B8UL ) #define XPMC_XPPU_APERPERM_174_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_174_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_174_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_174_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_174_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_174_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_174_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_174_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_174_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_174_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_174_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_174_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_174_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm175 */ #define XPMC_XPPU_APERPERM_175 ( ( XPMC_XPPU_BASEADDR ) + 0x000012BCUL ) #define XPMC_XPPU_APERPERM_175_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_175_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_175_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_175_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_175_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_175_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_175_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_175_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_175_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_175_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_175_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_175_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_175_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm176 */ #define XPMC_XPPU_APERPERM_176 ( ( XPMC_XPPU_BASEADDR ) + 0x000012C0UL ) #define XPMC_XPPU_APERPERM_176_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_176_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_176_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_176_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_176_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_176_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_176_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_176_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_176_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_176_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_176_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_176_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_176_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm177 */ #define XPMC_XPPU_APERPERM_177 ( ( XPMC_XPPU_BASEADDR ) + 0x000012C4UL ) #define XPMC_XPPU_APERPERM_177_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_177_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_177_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_177_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_177_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_177_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_177_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_177_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_177_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_177_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_177_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_177_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_177_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm178 */ #define XPMC_XPPU_APERPERM_178 ( ( XPMC_XPPU_BASEADDR ) + 0x000012C8UL ) #define XPMC_XPPU_APERPERM_178_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_178_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_178_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_178_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_178_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_178_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_178_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_178_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_178_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_178_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_178_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_178_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_178_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm179 */ #define XPMC_XPPU_APERPERM_179 ( ( XPMC_XPPU_BASEADDR ) + 0x000012CCUL ) #define XPMC_XPPU_APERPERM_179_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_179_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_179_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_179_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_179_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_179_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_179_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_179_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_179_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_179_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_179_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_179_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_179_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm180 */ #define XPMC_XPPU_APERPERM_180 ( ( XPMC_XPPU_BASEADDR ) + 0x000012D0UL ) #define XPMC_XPPU_APERPERM_180_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_180_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_180_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_180_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_180_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_180_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_180_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_180_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_180_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_180_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_180_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_180_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_180_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm181 */ #define XPMC_XPPU_APERPERM_181 ( ( XPMC_XPPU_BASEADDR ) + 0x000012D4UL ) #define XPMC_XPPU_APERPERM_181_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_181_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_181_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_181_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_181_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_181_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_181_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_181_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_181_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_181_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_181_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_181_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_181_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm182 */ #define XPMC_XPPU_APERPERM_182 ( ( XPMC_XPPU_BASEADDR ) + 0x000012D8UL ) #define XPMC_XPPU_APERPERM_182_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_182_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_182_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_182_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_182_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_182_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_182_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_182_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_182_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_182_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_182_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_182_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_182_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm183 */ #define XPMC_XPPU_APERPERM_183 ( ( XPMC_XPPU_BASEADDR ) + 0x000012DCUL ) #define XPMC_XPPU_APERPERM_183_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_183_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_183_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_183_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_183_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_183_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_183_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_183_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_183_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_183_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_183_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_183_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_183_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm184 */ #define XPMC_XPPU_APERPERM_184 ( ( XPMC_XPPU_BASEADDR ) + 0x000012E0UL ) #define XPMC_XPPU_APERPERM_184_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_184_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_184_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_184_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_184_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_184_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_184_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_184_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_184_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_184_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_184_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_184_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_184_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm185 */ #define XPMC_XPPU_APERPERM_185 ( ( XPMC_XPPU_BASEADDR ) + 0x000012E4UL ) #define XPMC_XPPU_APERPERM_185_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_185_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_185_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_185_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_185_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_185_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_185_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_185_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_185_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_185_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_185_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_185_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_185_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm186 */ #define XPMC_XPPU_APERPERM_186 ( ( XPMC_XPPU_BASEADDR ) + 0x000012E8UL ) #define XPMC_XPPU_APERPERM_186_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_186_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_186_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_186_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_186_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_186_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_186_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_186_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_186_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_186_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_186_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_186_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_186_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm187 */ #define XPMC_XPPU_APERPERM_187 ( ( XPMC_XPPU_BASEADDR ) + 0x000012ECUL ) #define XPMC_XPPU_APERPERM_187_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_187_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_187_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_187_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_187_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_187_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_187_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_187_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_187_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_187_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_187_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_187_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_187_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm188 */ #define XPMC_XPPU_APERPERM_188 ( ( XPMC_XPPU_BASEADDR ) + 0x000012F0UL ) #define XPMC_XPPU_APERPERM_188_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_188_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_188_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_188_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_188_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_188_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_188_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_188_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_188_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_188_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_188_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_188_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_188_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm189 */ #define XPMC_XPPU_APERPERM_189 ( ( XPMC_XPPU_BASEADDR ) + 0x000012F4UL ) #define XPMC_XPPU_APERPERM_189_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_189_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_189_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_189_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_189_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_189_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_189_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_189_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_189_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_189_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_189_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_189_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_189_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm190 */ #define XPMC_XPPU_APERPERM_190 ( ( XPMC_XPPU_BASEADDR ) + 0x000012F8UL ) #define XPMC_XPPU_APERPERM_190_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_190_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_190_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_190_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_190_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_190_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_190_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_190_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_190_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_190_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_190_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_190_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_190_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm191 */ #define XPMC_XPPU_APERPERM_191 ( ( XPMC_XPPU_BASEADDR ) + 0x000012FCUL ) #define XPMC_XPPU_APERPERM_191_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_191_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_191_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_191_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_191_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_191_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_191_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_191_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_191_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_191_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_191_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_191_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_191_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm192 */ #define XPMC_XPPU_APERPERM_192 ( ( XPMC_XPPU_BASEADDR ) + 0x00001300UL ) #define XPMC_XPPU_APERPERM_192_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_192_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_192_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_192_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_192_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_192_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_192_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_192_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_192_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_192_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_192_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_192_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_192_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm193 */ #define XPMC_XPPU_APERPERM_193 ( ( XPMC_XPPU_BASEADDR ) + 0x00001304UL ) #define XPMC_XPPU_APERPERM_193_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_193_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_193_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_193_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_193_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_193_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_193_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_193_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_193_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_193_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_193_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_193_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_193_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm194 */ #define XPMC_XPPU_APERPERM_194 ( ( XPMC_XPPU_BASEADDR ) + 0x00001308UL ) #define XPMC_XPPU_APERPERM_194_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_194_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_194_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_194_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_194_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_194_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_194_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_194_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_194_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_194_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_194_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_194_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_194_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm195 */ #define XPMC_XPPU_APERPERM_195 ( ( XPMC_XPPU_BASEADDR ) + 0x0000130CUL ) #define XPMC_XPPU_APERPERM_195_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_195_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_195_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_195_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_195_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_195_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_195_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_195_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_195_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_195_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_195_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_195_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_195_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm196 */ #define XPMC_XPPU_APERPERM_196 ( ( XPMC_XPPU_BASEADDR ) + 0x00001310UL ) #define XPMC_XPPU_APERPERM_196_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_196_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_196_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_196_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_196_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_196_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_196_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_196_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_196_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_196_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_196_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_196_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_196_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm197 */ #define XPMC_XPPU_APERPERM_197 ( ( XPMC_XPPU_BASEADDR ) + 0x00001314UL ) #define XPMC_XPPU_APERPERM_197_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_197_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_197_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_197_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_197_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_197_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_197_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_197_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_197_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_197_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_197_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_197_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_197_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm198 */ #define XPMC_XPPU_APERPERM_198 ( ( XPMC_XPPU_BASEADDR ) + 0x00001318UL ) #define XPMC_XPPU_APERPERM_198_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_198_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_198_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_198_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_198_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_198_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_198_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_198_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_198_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_198_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_198_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_198_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_198_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm199 */ #define XPMC_XPPU_APERPERM_199 ( ( XPMC_XPPU_BASEADDR ) + 0x0000131CUL ) #define XPMC_XPPU_APERPERM_199_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_199_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_199_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_199_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_199_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_199_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_199_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_199_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_199_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_199_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_199_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_199_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_199_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm200 */ #define XPMC_XPPU_APERPERM_200 ( ( XPMC_XPPU_BASEADDR ) + 0x00001320UL ) #define XPMC_XPPU_APERPERM_200_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_200_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_200_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_200_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_200_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_200_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_200_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_200_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_200_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_200_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_200_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_200_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_200_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm201 */ #define XPMC_XPPU_APERPERM_201 ( ( XPMC_XPPU_BASEADDR ) + 0x00001324UL ) #define XPMC_XPPU_APERPERM_201_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_201_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_201_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_201_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_201_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_201_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_201_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_201_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_201_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_201_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_201_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_201_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_201_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm202 */ #define XPMC_XPPU_APERPERM_202 ( ( XPMC_XPPU_BASEADDR ) + 0x00001328UL ) #define XPMC_XPPU_APERPERM_202_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_202_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_202_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_202_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_202_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_202_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_202_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_202_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_202_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_202_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_202_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_202_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_202_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm203 */ #define XPMC_XPPU_APERPERM_203 ( ( XPMC_XPPU_BASEADDR ) + 0x0000132CUL ) #define XPMC_XPPU_APERPERM_203_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_203_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_203_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_203_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_203_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_203_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_203_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_203_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_203_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_203_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_203_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_203_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_203_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm204 */ #define XPMC_XPPU_APERPERM_204 ( ( XPMC_XPPU_BASEADDR ) + 0x00001330UL ) #define XPMC_XPPU_APERPERM_204_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_204_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_204_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_204_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_204_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_204_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_204_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_204_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_204_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_204_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_204_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_204_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_204_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm205 */ #define XPMC_XPPU_APERPERM_205 ( ( XPMC_XPPU_BASEADDR ) + 0x00001334UL ) #define XPMC_XPPU_APERPERM_205_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_205_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_205_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_205_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_205_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_205_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_205_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_205_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_205_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_205_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_205_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_205_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_205_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm206 */ #define XPMC_XPPU_APERPERM_206 ( ( XPMC_XPPU_BASEADDR ) + 0x00001338UL ) #define XPMC_XPPU_APERPERM_206_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_206_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_206_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_206_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_206_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_206_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_206_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_206_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_206_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_206_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_206_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_206_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_206_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm207 */ #define XPMC_XPPU_APERPERM_207 ( ( XPMC_XPPU_BASEADDR ) + 0x0000133CUL ) #define XPMC_XPPU_APERPERM_207_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_207_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_207_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_207_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_207_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_207_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_207_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_207_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_207_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_207_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_207_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_207_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_207_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm208 */ #define XPMC_XPPU_APERPERM_208 ( ( XPMC_XPPU_BASEADDR ) + 0x00001340UL ) #define XPMC_XPPU_APERPERM_208_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_208_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_208_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_208_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_208_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_208_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_208_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_208_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_208_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_208_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_208_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_208_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_208_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm209 */ #define XPMC_XPPU_APERPERM_209 ( ( XPMC_XPPU_BASEADDR ) + 0x00001344UL ) #define XPMC_XPPU_APERPERM_209_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_209_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_209_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_209_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_209_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_209_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_209_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_209_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_209_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_209_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_209_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_209_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_209_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm210 */ #define XPMC_XPPU_APERPERM_210 ( ( XPMC_XPPU_BASEADDR ) + 0x00001348UL ) #define XPMC_XPPU_APERPERM_210_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_210_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_210_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_210_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_210_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_210_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_210_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_210_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_210_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_210_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_210_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_210_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_210_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm211 */ #define XPMC_XPPU_APERPERM_211 ( ( XPMC_XPPU_BASEADDR ) + 0x0000134CUL ) #define XPMC_XPPU_APERPERM_211_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_211_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_211_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_211_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_211_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_211_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_211_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_211_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_211_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_211_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_211_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_211_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_211_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm212 */ #define XPMC_XPPU_APERPERM_212 ( ( XPMC_XPPU_BASEADDR ) + 0x00001350UL ) #define XPMC_XPPU_APERPERM_212_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_212_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_212_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_212_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_212_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_212_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_212_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_212_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_212_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_212_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_212_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_212_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_212_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm213 */ #define XPMC_XPPU_APERPERM_213 ( ( XPMC_XPPU_BASEADDR ) + 0x00001354UL ) #define XPMC_XPPU_APERPERM_213_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_213_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_213_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_213_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_213_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_213_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_213_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_213_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_213_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_213_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_213_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_213_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_213_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm214 */ #define XPMC_XPPU_APERPERM_214 ( ( XPMC_XPPU_BASEADDR ) + 0x00001358UL ) #define XPMC_XPPU_APERPERM_214_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_214_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_214_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_214_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_214_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_214_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_214_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_214_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_214_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_214_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_214_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_214_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_214_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm215 */ #define XPMC_XPPU_APERPERM_215 ( ( XPMC_XPPU_BASEADDR ) + 0x0000135CUL ) #define XPMC_XPPU_APERPERM_215_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_215_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_215_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_215_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_215_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_215_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_215_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_215_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_215_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_215_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_215_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_215_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_215_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm216 */ #define XPMC_XPPU_APERPERM_216 ( ( XPMC_XPPU_BASEADDR ) + 0x00001360UL ) #define XPMC_XPPU_APERPERM_216_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_216_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_216_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_216_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_216_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_216_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_216_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_216_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_216_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_216_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_216_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_216_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_216_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm217 */ #define XPMC_XPPU_APERPERM_217 ( ( XPMC_XPPU_BASEADDR ) + 0x00001364UL ) #define XPMC_XPPU_APERPERM_217_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_217_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_217_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_217_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_217_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_217_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_217_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_217_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_217_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_217_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_217_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_217_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_217_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm218 */ #define XPMC_XPPU_APERPERM_218 ( ( XPMC_XPPU_BASEADDR ) + 0x00001368UL ) #define XPMC_XPPU_APERPERM_218_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_218_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_218_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_218_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_218_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_218_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_218_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_218_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_218_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_218_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_218_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_218_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_218_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm219 */ #define XPMC_XPPU_APERPERM_219 ( ( XPMC_XPPU_BASEADDR ) + 0x0000136CUL ) #define XPMC_XPPU_APERPERM_219_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_219_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_219_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_219_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_219_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_219_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_219_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_219_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_219_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_219_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_219_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_219_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_219_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm220 */ #define XPMC_XPPU_APERPERM_220 ( ( XPMC_XPPU_BASEADDR ) + 0x00001370UL ) #define XPMC_XPPU_APERPERM_220_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_220_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_220_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_220_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_220_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_220_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_220_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_220_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_220_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_220_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_220_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_220_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_220_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm221 */ #define XPMC_XPPU_APERPERM_221 ( ( XPMC_XPPU_BASEADDR ) + 0x00001374UL ) #define XPMC_XPPU_APERPERM_221_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_221_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_221_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_221_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_221_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_221_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_221_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_221_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_221_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_221_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_221_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_221_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_221_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm222 */ #define XPMC_XPPU_APERPERM_222 ( ( XPMC_XPPU_BASEADDR ) + 0x00001378UL ) #define XPMC_XPPU_APERPERM_222_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_222_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_222_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_222_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_222_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_222_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_222_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_222_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_222_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_222_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_222_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_222_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_222_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm223 */ #define XPMC_XPPU_APERPERM_223 ( ( XPMC_XPPU_BASEADDR ) + 0x0000137CUL ) #define XPMC_XPPU_APERPERM_223_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_223_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_223_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_223_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_223_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_223_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_223_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_223_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_223_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_223_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_223_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_223_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_223_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm224 */ #define XPMC_XPPU_APERPERM_224 ( ( XPMC_XPPU_BASEADDR ) + 0x00001380UL ) #define XPMC_XPPU_APERPERM_224_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_224_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_224_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_224_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_224_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_224_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_224_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_224_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_224_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_224_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_224_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_224_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_224_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm225 */ #define XPMC_XPPU_APERPERM_225 ( ( XPMC_XPPU_BASEADDR ) + 0x00001384UL ) #define XPMC_XPPU_APERPERM_225_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_225_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_225_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_225_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_225_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_225_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_225_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_225_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_225_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_225_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_225_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_225_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_225_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm226 */ #define XPMC_XPPU_APERPERM_226 ( ( XPMC_XPPU_BASEADDR ) + 0x00001388UL ) #define XPMC_XPPU_APERPERM_226_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_226_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_226_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_226_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_226_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_226_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_226_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_226_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_226_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_226_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_226_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_226_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_226_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm227 */ #define XPMC_XPPU_APERPERM_227 ( ( XPMC_XPPU_BASEADDR ) + 0x0000138CUL ) #define XPMC_XPPU_APERPERM_227_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_227_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_227_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_227_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_227_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_227_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_227_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_227_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_227_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_227_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_227_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_227_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_227_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm228 */ #define XPMC_XPPU_APERPERM_228 ( ( XPMC_XPPU_BASEADDR ) + 0x00001390UL ) #define XPMC_XPPU_APERPERM_228_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_228_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_228_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_228_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_228_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_228_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_228_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_228_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_228_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_228_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_228_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_228_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_228_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm229 */ #define XPMC_XPPU_APERPERM_229 ( ( XPMC_XPPU_BASEADDR ) + 0x00001394UL ) #define XPMC_XPPU_APERPERM_229_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_229_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_229_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_229_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_229_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_229_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_229_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_229_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_229_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_229_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_229_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_229_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_229_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm230 */ #define XPMC_XPPU_APERPERM_230 ( ( XPMC_XPPU_BASEADDR ) + 0x00001398UL ) #define XPMC_XPPU_APERPERM_230_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_230_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_230_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_230_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_230_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_230_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_230_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_230_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_230_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_230_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_230_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_230_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_230_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm231 */ #define XPMC_XPPU_APERPERM_231 ( ( XPMC_XPPU_BASEADDR ) + 0x0000139CUL ) #define XPMC_XPPU_APERPERM_231_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_231_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_231_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_231_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_231_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_231_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_231_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_231_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_231_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_231_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_231_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_231_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_231_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm232 */ #define XPMC_XPPU_APERPERM_232 ( ( XPMC_XPPU_BASEADDR ) + 0x000013A0UL ) #define XPMC_XPPU_APERPERM_232_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_232_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_232_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_232_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_232_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_232_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_232_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_232_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_232_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_232_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_232_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_232_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_232_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm233 */ #define XPMC_XPPU_APERPERM_233 ( ( XPMC_XPPU_BASEADDR ) + 0x000013A4UL ) #define XPMC_XPPU_APERPERM_233_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_233_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_233_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_233_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_233_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_233_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_233_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_233_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_233_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_233_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_233_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_233_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_233_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm234 */ #define XPMC_XPPU_APERPERM_234 ( ( XPMC_XPPU_BASEADDR ) + 0x000013A8UL ) #define XPMC_XPPU_APERPERM_234_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_234_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_234_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_234_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_234_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_234_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_234_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_234_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_234_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_234_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_234_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_234_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_234_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm235 */ #define XPMC_XPPU_APERPERM_235 ( ( XPMC_XPPU_BASEADDR ) + 0x000013ACUL ) #define XPMC_XPPU_APERPERM_235_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_235_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_235_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_235_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_235_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_235_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_235_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_235_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_235_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_235_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_235_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_235_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_235_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm236 */ #define XPMC_XPPU_APERPERM_236 ( ( XPMC_XPPU_BASEADDR ) + 0x000013B0UL ) #define XPMC_XPPU_APERPERM_236_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_236_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_236_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_236_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_236_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_236_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_236_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_236_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_236_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_236_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_236_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_236_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_236_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm237 */ #define XPMC_XPPU_APERPERM_237 ( ( XPMC_XPPU_BASEADDR ) + 0x000013B4UL ) #define XPMC_XPPU_APERPERM_237_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_237_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_237_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_237_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_237_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_237_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_237_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_237_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_237_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_237_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_237_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_237_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_237_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm238 */ #define XPMC_XPPU_APERPERM_238 ( ( XPMC_XPPU_BASEADDR ) + 0x000013B8UL ) #define XPMC_XPPU_APERPERM_238_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_238_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_238_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_238_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_238_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_238_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_238_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_238_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_238_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_238_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_238_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_238_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_238_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm239 */ #define XPMC_XPPU_APERPERM_239 ( ( XPMC_XPPU_BASEADDR ) + 0x000013BCUL ) #define XPMC_XPPU_APERPERM_239_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_239_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_239_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_239_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_239_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_239_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_239_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_239_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_239_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_239_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_239_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_239_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_239_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm240 */ #define XPMC_XPPU_APERPERM_240 ( ( XPMC_XPPU_BASEADDR ) + 0x000013C0UL ) #define XPMC_XPPU_APERPERM_240_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_240_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_240_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_240_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_240_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_240_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_240_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_240_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_240_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_240_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_240_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_240_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_240_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm241 */ #define XPMC_XPPU_APERPERM_241 ( ( XPMC_XPPU_BASEADDR ) + 0x000013C4UL ) #define XPMC_XPPU_APERPERM_241_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_241_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_241_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_241_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_241_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_241_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_241_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_241_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_241_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_241_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_241_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_241_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_241_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm242 */ #define XPMC_XPPU_APERPERM_242 ( ( XPMC_XPPU_BASEADDR ) + 0x000013C8UL ) #define XPMC_XPPU_APERPERM_242_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_242_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_242_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_242_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_242_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_242_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_242_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_242_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_242_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_242_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_242_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_242_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_242_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm243 */ #define XPMC_XPPU_APERPERM_243 ( ( XPMC_XPPU_BASEADDR ) + 0x000013CCUL ) #define XPMC_XPPU_APERPERM_243_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_243_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_243_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_243_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_243_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_243_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_243_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_243_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_243_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_243_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_243_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_243_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_243_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm244 */ #define XPMC_XPPU_APERPERM_244 ( ( XPMC_XPPU_BASEADDR ) + 0x000013D0UL ) #define XPMC_XPPU_APERPERM_244_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_244_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_244_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_244_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_244_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_244_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_244_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_244_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_244_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_244_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_244_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_244_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_244_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm245 */ #define XPMC_XPPU_APERPERM_245 ( ( XPMC_XPPU_BASEADDR ) + 0x000013D4UL ) #define XPMC_XPPU_APERPERM_245_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_245_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_245_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_245_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_245_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_245_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_245_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_245_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_245_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_245_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_245_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_245_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_245_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm246 */ #define XPMC_XPPU_APERPERM_246 ( ( XPMC_XPPU_BASEADDR ) + 0x000013D8UL ) #define XPMC_XPPU_APERPERM_246_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_246_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_246_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_246_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_246_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_246_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_246_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_246_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_246_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_246_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_246_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_246_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_246_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm247 */ #define XPMC_XPPU_APERPERM_247 ( ( XPMC_XPPU_BASEADDR ) + 0x000013DCUL ) #define XPMC_XPPU_APERPERM_247_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_247_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_247_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_247_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_247_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_247_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_247_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_247_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_247_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_247_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_247_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_247_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_247_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm248 */ #define XPMC_XPPU_APERPERM_248 ( ( XPMC_XPPU_BASEADDR ) + 0x000013E0UL ) #define XPMC_XPPU_APERPERM_248_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_248_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_248_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_248_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_248_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_248_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_248_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_248_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_248_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_248_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_248_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_248_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_248_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm249 */ #define XPMC_XPPU_APERPERM_249 ( ( XPMC_XPPU_BASEADDR ) + 0x000013E4UL ) #define XPMC_XPPU_APERPERM_249_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_249_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_249_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_249_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_249_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_249_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_249_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_249_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_249_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_249_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_249_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_249_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_249_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm250 */ #define XPMC_XPPU_APERPERM_250 ( ( XPMC_XPPU_BASEADDR ) + 0x000013E8UL ) #define XPMC_XPPU_APERPERM_250_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_250_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_250_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_250_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_250_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_250_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_250_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_250_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_250_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_250_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_250_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_250_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_250_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm251 */ #define XPMC_XPPU_APERPERM_251 ( ( XPMC_XPPU_BASEADDR ) + 0x000013ECUL ) #define XPMC_XPPU_APERPERM_251_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_251_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_251_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_251_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_251_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_251_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_251_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_251_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_251_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_251_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_251_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_251_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_251_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm252 */ #define XPMC_XPPU_APERPERM_252 ( ( XPMC_XPPU_BASEADDR ) + 0x000013F0UL ) #define XPMC_XPPU_APERPERM_252_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_252_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_252_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_252_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_252_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_252_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_252_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_252_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_252_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_252_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_252_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_252_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_252_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm253 */ #define XPMC_XPPU_APERPERM_253 ( ( XPMC_XPPU_BASEADDR ) + 0x000013F4UL ) #define XPMC_XPPU_APERPERM_253_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_253_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_253_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_253_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_253_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_253_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_253_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_253_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_253_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_253_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_253_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_253_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_253_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm254 */ #define XPMC_XPPU_APERPERM_254 ( ( XPMC_XPPU_BASEADDR ) + 0x000013F8UL ) #define XPMC_XPPU_APERPERM_254_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_254_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_254_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_254_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_254_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_254_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_254_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_254_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_254_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_254_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_254_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_254_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_254_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm255 */ #define XPMC_XPPU_APERPERM_255 ( ( XPMC_XPPU_BASEADDR ) + 0x000013FCUL ) #define XPMC_XPPU_APERPERM_255_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_255_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_255_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_255_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_255_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_255_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_255_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_255_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_255_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_255_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_255_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_255_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_255_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm384 */ #define XPMC_XPPU_APERPERM_384 ( ( XPMC_XPPU_BASEADDR ) + 0x00001600UL ) #define XPMC_XPPU_APERPERM_384_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_384_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_384_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_384_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_384_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_384_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_384_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_384_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_384_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_384_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_384_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_384_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_384_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm385 */ #define XPMC_XPPU_APERPERM_385 ( ( XPMC_XPPU_BASEADDR ) + 0x00001604UL ) #define XPMC_XPPU_APERPERM_385_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_385_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_385_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_385_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_385_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_385_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_385_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_385_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_385_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_385_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_385_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_385_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_385_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm386 */ #define XPMC_XPPU_APERPERM_386 ( ( XPMC_XPPU_BASEADDR ) + 0x00001608UL ) #define XPMC_XPPU_APERPERM_386_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_386_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_386_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_386_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_386_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_386_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_386_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_386_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_386_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_386_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_386_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_386_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_386_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm387 */ #define XPMC_XPPU_APERPERM_387 ( ( XPMC_XPPU_BASEADDR ) + 0x0000160CUL ) #define XPMC_XPPU_APERPERM_387_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_387_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_387_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_387_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_387_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_387_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_387_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_387_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_387_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_387_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_387_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_387_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_387_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm388 */ #define XPMC_XPPU_APERPERM_388 ( ( XPMC_XPPU_BASEADDR ) + 0x00001610UL ) #define XPMC_XPPU_APERPERM_388_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_388_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_388_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_388_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_388_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_388_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_388_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_388_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_388_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_388_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_388_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_388_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_388_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm389 */ #define XPMC_XPPU_APERPERM_389 ( ( XPMC_XPPU_BASEADDR ) + 0x00001614UL ) #define XPMC_XPPU_APERPERM_389_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_389_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_389_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_389_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_389_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_389_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_389_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_389_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_389_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_389_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_389_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_389_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_389_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm390 */ #define XPMC_XPPU_APERPERM_390 ( ( XPMC_XPPU_BASEADDR ) + 0x00001618UL ) #define XPMC_XPPU_APERPERM_390_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_390_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_390_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_390_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_390_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_390_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_390_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_390_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_390_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_390_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_390_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_390_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_390_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm391 */ #define XPMC_XPPU_APERPERM_391 ( ( XPMC_XPPU_BASEADDR ) + 0x0000161CUL ) #define XPMC_XPPU_APERPERM_391_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_391_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_391_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_391_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_391_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_391_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_391_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_391_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_391_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_391_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_391_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_391_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_391_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm392 */ #define XPMC_XPPU_APERPERM_392 ( ( XPMC_XPPU_BASEADDR ) + 0x00001620UL ) #define XPMC_XPPU_APERPERM_392_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_392_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_392_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_392_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_392_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_392_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_392_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_392_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_392_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_392_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_392_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_392_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_392_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm393 */ #define XPMC_XPPU_APERPERM_393 ( ( XPMC_XPPU_BASEADDR ) + 0x00001624UL ) #define XPMC_XPPU_APERPERM_393_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_393_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_393_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_393_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_393_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_393_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_393_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_393_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_393_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_393_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_393_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_393_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_393_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm394 */ #define XPMC_XPPU_APERPERM_394 ( ( XPMC_XPPU_BASEADDR ) + 0x00001628UL ) #define XPMC_XPPU_APERPERM_394_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_394_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_394_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_394_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_394_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_394_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_394_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_394_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_394_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_394_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_394_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_394_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_394_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm395 */ #define XPMC_XPPU_APERPERM_395 ( ( XPMC_XPPU_BASEADDR ) + 0x0000162CUL ) #define XPMC_XPPU_APERPERM_395_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_395_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_395_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_395_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_395_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_395_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_395_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_395_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_395_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_395_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_395_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_395_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_395_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm396 */ #define XPMC_XPPU_APERPERM_396 ( ( XPMC_XPPU_BASEADDR ) + 0x00001630UL ) #define XPMC_XPPU_APERPERM_396_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_396_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_396_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_396_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_396_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_396_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_396_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_396_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_396_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_396_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_396_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_396_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_396_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm397 */ #define XPMC_XPPU_APERPERM_397 ( ( XPMC_XPPU_BASEADDR ) + 0x00001634UL ) #define XPMC_XPPU_APERPERM_397_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_397_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_397_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_397_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_397_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_397_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_397_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_397_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_397_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_397_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_397_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_397_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_397_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm398 */ #define XPMC_XPPU_APERPERM_398 ( ( XPMC_XPPU_BASEADDR ) + 0x00001638UL ) #define XPMC_XPPU_APERPERM_398_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_398_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_398_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_398_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_398_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_398_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_398_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_398_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_398_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_398_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_398_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_398_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_398_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm399 */ #define XPMC_XPPU_APERPERM_399 ( ( XPMC_XPPU_BASEADDR ) + 0x0000163CUL ) #define XPMC_XPPU_APERPERM_399_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_399_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_399_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_399_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_399_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_399_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_399_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_399_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_399_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_399_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_399_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_399_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_399_PERMISSION_DEFVAL 0x0UL /** * Register: XpmcXppuAperperm400 */ #define XPMC_XPPU_APERPERM_400 ( ( XPMC_XPPU_BASEADDR ) + 0x00001640UL ) #define XPMC_XPPU_APERPERM_400_RSTVAL 0x00000000UL #define XPMC_XPPU_APERPERM_400_PARITY_SHIFT 28UL #define XPMC_XPPU_APERPERM_400_PARITY_WIDTH 4UL #define XPMC_XPPU_APERPERM_400_PARITY_MASK 0xf0000000UL #define XPMC_XPPU_APERPERM_400_PARITY_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_400_TRUSTZONE_SHIFT 27UL #define XPMC_XPPU_APERPERM_400_TRUSTZONE_WIDTH 1UL #define XPMC_XPPU_APERPERM_400_TRUSTZONE_MASK 0x08000000UL #define XPMC_XPPU_APERPERM_400_TRUSTZONE_DEFVAL 0x0UL #define XPMC_XPPU_APERPERM_400_PERMISSION_SHIFT 0UL #define XPMC_XPPU_APERPERM_400_PERMISSION_WIDTH 20UL #define XPMC_XPPU_APERPERM_400_PERMISSION_MASK 0x000fffffUL #define XPMC_XPPU_APERPERM_400_PERMISSION_DEFVAL 0x0UL #ifdef __cplusplus } #endif #endif /* __XPMC_XPPU_H__ */

d43093f4ee8cc62a84bdb544b89faa2d3779ff1a

80999df7d43a7521609338975a904113776a8c4f

/libs/libmme/MmpDecoder/cnm-coda960-ref_sw_pkg-v3.3.0/vpuapi/vpuapifunc.h

f86d463d1ac823b4501d7e94ad65b52f378f6637

no_license

tifler/gdm-test-platform

30b766552049ef910ee0ac57ca7adee28087d26f

e24b897429fea8fae8cad7391f523a4f0451f4e7

refs/heads/master

UTF-8

C

h

//--=========================================================================-- // This file is a part of VPU Reference API project //----------------------------------------------------------------------------- // // This confidential and proprietary software may be used only // as authorized by a licensing agreement from Chips&Media Inc. // In the event of publication, the following notice is applicable: // // (C) COPYRIGHT 2006 - 2011 CHIPS&MEDIA INC. // ALL RIGHTS RESERVED // // The entire notice above must be reproduced on all authorized // copies. // //--=========================================================================-- #ifndef VPUAPI_UTIL_H_INCLUDED #define VPUAPI_UTIL_H_INCLUDED #include "vpuapi.h" #include "regdefine.h" // COD_STD enum { AVC_DEC = 0, VC1_DEC = 1, MP2_DEC = 2, MP4_DEC = 3, DV3_DEC = 3, RV_DEC = 4, AVS_DEC = 5, VPX_DEC = 7, AVC_ENC = 8, MP4_ENC = 11 }; // AUX_COD_STD enum { MP4_AUX_MPEG4 = 0, MP4_AUX_DIVX3 = 1 }; enum { VPX_AUX_THO = 0, VPX_AUX_VP6 = 1, VPX_AUX_VP8 = 2 }; enum { AVC_AUX_AVC = 0, AVC_AUX_MVC = 1 }; // BIT_RUN command enum { SEQ_INIT = 1, SEQ_END = 2, PIC_RUN = 3, SET_FRAME_BUF = 4, ENCODE_HEADER = 5, ENC_PARA_SET = 6, DEC_RENEW = 6, DEC_PARA_SET = 7, DEC_BUF_FLUSH = 8, RC_CHANGE_PARAMETER = 9, VPU_SLEEP = 10, VPU_WAKE = 11, ENC_ROI_INIT = 12, FIRMWARE_GET = 0xf }; #define MAX_GDI_IDX 31 #define MAX_REG_FRAME MAX_GDI_IDX*2 //2 for WTL // SW Reset command #define VPU_SW_RESET_BPU_CORE 0x008 #define VPU_SW_RESET_BPU_BUS 0x010 #define VPU_SW_RESET_VCE_CORE 0x020 #define VPU_SW_RESET_VCE_BUS 0x040 #define VPU_SW_RESET_GDI_CORE 0x080 #define VPU_SW_RESET_GDI_BUS 0x100 typedef struct { int useBitEnable; int useIpEnable; int useDbkYEnable; int useDbkCEnable; int useOvlEnable; int useBtpEnable; PhysicalAddress bufBitUse; PhysicalAddress bufIpAcDcUse; PhysicalAddress bufDbkYUse; PhysicalAddress bufDbkCUse; PhysicalAddress bufOvlUse; PhysicalAddress bufBtpUse; int bufSize; } SecAxiInfo; typedef struct { DecOpenParam openParam; DecInitialInfo initialInfo; PhysicalAddress streamWrPtr; PhysicalAddress streamRdPtr; int streamEndflag; int frameDisplayFlag; int clearDisplayIndexes; int setDisplayIndexes; PhysicalAddress streamRdPtrRegAddr; PhysicalAddress streamWrPtrRegAddr; PhysicalAddress streamBufStartAddr; PhysicalAddress streamBufEndAddr; PhysicalAddress frameDisplayFlagRegAddr; int streamBufSize; FrameBuffer frameBufPool[MAX_REG_FRAME]; vpu_buffer_t vbFrame; //1 for decoder frame buffer, 1 for WTL, 2 PPU vpu_buffer_t vbWTL; vpu_buffer_t vbPPU; vpu_buffer_t vbMV; int frameAllocExt; int ppuAllocExt; int numFrameBuffers; int stride; int frameBufferHeight; int rotationEnable; int mirrorEnable; int deringEnable; MirrorDirection mirrorDirection; int rotationAngle; FrameBuffer rotatorOutput; int rotatorStride; int rotatorOutputValid; int initialInfoObtained; int vc1BframeDisplayValid; int mapType; int tiled2LinearEnable; int wtlEnable; // coda980 only SecAxiInfo secAxiInfo; MaverickCacheConfig cacheConfig; int chunkSize; int seqInitEscape; // Report Information PhysicalAddress userDataBufAddr; vpu_buffer_t vbUserData; int userDataEnable; // User Data int userDataBufSize; int userDataReportMode; // User Data report mode (0 : interrupt mode, 1 interrupt disable mode) #ifdef SUPPORT_MEM_PROTECT WriteMemProtectCfg writeMemProtectCfg; #endif LowDelayInfo lowDelayInfo; int frameStartPos; int frameEndPos; int frameDelay; vpu_buffer_t vbSlice; // AVC, VP8 only vpu_buffer_t vbWork; DecOutputInfo decOutInfo[MAX_GDI_IDX]; TiledMapConfig mapCfg; int reorderEnable; int skipReorderEnable; int reOrderQueueNum; int reOrderQueue[MAX_GDI_IDX]; AVCErrorConcealMode avcErrorConcealMode; DRAMConfig dramCfg; int thumbnailMode; int frameBufDelay; } DecInfo; typedef struct { EncOpenParam openParam; EncInitialInfo initialInfo; PhysicalAddress streamRdPtr; PhysicalAddress streamWrPtr; int streamEndflag; PhysicalAddress streamRdPtrRegAddr; PhysicalAddress streamWrPtrRegAddr; PhysicalAddress streamBufStartAddr; PhysicalAddress streamBufEndAddr; int streamBufSize; int linear2TiledEnable; int mapType; int userMapEnable; FrameBuffer frameBufPool[MAX_REG_FRAME]; vpu_buffer_t vbFrame; vpu_buffer_t vbPPU; int frameAllocExt; int ppuAllocExt; vpu_buffer_t vbSubSampFrame; int numFrameBuffers; int stride; int frameBufferHeight; int rotationEnable; int mirrorEnable; MirrorDirection mirrorDirection; int rotationAngle; int initialInfoObtained; int ringBufferEnable; SecAxiInfo secAxiInfo; MaverickCacheConfig cacheConfig; #ifdef SUPPORT_MEM_PROTECT WriteMemProtectCfg writeMemProtectCfg; #endif int lineBufIntEn; vpu_buffer_t vbWork; vpu_buffer_t vbScratch; TiledMapConfig mapCfg; DRAMConfig dramCfg; } EncInfo; typedef struct CodecInst { int inUse; // DO NOT modify line of inUse variable it must be first line of CodecInst structure int instIndex; int coreIdx; int codecMode; int codecModeAux; int loggingEnable; union { EncInfo encInfo; DecInfo decInfo; } CodecInfo; } CodecInst; #ifdef __cplusplus extern "C" { #endif RetCode BitLoadFirmware(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize); RetCode BitLoadFirmwareCodewrite(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize); void BitIssueCommand(Uint32 coreIdx, CodecInst *inst, int cmd); RetCode InitCodecInstancePool(Uint32 coreIdx); RetCode GetCodecInstance(Uint32 coreIdx, CodecInst ** ppInst); void FreeCodecInstance(CodecInst * pCodecInst); RetCode CheckInstanceValidity(CodecInst * pci); RetCode CheckDecInstanceValidity(DecHandle handle); RetCode CheckDecOpenParam(DecOpenParam * pop); int DecBitstreamBufEmpty(DecInfo * pDecInfo); RetCode SetParaSet(DecHandle handle, int paraSetType, DecParamSet * para); void DecSetHostParaAddr(Uint32 coreIdx, PhysicalAddress baseAddr, PhysicalAddress paraAddr); #ifdef SUPPORT_MEM_PROTECT int SetDecWriteProtectRegions(CodecInst *inst); void ConfigDecWPROTRegion(int coreIdx, DecInfo * pDecInfo); int SetEncWriteProtectRegions(CodecInst *inst); void ConfigEncWPROTRegion(int coreIdx, EncInfo * pEncInfo, WriteMemProtectCfg *pCgf); #endif int ConfigSecAXI(Uint32 coreIdx, CodStd codStd, SecAxiInfo *sa, int width, int height, int profile); RetCode AllocateFrameBufferArray(int coreIdx, FrameBuffer *frambufArray, vpu_buffer_t *pvbFrame, int mapType, int interleave, int framebufFormat, int num, int stride, int memHeight, int gdiIndex, int fbType, PhysicalAddress tiledBaseAddr, DRAMConfig *pDramCfg); RetCode CheckEncInstanceValidity(EncHandle handle); RetCode CheckEncOpenParam(EncOpenParam * pop); RetCode CheckEncParam(EncHandle handle, EncParam * param); RetCode GetEncHeader(EncHandle handle, EncHeaderParam * encHeaderParam); RetCode EncParaSet(EncHandle handle, int paraSetType); RetCode SetGopNumber(EncHandle handle, Uint32 *gopNumber); RetCode SetIntraQp(EncHandle handle, Uint32 *intraQp); RetCode SetBitrate(EncHandle handle, Uint32 *bitrate); RetCode SetFramerate(EncHandle handle, Uint32 *frameRate); RetCode SetIntraRefreshNum(EncHandle handle, Uint32 *pIntraRefreshNum); RetCode SetSliceMode(EncHandle handle, EncSliceMode *pSliceMode); RetCode SetHecMode(EncHandle handle, int mode); void EncSetHostParaAddr(Uint32 coreIdx, PhysicalAddress baseAddr, PhysicalAddress paraAddr); RetCode EnterLock(Uint32 coreIdx); RetCode LeaveLock(Uint32 coreIdx); RetCode EnterDispFlagLock(Uint32 coreIdx); RetCode LeaveDispFlagLock(Uint32 coreIdx); RetCode SetClockGate(Uint32 coreIdx, Uint32 on); void SetPendingInst(Uint32 coreIdx, CodecInst *inst); void ClearPendingInst(Uint32 coreIdx); CodecInst *GetPendingInst(Uint32 coreIdx); int SetTiledMapType(Uint32 coreIdx, TiledMapConfig *pMapCfg, DRAMConfig *dramCfg, int stride, int mapType); void SetTiledFrameBase(Uint32 coreIdx, PhysicalAddress baseAddr); PhysicalAddress GetTiledFrameBase(Uint32 coreIdx, FrameBuffer *frame, int num); int GetXY2AXIAddr(TiledMapConfig *pMapCfg, int ycbcr, int posY, int posX, int stride, FrameBuffer *fb); int GetLowDelayOutput(CodecInst *pCodecInst, DecOutputInfo *lowDelayOutput); #ifdef __cplusplus } #endif #endif // endif VPUAPI_UTIL_H_INCLUDED

f1af247df1026c514d3ba3ab4f36ba5254287c68

c158769f03e30af5ae26f883ae9d968c9543bab4

/libunix/set-tty-8n1.c

7b92047796b76dcb83817384c338ab3b3c4a0de9

no_license

PaulWendt96/cs240lx-20spr

22d0e05e3ca142f33883c0d3e67e01a4fa9fe2c8

ac8a2602dd5d5ba14c99afd88b36f033cc9e407a

refs/heads/master

UTF-8

C

c

#include <assert.h> #include <fcntl.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include <sys/stat.h> #include <unistd.h> #include <termios.h> #include "demand.h" #include "libunix.h" // XXX: if anyone figures out a cleaner way to do this, lmk. I don't // have a mac, so stopped as soon as we had something that worked on // linux & macos. // params: // - <timeout> is in seconds (< 1 ok) // - <speed> is baud rate. int set_tty_to_8n1(int fd, unsigned speed, double timeout) { struct termios tty; memset(&tty, 0, sizeof tty); if (tcgetattr (fd, &tty) != 0) panic("tcgetattr failed\n"); memset (&tty, 0, sizeof tty); // https://github.com/rlcheng/raspberry_pi_workshop cfsetspeed(&tty, speed); // disable IGNBRK for mismatched speed tests; otherwise receive break // as \000 chars // XXX: wait, does this disable break or ignore-ignore break?? tty.c_iflag &= ~IGNBRK; // disable break processing tty.c_lflag = 0; // no signaling chars, no echo, // no canonical processing tty.c_oflag = 0; // no remapping, no delays tty.c_cc[VMIN] = 0; // read doesn't block assert(timeout < 100 && timeout > 0); // 0.1 seconds read timeout tty.c_cc[VTIME] = (int)timeout *80; // this seems to cause issues? /* * Setup TTY for 8n1 mode, used by the pi UART. */ // Disables the Parity Enable bit(PARENB),So No Parity tty.c_cflag &= ~PARENB; // CSTOPB = 2 Stop bits,here it is cleared so 1 Stop bit tty.c_cflag &= ~CSTOPB; // Clears the mask for setting the data size tty.c_cflag &= ~CSIZE; // Set the data bits = 8 tty.c_cflag |= CS8; // No Hardware flow Control tty.c_cflag &= ~CRTSCTS; // Enable receiver,Ignore Modem Control lines tty.c_cflag |= CREAD | CLOCAL; // Disable XON/XOFF flow control both i/p and o/p tty.c_iflag &= ~(IXON | IXOFF | IXANY); // Non Cannonical mode tty.c_iflag &= ~(ICANON | ECHO | ECHOE | ISIG); // No Output Processing tty.c_oflag &= ~OPOST; if(tcsetattr (fd, TCSANOW, &tty) != 0) panic("tcsetattr failed\n"); return fd; }

5386e8db6bffe7bbb2151ba9b99c7624b7b8fc9a

d986f63000c2ca721c06226ce31668f23134bca4

/tests/tests/Init/06-Add/06-02_Add_Variables.c

20e032cdb727bc23f2ad98c3d02d4641e1285fe2

no_license

Fabien-GELUS/PLD-COMP

c27642da609dba9484e50f7e005a81cf9649206b

09d5e5799b50cf124707d346af0a4a41f551e159

refs/heads/master

UTF-8

C

c

#include <inttypes.h> int main() { int a,b,c; a = 7; b = 42; c = 20; a = a+b+c; return a; }

d9e1bca18c93e555b2259252fb11e7d00b6acae3

7daefc9aaa205b3c239e02c8b6c961c627c58679

/0x02-functions_nested_loops/10-add.c

4077fba1d9161f1a19349314e655c4be48a6608f

no_license

nasserdr/c_common_tools

e797ff667a40bbf3dddaf1edfebbeea9b42ce156

f347838ecdf2d07f67d2209cbd10a5c91d573c4a

refs/heads/master

UTF-8

C

c

#include "holberton.h" /** * add - Adds 2 numbers * * @m1: input integer 1 * @m2: input integer 2 * * Return: m1 + m2 */ int add(int m1, int m2) { return (m1 + m2); }

668fad776351992d229a31841ce845fd04cf5a08

86ec9543b7b2ef3a5d1803cf17bddc492435d516

/src/openmp/vect.h

da5aebae5098b5930b6285f0df15b3b2f32d103c

no_license

KevinXuxuxu/grav

d87f55f976b518d30c4d36a3f95f706e363e7688

e3cbe5e473622565a2e785fd40f62dd4f2e617c6

refs/heads/master

UTF-8

C

h

// // vect.h // grav // // Created by XuFangzhou on 17/3/28. // Copyright © 2017年 XuFangzhou. All rights reserved. // #ifndef vect_h #define vect_h #include <cmath> #include <pmmintrin.h> struct Vect { Vect() {} Vect(float _x, float _y = 0.0, float _z = 0.0) :x(_x), y(_y), z(_z) {} union { struct { float x, y, z; }; // float c[3]; }; Vect operator +(Vect b) const { return Vect(x + b.x, y + b.y, z + b.z); } Vect operator +=(Vect b) { x += b.x; y += b.y; z += b.z; return *this; } Vect operator -(Vect b) const { return Vect(x - b.x, y - b.y, z - b.z); } Vect operator *(float k) const { return Vect(x * k, y * k, z * k); } friend Vect operator *(float k, Vect v) { return Vect(v.x * k, v.y * k, v.z * k); } Vect operator /(float k) const { return Vect(x / k, y / k, z / k); } float operator &(Vect b) const { return x * b.x + y * b.y + z * b.z; } float abs() const { return sqrt(x * x + y * y + z * z); } Vect unit() const { return *this / abs(); } }; //float dotProduct(Vect a, Vect b) //{ // return a.x * b.x + a.y * b.y + a.z * b.z; //} #endif /* vect_h */

4e84ff1df245d2f5873296d106cff351e863f92a

64ff1ed19376504536817f3d5034b6757f03c537

/clicks/eink290inch/example/main.c

2e7cf12d90d25a7563d98106625dcb40da64e4e4

no_license

KWest-WRD/mikrosdk_click_v2

69efc8eaa8de5990a5aad78ebae5bfd3b9c0d20f

9c97d8ed79fc6ddf690e4b911de149aea3d5eebf

refs/heads/master

UTF-8

C

c

/*! * \file * \brief Eink290Inch Click example * * # Description * This application write a text and draw an image on eINK display. * * The demo application is composed of two sections : * * ## Application Init * Driver initialization - basic procedure for starting e-ink display. * Start the display settings and select communication, write LUT table. * Print text to the display by changing font size * * ## Application Task * Drawing an image to the display every 1 second. * * *note:* * - Create Image: * Save the image in resolution of 128x296 px with the extension (monochrome bmp) ... * Upload the image to Image2Lcd program * Set parameters to: * 1. Output file type : C array * 2. Scan Mode : Horisontal scan * 3. Bits Pixel : monochrome * 4. Max width and height : 128x296 * 5. Check only MSB first * 6. Check Reverse color and adjust Normal type * The image to be generated should contain about 5000 bytes ... * Insert the image into the file eINK_290_display_image.h * * - Create Font: * Close existing project, open a new VTFT project * Add label and adjust text font * Generate source code * Copy the font from resource.c file to this project in file eINK_290_display_font.h * * - Create new functions: * At the beginning of your new function, set eink290_setMemoryArea and eink290_setMemoryPointer * Create new pixels and create a new image buffer * Send command to write to RAM ( EINK290_CMD_WRITE_RAM ) * Forward 4736 data bytes .. * 1. By using the eink290_sendData function (sending one by one byte) * Finally call the eink290_updateDisplay function to see the image on the display * * *** Changing the LUT table can lead to loss of display performance .... * * \author MikroE Team * */ // ------------------------------------------------------------------- INCLUDES #include "board.h" #include "log.h" #include "eink_290inch.h" #include "eINK_290_display_image.h" #include "eINK_290_display_font.h" // ------------------------------------------------------------------ VARIABLES static eink_290inch_t eink_290inch; static log_t logger; char demo_text[ 5 ] = { 'e', 'I', 'N', 'K' , 0 }; char demo_text1[ 8 ] = { 'D', 'i', 's', 'p', 'l', 'a', 'y', 0 }; char demo_text2[ 10 ] = { '2', '.', '9', '0', 'i', 'n', 'c', 'h', 0 }; // ------------------------------------------------------- ADDITIONAL FUNCTIONS const uint8_t EINK290_LUT_TABLE_1[70]= { 0xA0,0x90,0x50,0x00,0x00,0x00,0x00, 0x50,0x90,0xA0,0x00,0x00,0x00,0x00, 0xA0,0x90,0x50,0x00,0x00,0x00,0x00, 0x50,0x90,0xA0,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0F,0x0F,0x0F,0x0F,0x02,0x10,0x10, 0x0A,0x0A,0x03,0x08,0x08,0x09,0x43, 0x07,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; // ------------------------------------------------------ APPLICATION FUNCTIONS void application_init ( void ) { log_cfg_t log_cfg; eink_290inch_cfg_t cfg; eink_290inch_font_t cfg_font; eink_290inch_set_text_t text_set; // Logger initialization. LOG_MAP_USB_UART( log_cfg ); log_cfg.level = LOG_LEVEL_DEBUG; log_cfg.baud = 9600; log_init( &logger, &log_cfg ); log_info( &logger, "---- Application Init ----" ); // Click initialization. eink_290inch_cfg_setup( &cfg ); EINK290INCH_MAP_MIKROBUS( cfg, MIKROBUS_1 ); eink_290inch_init( &eink_290inch, &cfg ); eink_290_start_config( &eink_290inch ); eink_290_set_lut( &eink_290inch, EINK290_LUT_TABLE_1, 70 ); cfg_font.p_font = &guiFont_Tahoma_18_Regular[ 0 ]; cfg_font.color = EINK290_SCREEN_COLOR_WHITE; cfg_font.orientation = EINK290_FO_HORIZONTAL; eink_290_set_font( &eink_290inch, &cfg_font ); text_set.n_char = 4; text_set.text_x = 7; text_set.text_y = 50; eink_290_text( &eink_290inch, &demo_text[ 0 ], &text_set ); Delay_ms( 1000 ); cfg_font.p_font = &guiFont_Tahoma_10_Regular[ 0 ]; cfg_font.color = EINK290_SCREEN_COLOR_WHITE; cfg_font.orientation = EINK290_FO_HORIZONTAL; eink_290_set_font( &eink_290inch, &cfg_font ); text_set.n_char = 7; text_set.text_x = 12; text_set.text_y = 90; eink_290_text( &eink_290inch, &demo_text1[ 0 ], &text_set ); Delay_ms( 1000 ); cfg_font.p_font = &guiFont_Tahoma_8_Regular[ 0 ]; cfg_font.color = EINK290_SCREEN_COLOR_WHITE; cfg_font.orientation = EINK290_FO_HORIZONTAL; eink_290_set_font( &eink_290inch, &cfg_font ); text_set.n_char = 9; text_set.text_x = 12; text_set.text_y = 120; eink_290_text( &eink_290inch, &demo_text2[ 0 ], &text_set ); Delay_ms( 1000 ); } void application_task ( void ) { eink_290_display_image( &eink_290inch, &demoImage_light[ 0 ] ); Delay_1sec( ); eink_290_display_image( &eink_290inch, &demoImage_dark[ 0 ] ); Delay_1sec( ); } void main ( void ) { application_init( ); for ( ; ; ) { application_task( ); } } // ------------------------------------------------------------------------ END

0d5014af169d6f8985406349c36ff48f9e50f5fa

f38db948bab7929d13decf1dc253a7973e80db11

/macros/efficiency/weightsInc_8TeV/TMVAClassification_Likelihood.class.C

323c80e242dccf6058d2045305c6459c142a0f3a

no_license

zukhaimira/UfHMuMuCode

82d71f0a9ead9bfa3158882d1208b23821dd0081

b52989c387c344f8a7f83595df7a6e116bec880f

refs/heads/master

UTF-8

C

c

// Class: ReadLikelihood // Automatically generated by MethodBase::MakeClass // /* configuration options ===================================================== #GEN -*-*-*-*-*-*-*-*-*-*-*- general info -*-*-*-*-*-*-*-*-*-*-*- Method : Likelihood::Likelihood TMVA Release : 4.1.2 [262402] ROOT Release : 5.32/00 [335872] Creator : jhugon Date : Wed Jan 23 11:25:27 2013 Host : Linux uftrig01 2.6.18-274.17.1.el5 #1 SMP Wed Jan 11 11:10:32 CET 2012 x86_64 x86_64 x86_64 GNU/Linux Dir : /data/uftrig01b/jhugon/hmumu/analysisV00-01-10 Training events: 1421612 Analysis type : [Classification] #OPT -*-*-*-*-*-*-*-*-*-*-*-*- options -*-*-*-*-*-*-*-*-*-*-*-*- # Set by User: V: "False" [Verbose output (short form of "VerbosityLevel" below - overrides the latter one)] H: "True" [Print method-specific help message] TransformOutput: "True" [Transform likelihood output by inverse sigmoid function] # Default: VerbosityLevel: "Default" [Verbosity level] VarTransform: "None" [List of variable transformations performed before training, e.g., "D_Background,P_Signal,G,N_AllClasses" for: "Decorrelation, PCA-transformation, Gaussianisation, Normalisation, each for the given class of events ('AllClasses' denotes all events of all classes, if no class indication is given, 'All' is assumed)"] CreateMVAPdfs: "False" [Create PDFs for classifier outputs (signal and background)] IgnoreNegWeightsInTraining: "False" [Events with negative weights are ignored in the training (but are included for testing and performance evaluation)] ## #VAR -*-*-*-*-*-*-*-*-*-*-*-* variables *-*-*-*-*-*-*-*-*-*-*-*- NVar 3 ptDiMu ptDiMu ptDiMu ptDiMu 'F' [0.00680064223707,1167.73059082] yDiMu yDiMu yDiMu yDiMu 'F' [-2.09949946404,2.09889316559] cosThetaStar cosThetaStar cosThetaStar cosThetaStar 'F' [-0.999975323677,0.999994874001] NSpec 33 mDiMu mDiMu mDiMu mDiMu 'F' [70.0003128052,159.997802734] mDiJet mDiJet mDiJet mDiJet 'F' [-10,1811.97058105] ptDiJet ptDiJet ptDiJet ptDiJet 'F' [-10,1030.38183594] yDiJet yDiJet yDiJet yDiJet 'F' [-10,4.4340262413] ptMu1 ptMu1 ptMu1 ptMu1 'F' [25.0342025757,838.69708252] ptMu2 ptMu2 ptMu2 ptMu2 'F' [25.0000209808,520.315917969] etaMu1 etaMu1 etaMu1 etaMu1 'F' [-2.09999346733,2.0999917984] etaMu2 etaMu2 etaMu2 etaMu2 'F' [-2.09999346733,2.09999918938] ptJet1 ptJet1 ptJet1 ptJet1 'F' [-10,1069.79284668] ptJet2 ptJet2 ptJet2 ptJet2 'F' [-10,802.2890625] etaJet1 etaJet1 etaJet1 etaJet1 'F' [-10,4.69862174988] etaJet2 etaJet2 etaJet2 etaJet2 'F' [-10,4.69629192352] cosThetaStarCS cosThetaStarCS cosThetaStarCS cosThetaStarCS 'F' [-0.99996972084,0.999971807003] deltaEtaJets deltaEtaJets deltaEtaJets deltaEtaJets 'F' [-10,4.56191921234] productEtaJets productEtaJets productEtaJets productEtaJets 'F' [-4.77376651764,20.0798492432] nJetsInRapidityGap nJetsInRapidityGap nJetsInRapidityGap nJetsInRapidityGap 'F' [0,5] deltaEtaMuons deltaEtaMuons deltaEtaMuons deltaEtaMuons 'F' [2.38418579102e-06,3.42767262459] deltaPhiMuons deltaPhiMuons deltaPhiMuons deltaPhiMuons 'F' [-3.14159250259,3.14159250259] deltaRMuons deltaRMuons deltaRMuons deltaRMuons 'F' [0.164975017309,4.60905170441] deltaPhiJets deltaPhiJets deltaPhiJets deltaPhiJets 'F' [-10,3.1415874958] deltaRJets deltaRJets deltaRJets deltaRJets 'F' [-10,5.42846107483] deltaPhiHJ1 deltaPhiHJ1 deltaPhiHJ1 deltaPhiHJ1 'F' [-10,3.14158535004] relIsoMu1 relIsoMu1 relIsoMu1 relIsoMu1 'F' [0,0.119999833405] relIsoMu2 relIsoMu2 relIsoMu2 relIsoMu2 'F' [0,0.119999818504] ht ht ht ht 'F' [0,2186.74121094] nJets nJets nJets nJets 'F' [0,9] nVtx nVtx nVtx nVtx 'F' [1,59] htInRapidityGap htInRapidityGap htInRapidityGap htInRapidityGap 'F' [0,279.8934021] met met met met 'F' [0.0227062087506,715.028625488] ptmiss ptmiss ptmiss ptmiss 'F' [-10,709.591064453] puJetIDSimpleDiscJet1 puJetIDSimpleDiscJet1 puJetIDSimpleDiscJet1 puJetIDSimpleDiscJet1 'F' [-10,0.992504835129] puJetIDSimpleDiscJet2 puJetIDSimpleDiscJet2 puJetIDSimpleDiscJet2 puJetIDSimpleDiscJet2 'F' [-10,0.991926014423] puJetIDSimpleDiscJet3 puJetIDSimpleDiscJet3 puJetIDSimpleDiscJet3 puJetIDSimpleDiscJet3 'F' [-10,0.990395784378] ============================================================================ */ #include <vector> #include <cmath> #include <string> #include <iostream> #include <math.h> #include <cstdlib> #ifndef IClassifierReader__def #define IClassifierReader__def class IClassifierReader { public: // constructor IClassifierReader() : fStatusIsClean( true ) {} virtual ~IClassifierReader() {} // return classifier response virtual double GetMvaValue( const std::vector<double>& inputValues ) const = 0; // returns classifier status bool IsStatusClean() const { return fStatusIsClean; } protected: bool fStatusIsClean; }; #endif class ReadLikelihood : public IClassifierReader { public: // constructor ReadLikelihood( std::vector<std::string>& theInputVars ) : IClassifierReader(), fClassName( "ReadLikelihood" ), fNvars( 3 ), fIsNormalised( false ) { // the training input variables const char* inputVars[] = { "ptDiMu", "yDiMu", "cosThetaStar" }; // sanity checks if (theInputVars.size() <= 0) { std::cout << "Problem in class \"" << fClassName << "\": empty input vector" << std::endl; fStatusIsClean = false; } if (theInputVars.size() != fNvars) { std::cout << "Problem in class \"" << fClassName << "\": mismatch in number of input values: " << theInputVars.size() << " != " << fNvars << std::endl; fStatusIsClean = false; } // validate input variables for (size_t ivar = 0; ivar < theInputVars.size(); ivar++) { if (theInputVars[ivar] != inputVars[ivar]) { std::cout << "Problem in class \"" << fClassName << "\": mismatch in input variable names" << std::endl << " for variable [" << ivar << "]: " << theInputVars[ivar].c_str() << " != " << inputVars[ivar] << std::endl; fStatusIsClean = false; } } // initialize min and max vectors (for normalisation) fVmin[0] = 0.00680064223706722; fVmax[0] = 1167.73059082031; fVmin[1] = -2.09949946403503; fVmax[1] = 2.09889316558838; fVmin[2] = -0.999975323677063; fVmax[2] = 0.999994874000549; // initialize input variable types fType[0] = 'F'; fType[1] = 'F'; fType[2] = 'F'; // initialize constants Initialize(); } // destructor virtual ~ReadLikelihood() { Clear(); // method-specific } // the classifier response // "inputValues" is a vector of input values in the same order as the // variables given to the constructor double GetMvaValue( const std::vector<double>& inputValues ) const; private: // method-specific destructor void Clear(); // common member variables const char* fClassName; const size_t fNvars; size_t GetNvar() const { return fNvars; } char GetType( int ivar ) const { return fType[ivar]; } // normalisation of input variables const bool fIsNormalised; bool IsNormalised() const { return fIsNormalised; } double fVmin[3]; double fVmax[3]; double NormVariable( double x, double xmin, double xmax ) const { // normalise to output range: [-1, 1] return 2*(x - xmin)/(xmax - xmin) - 1.0; } // type of input variable: 'F' or 'I' char fType[3]; // initialize internal variables void Initialize(); double GetMvaValue__( const std::vector<double>& inputValues ) const; // private members (method specific) double fEpsilon; static float fRefS[][10000]; // signal reference vector [nvars][max_nbins] static float fRefB[][10000]; // backgr reference vector [nvars][max_nbins] // if a variable has its PDF encoded as a spline0 --> treat it like an Integer valued one bool fHasDiscretPDF[3]; int fNbin[3]; // number of bins (discrete variables may have less bins) double fHistMin[3]; double fHistMax[3]; double TransformLikelihoodOutput( double, double ) const; }; inline void ReadLikelihood::Initialize() { fEpsilon = 2.2250738585072e-305; fNbin[0] = 10000; fHistMin[0] = 0.00680064223706722; fHistMax[0] = 1167.73059082031; fNbin[1] = 10000; fHistMin[1] = -2.09949946403503; fHistMax[1] = 2.09889316558838; fNbin[2] = 10000; fHistMin[2] = -0.999975323677063; fHistMax[2] = 0.999994874000549; fHasDiscretPDF[0] = false; fHasDiscretPDF[1] = false; fHasDiscretPDF[2] = false; } inline double ReadLikelihood::GetMvaValue__( const std::vector<double>& inputValues ) const { double ps(1), pb(1); std::vector<double> inputValuesSig = inputValues; std::vector<double> inputValuesBgd = inputValues; for (size_t ivar = 0; ivar < GetNvar(); ivar++) { // dummy at present... will be used for variable transforms double x[2] = { inputValuesSig[ivar], inputValuesBgd[ivar] }; for (int itype=0; itype < 2; itype++) { // interpolate linearly between adjacent bins // this is not useful for discrete variables (or forced Spline0) int bin = int((x[itype] - fHistMin[ivar])/(fHistMax[ivar] - fHistMin[ivar])*fNbin[ivar]) + 0; // since the test data sample is in general different from the training sample // it can happen that the min/max of the training sample are trespassed --> correct this if (bin < 0) { bin = 0; x[itype] = fHistMin[ivar]; } else if (bin >= fNbin[ivar]) { bin = fNbin[ivar]-1; x[itype] = fHistMax[ivar]; } // find corresponding histogram from cached indices float ref = (itype == 0) ? fRefS[ivar][bin] : fRefB[ivar][bin]; // sanity check if (ref < 0) { std::cout << "Fatal error in ReadLikelihood: bin entry < 0 ==> abort" << std::endl; std::exit(1); } double p = ref; if (GetType(ivar) != 'I' && !fHasDiscretPDF[ivar]) { float bincenter = (bin + 0.5)/fNbin[ivar]*(fHistMax[ivar] - fHistMin[ivar]) + fHistMin[ivar]; int nextbin = bin; if ((x[itype] > bincenter && bin != fNbin[ivar]-1) || bin == 0) nextbin++; else nextbin--; double refnext = (itype == 0) ? fRefS[ivar][nextbin] : fRefB[ivar][nextbin]; float nextbincenter = (nextbin + 0.5)/fNbin[ivar]*(fHistMax[ivar] - fHistMin[ivar]) + fHistMin[ivar]; double dx = bincenter - nextbincenter; double dy = ref - refnext; p += (x[itype] - bincenter) * dy/dx; } if (p < fEpsilon) p = fEpsilon; // avoid zero response if (itype == 0) ps *= p; else pb *= p; } } // the likelihood ratio (transform it ?) return TransformLikelihoodOutput( ps, pb ); } inline double ReadLikelihood::TransformLikelihoodOutput( double ps, double pb ) const { // returns transformed or non-transformed output if (ps < fEpsilon) ps = fEpsilon; if (pb < fEpsilon) pb = fEpsilon; double r = ps/(ps + pb); if (r >= 1.0) r = 1. - 1.e-15; if (true) { // inverse Fermi function // sanity check if (r <= 0.0) r = fEpsilon; else if (r >= 1.0) r = 1. - 1.e-15; double tau = 15.0; r = - log(1.0/r - 1.0)/tau; } return r; } // Clean up inline void ReadLikelihood::Clear() { // nothing to clear } // signal map float ReadLikelihood::fRefS[][10000] = { { 0.0109861455857754, 0.0110976155847311, 0.0112083582207561, 0.0113183734938502, 0.0114276604726911, 0.0115362210199237, 0.011644053272903, 0.011751159094274, 0.0118575366213918, 0.0119631867855787, 0.0120681095868349, 0.0121723050251603, 0.0122757731005549, 0.0123785138130188, 0.0124805271625519, 0.0125818122178316, 0.0126823699101806, 0.0127822011709213, 0.0128813032060862, 0.0129796806722879, 0.0130773279815912, 0.0131742488592863, 0.0132704423740506, 0.0133659075945616, 0.0134606463834643, 0.0135546568781137, 0.013647940941155, 0.0137404957786202, 0.0138323241844773, 0.0139234252274036, 0.0140137989073992, 0.0141034452244639, 0.0141923632472754, 0.014280553907156, 0.0143680172041059, 0.0144547540694475, 0.0145407635718584, 0.0146260438486934, 0.0147105976939201, 0.0147944232448936, 0.0148775223642588, 0.0149598931893706, 0.0150415385141969, 0.0151224555447698, 0.0152026424184442, 0.0152821037918329, 0.0153608387336135, 0.0154388453811407, 0.0155161237344146, 0.0155926756560802, 0.0156685002148151, 0.0157435964792967, 0.01581796631217, 0.01589160785079, 0.0159645229578018, 0.0160367097705603, 0.0161081682890654, 0.0161789003759623, 0.0162489041686058, 0.016318179666996, 0.0163867305964231, 0.0164545513689518, 0.0165216475725174, 0.0165880154818296, 0.0166536532342434, 0.0167185645550489, 0.0167827513068914, 0.0168462079018354, 0.0169089380651712, 0.0169709399342537, 0.0170322135090828, 0.0170927606523037, 0.0171525813639164, 0.0172116719186306, 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0.062069353, 0.061955638, 0.061842561, 0.061729442, 0.06161752, 0.061506819, 0.061396673, 0.061287172, 0.061177626, 0.061069265, 0.060962155, 0.060855586, 0.060749654, 0.060643706, 0.060538914, 0.060435999, 0.060333021, 0.060230628, 0.060128253, 0.060027655, 0.059927676, 0.059828311, 0.059730113, 0.059631307, 0.05959652, 0.05953778, 0.059479669, 0.0594231, 0.059365604, 0.0593112, 0.059258029, 0.059204243, 0.059153236, 0.059101924, 0.059051849, 0.059002388, 0.058955092, 0.058908109, 0.058862668, 0.058817226, 0.058773331, 0.058730673, 0.058688629, 0.058648139, 0.058607336, 0.058569003, 0.058531601, 0.058494508, 0.058459263, 0.058422789, 0.058389407, 0.058357257, 0.058325417, 0.058294818, 0.058264211, 0.058235466, 0.058207951, 0.058181368, 0.058156021, 0.058130369, 0.058106564, 0.058085233, 0.05806236, 0.058042578, 0.058022175, 0.058003627, 0.05798601, 0.057969008, 0.05795417, 0.057937782, 0.0579248, 0.05791213, 0.057900384, 0.05789049, 0.057879049, 0.057871323, 0.057863288, 0.057856794, 0.057851538, 0.057845667, 0.057842579, 0.057791341, 0.057794746, 0.057796907, 0.057800308, 0.057802469, 0.057804327, 0.057807103, 0.057808653, 0.057809275, 0.057811126, 0.057810817, 0.057813287, 0.0578136, 0.057812978, 0.057813287, 0.057813287, 0.057812668, 0.057812054, 0.057811126, 0.05780958, 0.05780958, 0.057807416, 0.057805251, 0.057804015, 0.057801541, 0.057798758, 0.057795975, 0.057792574, 0.057790413, 0.057786088, 0.057783306, 0.057778668, 0.057774652, 0.057770938, 0.057765685, 0.057761051, 0.057756718, 0.057751775, 0.057745282, 0.057739101, 0.057733845, 0.05772797, 0.057722095, 0.057714682, 0.057708185, 0.05770139, 0.057693355, 0.05768593, 0.05767728, 0.057670791, 0.057662439, 0.057653788, 0.057644513, 0.057635546, 0.057626583, 0.05761762, 0.057607725, 0.057545677, 0.057510134, 0.057473656, 0.057436254, 0.057397306, 0.057359591, 0.057320025, 0.057279527, 0.057237796, 0.057197299, 0.057153407, 0.05711044, 0.057065003, 0.05702018, 0.056974739, 0.056927755, 0.05688015, 0.056833167, 0.056782164, 0.056733631, 0.056682006, 0.056630693, 0.056579381, 0.056525595, 0.056471501, 0.056416474, 0.056361146, 0.056304887, 0.056248318, 0.056190204, 0.056133021, 0.056073051, 0.056011535, 0.055950325, 0.055888813, 0.055826064, 0.055762697, 0.055698402, 0.055634104, 0.055569191, 0.055501804, 0.055434413, 0.055365484, 0.055296548, 0.055227, 0.055156827, 0.055084802, 0.055012163, 0.054940447, 0.054866567, 0.054791763, 0.054716032, 0.054640606, 0.054563325, 0.054485124, 0.054405987, 0.054328088, 0.054246172, 0.054169513, 0.054093469, 0.054015573, 0.053936437, 0.053858541, 0.053778168, 0.053697798, 0.053617429, 0.053535823, 0.05345298, 0.053371374, 0.053287294, 0.053203214, 0.053119134, 0.053033818, 0.052947886, 0.052860714, 0.052773543, 0.052686371, 0.052597348, 0.052507702, 0.052418679, 0.052328415, 0.0522363, 0.052146036, 0.052052684, 0.05195995, 0.051866595, 0.051771391, 0.05167618, 0.051581591, 0.051485147, 0.051388085, 0.051291022, 0.051192723, 0.051095042, 0.05099427, 0.050894115, 0.050793961, 0.050692573, 0.050590567, 0.050488558, 0.050384693, 0.050280832, 0.050176967, 0.050071251, 0.049966149, 0.049859196, 0.049751624, 0.049643435, 0.049536481, 0.049427051, 0.049317006, 0.049207579, 0.049096297, 0.048985634, 0.048872497, 0.048759978, 0.048646227, 0.048531853, 0.04841686, 0.048302487, 0.048186261, 0.048068795, 0.047952566, 0.047833867, 0.047715168, 0.047597084, 0.047475912, 0.047356594, 0.0472348, 0.04711239, 0.046989977, 0.046867568, 0.046743304, 0.04662028, 0.046494775, 0.046368659, 0.046242535, 0.046115182, 0.045987826, 0.045860469, 0.045731261, 0.045601431, 0.04547222 }, }; inline double ReadLikelihood::GetMvaValue( const std::vector<double>& inputValues ) const { // classifier response value double retval = 0; // classifier response, sanity check first if (!IsStatusClean()) { std::cout << "Problem in class \"" << fClassName << "\": cannot return classifier response" << " because status is dirty" << std::endl; retval = 0; } else { if (IsNormalised()) { // normalise variables std::vector<double> iV; int ivar = 0; for (std::vector<double>::const_iterator varIt = inputValues.begin(); varIt != inputValues.end(); varIt++, ivar++) { iV.push_back(NormVariable( *varIt, fVmin[ivar], fVmax[ivar] )); } retval = GetMvaValue__( iV ); } else { retval = GetMvaValue__( inputValues ); } } return retval; }

6a1b572580cf5d0b6f1f99d6f1406b5b1aedebe6

44449845d88f056e528d39babd57a248fe309834

/kernel/tirtos/packages/ti/sysbios/hal/CoreNull.h

a27b96cf3e80e47e3bf9db10406f44e8cf146cdc

no_license

ndrs-pst/simplelink_cc32xx_sdk

cf60675af09759aa38559e6891d7f20d68fd0207

965b7fac5ed11f24e7e8ee316bbd39b337d4f7de

refs/heads/main

UTF-8

C

h

/* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-K04 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ #ifndef ti_sysbios_hal_CoreNull__include #define ti_sysbios_hal_CoreNull__include #ifndef __nested__ #define __nested__ #define ti_sysbios_hal_CoreNull__top__ #endif #ifndef __extern #ifdef __cplusplus #define __extern extern "C" #else #define __extern extern #endif #endif #define ti_sysbios_hal_CoreNull___VERS 200 /* * ======== INCLUDES ======== */ #include <xdc/std.h> #include <xdc/runtime/xdc.h> #include <xdc/runtime/Types.h> #include <ti/sysbios/hal/package/package.defs.h> #include <ti/sysbios/interfaces/ICore.h> /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_hal_CoreNull_Module__diagsEnabled; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__diagsEnabled ti_sysbios_hal_CoreNull_Module__diagsEnabled__C; #ifdef ti_sysbios_hal_CoreNull_Module__diagsEnabled__CR #define ti_sysbios_hal_CoreNull_Module__diagsEnabled__C (*((CT__ti_sysbios_hal_CoreNull_Module__diagsEnabled*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__diagsEnabled__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__diagsEnabled (ti_sysbios_hal_CoreNull_Module__diagsEnabled__C) #endif /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_hal_CoreNull_Module__diagsIncluded; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__diagsIncluded ti_sysbios_hal_CoreNull_Module__diagsIncluded__C; #ifdef ti_sysbios_hal_CoreNull_Module__diagsIncluded__CR #define ti_sysbios_hal_CoreNull_Module__diagsIncluded__C (*((CT__ti_sysbios_hal_CoreNull_Module__diagsIncluded*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__diagsIncluded__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__diagsIncluded (ti_sysbios_hal_CoreNull_Module__diagsIncluded__C) #endif /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_hal_CoreNull_Module__diagsMask; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__diagsMask ti_sysbios_hal_CoreNull_Module__diagsMask__C; #ifdef ti_sysbios_hal_CoreNull_Module__diagsMask__CR #define ti_sysbios_hal_CoreNull_Module__diagsMask__C (*((CT__ti_sysbios_hal_CoreNull_Module__diagsMask*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__diagsMask__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__diagsMask (ti_sysbios_hal_CoreNull_Module__diagsMask__C) #endif /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_hal_CoreNull_Module__gateObj; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__gateObj ti_sysbios_hal_CoreNull_Module__gateObj__C; #ifdef ti_sysbios_hal_CoreNull_Module__gateObj__CR #define ti_sysbios_hal_CoreNull_Module__gateObj__C (*((CT__ti_sysbios_hal_CoreNull_Module__gateObj*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__gateObj__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__gateObj (ti_sysbios_hal_CoreNull_Module__gateObj__C) #endif /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_hal_CoreNull_Module__gatePrms; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__gatePrms ti_sysbios_hal_CoreNull_Module__gatePrms__C; #ifdef ti_sysbios_hal_CoreNull_Module__gatePrms__CR #define ti_sysbios_hal_CoreNull_Module__gatePrms__C (*((CT__ti_sysbios_hal_CoreNull_Module__gatePrms*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__gatePrms__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__gatePrms (ti_sysbios_hal_CoreNull_Module__gatePrms__C) #endif /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_hal_CoreNull_Module__id; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__id ti_sysbios_hal_CoreNull_Module__id__C; #ifdef ti_sysbios_hal_CoreNull_Module__id__CR #define ti_sysbios_hal_CoreNull_Module__id__C (*((CT__ti_sysbios_hal_CoreNull_Module__id*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__id__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__id (ti_sysbios_hal_CoreNull_Module__id__C) #endif /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_hal_CoreNull_Module__loggerDefined; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__loggerDefined ti_sysbios_hal_CoreNull_Module__loggerDefined__C; #ifdef ti_sysbios_hal_CoreNull_Module__loggerDefined__CR #define ti_sysbios_hal_CoreNull_Module__loggerDefined__C (*((CT__ti_sysbios_hal_CoreNull_Module__loggerDefined*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__loggerDefined__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__loggerDefined (ti_sysbios_hal_CoreNull_Module__loggerDefined__C) #endif /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_hal_CoreNull_Module__loggerObj; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__loggerObj ti_sysbios_hal_CoreNull_Module__loggerObj__C; #ifdef ti_sysbios_hal_CoreNull_Module__loggerObj__CR #define ti_sysbios_hal_CoreNull_Module__loggerObj__C (*((CT__ti_sysbios_hal_CoreNull_Module__loggerObj*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__loggerObj__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__loggerObj (ti_sysbios_hal_CoreNull_Module__loggerObj__C) #endif /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_hal_CoreNull_Module__loggerFxn0; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__loggerFxn0 ti_sysbios_hal_CoreNull_Module__loggerFxn0__C; #ifdef ti_sysbios_hal_CoreNull_Module__loggerFxn0__CR #define ti_sysbios_hal_CoreNull_Module__loggerFxn0__C (*((CT__ti_sysbios_hal_CoreNull_Module__loggerFxn0*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__loggerFxn0__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__loggerFxn0 (ti_sysbios_hal_CoreNull_Module__loggerFxn0__C) #endif /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_hal_CoreNull_Module__loggerFxn1; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__loggerFxn1 ti_sysbios_hal_CoreNull_Module__loggerFxn1__C; #ifdef ti_sysbios_hal_CoreNull_Module__loggerFxn1__CR #define ti_sysbios_hal_CoreNull_Module__loggerFxn1__C (*((CT__ti_sysbios_hal_CoreNull_Module__loggerFxn1*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__loggerFxn1__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__loggerFxn1 (ti_sysbios_hal_CoreNull_Module__loggerFxn1__C) #endif /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_hal_CoreNull_Module__loggerFxn2; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__loggerFxn2 ti_sysbios_hal_CoreNull_Module__loggerFxn2__C; #ifdef ti_sysbios_hal_CoreNull_Module__loggerFxn2__CR #define ti_sysbios_hal_CoreNull_Module__loggerFxn2__C (*((CT__ti_sysbios_hal_CoreNull_Module__loggerFxn2*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__loggerFxn2__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__loggerFxn2 (ti_sysbios_hal_CoreNull_Module__loggerFxn2__C) #endif /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_hal_CoreNull_Module__loggerFxn4; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__loggerFxn4 ti_sysbios_hal_CoreNull_Module__loggerFxn4__C; #ifdef ti_sysbios_hal_CoreNull_Module__loggerFxn4__CR #define ti_sysbios_hal_CoreNull_Module__loggerFxn4__C (*((CT__ti_sysbios_hal_CoreNull_Module__loggerFxn4*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__loggerFxn4__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__loggerFxn4 (ti_sysbios_hal_CoreNull_Module__loggerFxn4__C) #endif /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_hal_CoreNull_Module__loggerFxn8; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Module__loggerFxn8 ti_sysbios_hal_CoreNull_Module__loggerFxn8__C; #ifdef ti_sysbios_hal_CoreNull_Module__loggerFxn8__CR #define ti_sysbios_hal_CoreNull_Module__loggerFxn8__C (*((CT__ti_sysbios_hal_CoreNull_Module__loggerFxn8*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__loggerFxn8__C_offset))) #else #define ti_sysbios_hal_CoreNull_Module__loggerFxn8 (ti_sysbios_hal_CoreNull_Module__loggerFxn8__C) #endif /* Object__count */ typedef xdc_Int CT__ti_sysbios_hal_CoreNull_Object__count; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Object__count ti_sysbios_hal_CoreNull_Object__count__C; #ifdef ti_sysbios_hal_CoreNull_Object__count__CR #define ti_sysbios_hal_CoreNull_Object__count__C (*((CT__ti_sysbios_hal_CoreNull_Object__count*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Object__count__C_offset))) #else #define ti_sysbios_hal_CoreNull_Object__count (ti_sysbios_hal_CoreNull_Object__count__C) #endif /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_hal_CoreNull_Object__heap; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Object__heap ti_sysbios_hal_CoreNull_Object__heap__C; #ifdef ti_sysbios_hal_CoreNull_Object__heap__CR #define ti_sysbios_hal_CoreNull_Object__heap__C (*((CT__ti_sysbios_hal_CoreNull_Object__heap*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Object__heap__C_offset))) #else #define ti_sysbios_hal_CoreNull_Object__heap (ti_sysbios_hal_CoreNull_Object__heap__C) #endif /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_hal_CoreNull_Object__sizeof; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Object__sizeof ti_sysbios_hal_CoreNull_Object__sizeof__C; #ifdef ti_sysbios_hal_CoreNull_Object__sizeof__CR #define ti_sysbios_hal_CoreNull_Object__sizeof__C (*((CT__ti_sysbios_hal_CoreNull_Object__sizeof*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Object__sizeof__C_offset))) #else #define ti_sysbios_hal_CoreNull_Object__sizeof (ti_sysbios_hal_CoreNull_Object__sizeof__C) #endif /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_hal_CoreNull_Object__table; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_Object__table ti_sysbios_hal_CoreNull_Object__table__C; #ifdef ti_sysbios_hal_CoreNull_Object__table__CR #define ti_sysbios_hal_CoreNull_Object__table__C (*((CT__ti_sysbios_hal_CoreNull_Object__table*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Object__table__C_offset))) #else #define ti_sysbios_hal_CoreNull_Object__table (ti_sysbios_hal_CoreNull_Object__table__C) #endif /* numCores */ typedef xdc_UInt CT__ti_sysbios_hal_CoreNull_numCores; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_numCores ti_sysbios_hal_CoreNull_numCores__C; #ifdef ti_sysbios_hal_CoreNull_numCores__CR #define ti_sysbios_hal_CoreNull_numCores (*((CT__ti_sysbios_hal_CoreNull_numCores*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_numCores__C_offset))) #else #ifdef ti_sysbios_hal_CoreNull_numCores__D #define ti_sysbios_hal_CoreNull_numCores (ti_sysbios_hal_CoreNull_numCores__D) #else #define ti_sysbios_hal_CoreNull_numCores (ti_sysbios_hal_CoreNull_numCores__C) #endif #endif /* id */ typedef xdc_UInt CT__ti_sysbios_hal_CoreNull_id; __extern __FAR__ const CT__ti_sysbios_hal_CoreNull_id ti_sysbios_hal_CoreNull_id__C; #ifdef ti_sysbios_hal_CoreNull_id__CR #define ti_sysbios_hal_CoreNull_id (*((CT__ti_sysbios_hal_CoreNull_id*)(xdcRomConstPtr + ti_sysbios_hal_CoreNull_id__C_offset))) #else #ifdef ti_sysbios_hal_CoreNull_id__D #define ti_sysbios_hal_CoreNull_id (ti_sysbios_hal_CoreNull_id__D) #else #define ti_sysbios_hal_CoreNull_id (ti_sysbios_hal_CoreNull_id__C) #endif #endif /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_hal_CoreNull_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_UInt (*getId)(void); xdc_Void (*interruptCore)(xdc_UInt coreId); xdc_IArg (*lock)(void); xdc_Void (*unlock)(void); xdc_UInt (*hwiDisable)(void); xdc_UInt (*hwiEnable)(void); xdc_Void (*hwiRestore)(xdc_UInt key); xdc_runtime_Types_SysFxns2 __sfxns; }; #ifndef ti_sysbios_hal_CoreNull_Module__FXNS__CR /* Module__FXNS__C */ __extern const ti_sysbios_hal_CoreNull_Fxns__ ti_sysbios_hal_CoreNull_Module__FXNS__C; #else #define ti_sysbios_hal_CoreNull_Module__FXNS__C (*(xdcRomConstPtr + ti_sysbios_hal_CoreNull_Module__FXNS__C_offset)) #endif /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ #define ti_sysbios_hal_CoreNull_Module_startup( state ) (-1) /* Module__startupDone__S */ xdc__CODESECT(ti_sysbios_hal_CoreNull_Module__startupDone__S, "ti_sysbios_hal_CoreNull_Module__startupDone__S") __extern xdc_Bool ti_sysbios_hal_CoreNull_Module__startupDone__S( void); /* getId__E */ #define ti_sysbios_hal_CoreNull_getId ti_sysbios_hal_CoreNull_getId__E xdc__CODESECT(ti_sysbios_hal_CoreNull_getId__E, "ti_sysbios_hal_CoreNull_getId") __extern xdc_UInt ti_sysbios_hal_CoreNull_getId__E( void); /* interruptCore__E */ #define ti_sysbios_hal_CoreNull_interruptCore ti_sysbios_hal_CoreNull_interruptCore__E xdc__CODESECT(ti_sysbios_hal_CoreNull_interruptCore__E, "ti_sysbios_hal_CoreNull_interruptCore") __extern xdc_Void ti_sysbios_hal_CoreNull_interruptCore__E( xdc_UInt coreId); /* lock__E */ #define ti_sysbios_hal_CoreNull_lock ti_sysbios_hal_CoreNull_lock__E xdc__CODESECT(ti_sysbios_hal_CoreNull_lock__E, "ti_sysbios_hal_CoreNull_lock") __extern xdc_IArg ti_sysbios_hal_CoreNull_lock__E( void); /* unlock__E */ #define ti_sysbios_hal_CoreNull_unlock ti_sysbios_hal_CoreNull_unlock__E xdc__CODESECT(ti_sysbios_hal_CoreNull_unlock__E, "ti_sysbios_hal_CoreNull_unlock") __extern xdc_Void ti_sysbios_hal_CoreNull_unlock__E( void); /* hwiDisable__E */ #define ti_sysbios_hal_CoreNull_hwiDisable ti_sysbios_hal_CoreNull_hwiDisable__E xdc__CODESECT(ti_sysbios_hal_CoreNull_hwiDisable__E, "ti_sysbios_hal_CoreNull_hwiDisable") __extern xdc_UInt ti_sysbios_hal_CoreNull_hwiDisable__E( void); /* hwiEnable__E */ #define ti_sysbios_hal_CoreNull_hwiEnable ti_sysbios_hal_CoreNull_hwiEnable__E xdc__CODESECT(ti_sysbios_hal_CoreNull_hwiEnable__E, "ti_sysbios_hal_CoreNull_hwiEnable") __extern xdc_UInt ti_sysbios_hal_CoreNull_hwiEnable__E( void); /* hwiRestore__E */ #define ti_sysbios_hal_CoreNull_hwiRestore ti_sysbios_hal_CoreNull_hwiRestore__E xdc__CODESECT(ti_sysbios_hal_CoreNull_hwiRestore__E, "ti_sysbios_hal_CoreNull_hwiRestore") __extern xdc_Void ti_sysbios_hal_CoreNull_hwiRestore__E( xdc_UInt key); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline ti_sysbios_interfaces_ICore_Module ti_sysbios_hal_CoreNull_Module_upCast(void); static inline ti_sysbios_interfaces_ICore_Module ti_sysbios_hal_CoreNull_Module_upCast(void) { return (ti_sysbios_interfaces_ICore_Module)&ti_sysbios_hal_CoreNull_Module__FXNS__C; } /* Module_to_ti_sysbios_interfaces_ICore */ #define ti_sysbios_hal_CoreNull_Module_to_ti_sysbios_interfaces_ICore ti_sysbios_hal_CoreNull_Module_upCast /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ #define ti_sysbios_hal_CoreNull_Module_startupDone() ti_sysbios_hal_CoreNull_Module__startupDone__S() /* Object_heap */ #define ti_sysbios_hal_CoreNull_Object_heap() ti_sysbios_hal_CoreNull_Object__heap__C /* Module_heap */ #define ti_sysbios_hal_CoreNull_Module_heap() ti_sysbios_hal_CoreNull_Object__heap__C /* Module_id */ static inline CT__ti_sysbios_hal_CoreNull_Module__id ti_sysbios_hal_CoreNull_Module_id(void); static inline CT__ti_sysbios_hal_CoreNull_Module__id ti_sysbios_hal_CoreNull_Module_id( void ) { return ti_sysbios_hal_CoreNull_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_hal_CoreNull_Module_hasMask(void); static inline xdc_Bool ti_sysbios_hal_CoreNull_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_hal_CoreNull_Module__diagsMask__C != (CT__ti_sysbios_hal_CoreNull_Module__diagsMask)NULL); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_hal_CoreNull_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_hal_CoreNull_Module_getMask(void) { return (ti_sysbios_hal_CoreNull_Module__diagsMask__C != (CT__ti_sysbios_hal_CoreNull_Module__diagsMask)NULL) ? *ti_sysbios_hal_CoreNull_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline xdc_Void ti_sysbios_hal_CoreNull_Module_setMask(xdc_Bits16 mask); static inline xdc_Void ti_sysbios_hal_CoreNull_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_hal_CoreNull_Module__diagsMask__C != (CT__ti_sysbios_hal_CoreNull_Module__diagsMask)NULL) { *ti_sysbios_hal_CoreNull_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ #ifdef ti_sysbios_hal_CoreNull__top__ #undef __nested__ #endif #endif /* ti_sysbios_hal_CoreNull__include */ /* * ======== STATE STRUCTURES ======== */ #if defined(__config__) || (!defined(__nested__) && defined(ti_sysbios_hal_CoreNull__internalaccess)) #ifndef ti_sysbios_hal_CoreNull__include_state #define ti_sysbios_hal_CoreNull__include_state #endif /* ti_sysbios_hal_CoreNull__include_state */ #endif /* * ======== PREFIX ALIASES ======== */ #if !defined(__nested__) && !defined(ti_sysbios_hal_CoreNull__nolocalnames) #ifndef ti_sysbios_hal_CoreNull__localnames__done #define ti_sysbios_hal_CoreNull__localnames__done /* module prefix */ #define CoreNull_numCores ti_sysbios_hal_CoreNull_numCores #define CoreNull_id ti_sysbios_hal_CoreNull_id #define CoreNull_getId ti_sysbios_hal_CoreNull_getId #define CoreNull_interruptCore ti_sysbios_hal_CoreNull_interruptCore #define CoreNull_lock ti_sysbios_hal_CoreNull_lock #define CoreNull_unlock ti_sysbios_hal_CoreNull_unlock #define CoreNull_hwiDisable ti_sysbios_hal_CoreNull_hwiDisable #define CoreNull_hwiEnable ti_sysbios_hal_CoreNull_hwiEnable #define CoreNull_hwiRestore ti_sysbios_hal_CoreNull_hwiRestore #define CoreNull_Module_name ti_sysbios_hal_CoreNull_Module_name #define CoreNull_Module_id ti_sysbios_hal_CoreNull_Module_id #define CoreNull_Module_startup ti_sysbios_hal_CoreNull_Module_startup #define CoreNull_Module_startupDone ti_sysbios_hal_CoreNull_Module_startupDone #define CoreNull_Module_hasMask ti_sysbios_hal_CoreNull_Module_hasMask #define CoreNull_Module_getMask ti_sysbios_hal_CoreNull_Module_getMask #define CoreNull_Module_setMask ti_sysbios_hal_CoreNull_Module_setMask #define CoreNull_Object_heap ti_sysbios_hal_CoreNull_Object_heap #define CoreNull_Module_heap ti_sysbios_hal_CoreNull_Module_heap #define CoreNull_Module_upCast ti_sysbios_hal_CoreNull_Module_upCast #define CoreNull_Module_to_ti_sysbios_interfaces_ICore ti_sysbios_hal_CoreNull_Module_to_ti_sysbios_interfaces_ICore #endif /* ti_sysbios_hal_CoreNull__localnames__done */ #endif

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/vulnerable_code/3ef7f59f-c1f8-4512-a102-129b3b0fe279.c

3533ec17429d0a26dde6e6f957dd0c59d56b37e0

no_license

nmharmon8/Deep-Buffer-Overflow-Detection

70fe02c8dc75d12e91f5bc4468cf260e490af1a4

e0c86210c86afb07c8d4abcc957c7f1b252b4eb2

refs/heads/master

UTF-8

C

c

#include <string.h> #include <stdio.h> int main() { int i=0; int j=14; int k; int l; k = 53; l = 64; k = i-j; l = i-j; l = l/j; l = l%j; l = i+j; k = l-k*i; //variables /* START VULNERABILITY */ int a; char b[60]; char c[67]; a = 0; do { //random /* START BUFFER SET */ *((char *)c + a) = *((char *)b + a); /* END BUFFER SET */ //random a++; } while(b[a] != 0); /* END VULNERABILITY */ //random printf("%d%d\n",k,l); return 0; }

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/linux/C/day11/06str.c

0b301b8fe9b0830b3def0e201083831f97c51f5d

no_license

chlinwei/linwei

ef4a2030867dc32e96fb4b132da40b4c314ca5e2

6f177e9328bf716bd82942dc8d6ba79e512e312d

refs/heads/master

UTF-8

C

c

/* 字符串练习 */ #include <stdio.h> #include <string.h> int main() { int rank = 0; char ranks[50] = {0}; char tmp[10] = {0}; do { printf("请输入一个考试成绩："); scanf("%d", &rank); if (rank < 0) { break; } sprintf(tmp, "%d,", rank); strcat(ranks, tmp); } while (1); ranks[strlen(ranks) - 1] = 0; printf("%s\n", ranks); return 0; }

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/AdventureGame2.c

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permissive

Abdul-Basith-siddiqui/C-Programs

fc7eaf2c74a7b2e049c9077ca2940a9998d6979b

5f12201c5061db8d5bae3c94e11dc5e9a9af7680

refs/heads/master

MIT

UTF-8

C

c

# include <stdio.h>// defines scanf() and printf() # include <math.h>//has math functions; exp(x,y) # include <stdlib.h>//defines rand() # include <string.h>// # include <time.h>//defines time() int n = 10; char arr[10][10]; int iPlayerPosition=0, jPlayerPosition=0; //Functions int movePlayer(int playersMove, char arr[][10], int iPosition, int jPosition); int moveCheck(int playersMove, char arr[][10], int iPosition, int jPosition); int wallCheck(int playersMove, char arr[][10], int iPosition, int jPosition); int moveCheck2(int playersMove, char arr[][10], int iPosition, int jPosition); int main(void) { int seed = time(NULL); srand(seed);// seeding random int playersMove; int i,j,k; int iRandom=rand()%n + 0 , jRandom =rand()%n + 0; // iRandom and jRandom range from 0 to 9; int TRUE; /////////////////////******************************* Setting up the grid *********////////////////////////////////////////////// // placing 0's into the array just to fill the gird and to know which are empty , so any array with a 0 is considered empty for(i=0; i<n; i++) for(j=0; j<n; j++) { arr[i][j] = '0'; }//*/ arr[0][0] = 'P';// starting P "the player" at the top left of the grid / board arr[n-1][n-1] = 'T';// Placing the treasure on the bottom left of the board for(k=0; k < n*(.5); k++)// the percentage of 'X' on the grid is 5% { if(arr[iRandom][jRandom] == '0') { arr[iRandom][jRandom] = 'X'; //printf("arr[%d][%d] = %c\n", iRandom, jRandom, arr[iRandom][jRandom]); iRandom = rand()%n + 0; // iRandom ranges from 0 to 9 jRandom = rand()%n + 0;// jRandom ranges from 0 to 9 } //*/ } for(k=0; k < n*(.10); k++)// the percentage of '*' on the grid is 10% { if(arr[iRandom][jRandom] == '0') { arr[iRandom][jRandom] = '*'; iRandom = rand()%n + 0; // iRandom ranges from 0 to 9 jRandom = rand()%n + 0;// jRandom ranges from 0 to 9 } } //FILLING UP THE REMAINDING SPOTS for(i=0; i<n; i++) for(j=0; j<n; j++) { if(arr[i][j] == '0') arr[i][j] = '.'; }//*/ ///////////////////////////////////////////////////////////////////END SETTING UP THE BOARD////////////////////////////////////////// char c; do{ printf("Welcome to the Adventure Game 8=up,2=down,4=left,6=right\n"); printf("X-BLOCK, *-DIE, T-TREASURE, P-PERSON\n"); printf("Object of the game is to get to the treasure\n\n"); for(i=0; i<n; i++) { for(j=0; j<n; j++) { printf("%c ", arr[i][j] ); } printf("\n"); } printf("Enter your move: "); scanf("%d", &playersMove); //printf("players move is %c\n", playersMove); TRUE = movePlayer(playersMove, arr, iPlayerPosition, jPlayerPosition); system("cls"); }while(TRUE != -1 &&TRUE != 2); system("pause"); } ///////////////////////////////////////////////////////////FUNCTIONS////////////////////////////////////////////////////////////// int movePlayer(int playersMove, char arr[][n], int iPosition, int jPosition) { int tempi = iPosition; int tempj = jPosition; int TRUE; // printf("players move is %c\n", playersMove); if(playersMove == 8) {//printf("move up\n"); iPlayerPosition -= 1; } else if(playersMove ==2 ) {//printf("move down\n"); iPlayerPosition += 1; } else if(playersMove == 6) {//printf("move right\n"); jPlayerPosition += 1; } else if(playersMove == 4) {//printf("move left\n"); jPlayerPosition -= 1; } TRUE = moveCheck(playersMove, arr, iPlayerPosition, jPlayerPosition); if( TRUE == 1 && wallCheck(playersMove, arr, iPlayerPosition, jPlayerPosition) == 1) { //swap arrays char temp = arr[tempi][tempj]; arr[tempi][tempj] =arr[iPlayerPosition][jPlayerPosition]; arr[iPlayerPosition][jPlayerPosition] = temp; return TRUE; } else { iPlayerPosition = iPosition; jPlayerPosition = jPosition; return TRUE; } } int moveCheck(int playersMove, char arr[][10], int iPosition, int jPosition) { if(arr[iPosition][jPosition] == 'X') { printf("Can't move there\n"); return 0; } if(arr[iPosition][jPosition] == '*') { printf("You Lose, Thank You for Playing\n"); //system("pause"); return -1; } if(arr[iPosition][jPosition] == 'T') { printf("Congratulations you win !\n"); system("pause"); return 2; } return 1; } int wallCheck(int playersMove, char arr[][10], int iPosition, int jPosition) { //Handling the corners if(iPosition<0 && jPosition<0 && (playersMove== 8 || playersMove==4)) { printf("Can't move there\n"); return 0; } else if(iPosition<0 && jPosition>9 && (playersMove== 8 || playersMove==6)) { printf("Can't move there\n"); return 0; } else if(iPosition>9 && jPosition<0 && (playersMove== 2 || playersMove==4)) { printf("Can't move there\n"); return 0; } else if(iPosition>9 && jPosition<0 && (playersMove== 2 || playersMove==6)) { printf("Can't move there\n"); return 0; } else// handling the ith rows and jth columns { if(iPosition < 0 && playersMove == 8) {printf("Can't move there\n"); return 0;} if(iPosition > 9 && playersMove == 2) {printf("Can't move there\n"); return 0;} if(jPosition < 0 && playersMove == 4) {printf("Can't move there\n"); return 0;} if(jPosition > 9 && playersMove == 6) {printf("Can't move there\n"); return 0;} } // printf("iPosition = %d , jPosition = %d\n", iPosition, jPosition); //system("pause"); return 1; } int moveCheck2(int playersMove, char arr[][10], int iPosition, int jPosition) { if(arr[iPosition][jPosition] == '*') { printf("You Lose, Thank You for Playing\n"); return 0; } return 1; }

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/ios/build/QRScanner/Build/Intermediates.noindex/QRScanner.build/Debug-iphoneos/QRScanner.build/DerivedSources/QRScanner_vers.c

1a4c3875bd412eec4665aeded85780437869907a

no_license

jessyjosephine/QRScanner

00f18202310f92038d04aaaa04f6def992ff551f

8f4b222dbef3f79a7deee55796735bb32288a397

refs/heads/master

UTF-8

C

c

extern const unsigned char QRScannerVersionString[]; extern const double QRScannerVersionNumber; const unsigned char QRScannerVersionString[] __attribute__ ((used)) = "@(#)PROGRAM:QRScanner PROJECT:QRScanner-1" "\n"; const double QRScannerVersionNumber __attribute__ ((used)) = (double)1.;

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bc2933859597a1acccb22e74ec95328f530becf6

/Codes in Unix/client.c

05a0226ad59332cfa437a0e8a0be20376abed759

no_license

Micazhang/Instant-Message-System

eb467009f103d3fb7e6c00a0ee11c27f1d42ed1b

b97123fca6dae223dcbb734b2b726eaa51782ecc

refs/heads/master

UTF-8

C

c

#include<stdio.h> #include<netinet/in.h> #include<sys/socket.h> #include<sys/types.h> #include<string.h> #include<stdlib.h> #include<netdb.h> #include<unistd.h> #include<signal.h> #include<time.h> #include<termios.h> int main(int argc,char *argv[]) { struct sockaddr_in clientaddr; pid_t pid; int clientfd,sendbytes,recvbytes; struct hostent *host; char *buf, *buf_r; struct termios term; long vdisable; vdisable=fpathconf(STDIN_FILENO,_PC_VDISABLE); tcgetattr(STDIN_FILENO,&term); term.c_cc[VINTR] = vdisable; term.c_cc[VINTR] = 4; tcsetattr(STDIN_FILENO,TCSAFLUSH,&term); if(argc<4) { printf("usage:\n"); printf("%s host port name\n",argv[0]); exit(1); } host=gethostbyname(argv[1]); if((clientfd=socket(AF_INET,SOCK_STREAM,0))==-1) { perror("socket\n"); exit(1); } clientaddr.sin_family = AF_INET; clientaddr.sin_port = htons((uint16_t)atoi(argv[2])); clientaddr.sin_addr = *((struct in_addr *)host->h_addr); bzero(&(clientaddr.sin_zero),0); if(connect(clientfd,(struct sockaddr *)&clientaddr,sizeof(struct sockaddr_in))==-1) { perror("connect\n"); exit(1); } buf=(char *)malloc(120); memset(buf,0,120); buf_r=(char *)malloc(100); if(recv(clientfd,buf,100,0)==-1) { perror("recv:"); exit(1); } printf("\n%s\n",buf); pid=fork(); while(1) { if(pid>0){ strcpy(buf,argv[3]); strcat(buf,":"); memset(buf_r,0,100); fgets(buf_r,100,stdin); strncat(buf,buf_r,strlen(buf_r)-1); if((sendbytes=send(clientfd,buf,strlen(buf),0))==-1) { perror("send\n"); exit(1); } } else if(pid == 0) { memset(buf,0,100); if(recv(clientfd,buf,100,0)<=0) { perror("recv:"); close(clientfd); raise(SIGSTOP); exit(1); } printf("%s\n",buf); } else perror("fork"); } close(clientfd); return 0; }

075dd95ee6914a04f431a01380bcf1412ba7d7b8

5eba39fa53189f3c334df06cc6487ec01eae679b

/Programas C/SEQUEN1.C

2cec763c0862671452ab08f10cd30d32f00a93a5

no_license

marcosinocencio/C

df938c268b954f6aca58fb64912ca521df3a4701

3d984929fca92e8d1348103fe2cbf7e1b2abde96

refs/heads/main

UTF-8

C

c

#include <stdio.h> #include <stdlib.h> #define MSG1 "Introduza o numero de termos da sequencia : " #define MSG2 "Introduza o %d-esimo termo da sequencia : " #define MSG4 "\n\nPor favor, introduza um numero MAIOR OU IGUAL a 1" #define MSG5 "\nPressione uma tecla para continuar!!!! " #define MSG6 "\n\n\n Pressione a tecla 's' ou 'S' para executar o programa novamente ou " #define MSG7 "\nqualquer outra tecla para finalizar. " int sp = 0, sn = 0, qp = 0, qn = 0, i = 1, n, num; int continua = 1; char ch; int main(void) { do { do { system("cls"); printf(MSG1); scanf("%d", &n); if ( n < 1 ) { printf(MSG4); printf("\n\n"); system("Pause"); } } while (n < 1); sp = sn = qp = qn = 0; i = 1; for ( ;i <= n; i++) { printf("\n"); printf(MSG2, i); scanf("%d", &num); if ( num >= 0 ) { sp += num; qp++;} else { sn += num; qn++; } } // for printf("\nA soma dos numeros positivos e igual a %d",sp); printf("\nA quantidade de termos positivos e igual a %d",qp); printf("\n\nA soma dos numeros negativos e igual a %d",sn); printf("\nA quantidade de termos negativos e igual a %d",qn); printf(MSG6); printf(MSG7); fflush(stdin); // esvaziando o buffer de entrada associado ao teclado ch = getchar(); if ( (ch == 's') || (ch == 'S') ) continua = 1; else continua = 0; } while ( continua ); // do-while mais externo printf("\n\n\n"); system("Pause"); return(0); }

53a838c24a9a3f22e5f7a567ef931dd550cadc1b

de8c0ea84980b6d9bb6e3e23b87e6066a65f4995

/3pp/linux/arch/parisc/math-emu/hppa.h

b25b266c998694d6b7e17fc46700adb448d715cd

permissive

eerimoq/monolinux-example-project

7cc19c6fc179a6d1fd3ec60f383f906b727e6715

57c4c2928b11cc04db59fb5ced962762099a9895

refs/heads/master

MIT

C

UTF-8

C

h

/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Linux/PA-RISC Project (http://www.parisc-linux.org/) * * Floating-point emulation code * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <[email protected]> */ #ifdef __NO_PA_HDRS PA header file -- do not include this header file for non-PA builds. #endif /* amount is assumed to be a constant between 0 and 32 (non-inclusive) */ #define Shiftdouble(left,right,amount,dest) \ /* int left, right, amount, dest; */ \ dest = ((left) << (32-(amount))) | ((unsigned int)(right) >> (amount)) /* amount must be less than 32 */ #define Variableshiftdouble(left,right,amount,dest) \ /* unsigned int left, right; int amount, dest; */ \ if (amount == 0) dest = right; \ else dest = ((((unsigned) left)&0x7fffffff) << (32-(amount))) | \ ((unsigned) right >> (amount)) /* amount must be between 0 and 32 (non-inclusive) */ #define Variable_shift_double(left,right,amount,dest) \ /* unsigned int left, right; int amount, dest; */ \ dest = (left << (32-(amount))) | ((unsigned) right >> (amount))

5ceeedf9e8826e33d3db910dbdf8a27b52d31919

2eb97a860d8604484a3835fe13a9e2390b6f0046

/os/drivers/wireless/realtek/rtk/include/ieee80211.h

1428b30cd12b8ce16a57b34778239e31ebdce1f9

permissive

glb1013/TizenRT

031453835e0dc81edbf5af391622a9ea3b1d9674

3497c0f768ce102eaad055894011422853129c44

refs/heads/master

Apache-2.0

UTF-8

C

h

/****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA * * ******************************************************************************/ #ifndef __IEEE80211_H #define __IEEE80211_H #ifndef CONFIG_RTL8711FW // #include <drv_types.h> #if defined PLATFORM_OS_XP #include <ntstrsafe.h> #endif #if defined PLATFORM_LINUX #include <linux/wireless.h> #endif #else #include <list.h> #endif #define MGMT_QUEUE_NUM 5 #define ETH_ALEN 6 #define ETH_TYPE_LEN 2 #define PAYLOAD_TYPE_LEN 1 #ifdef CONFIG_AP_MODE #define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) /* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ enum { RTL871X_HOSTAPD_FLUSH = 1, RTL871X_HOSTAPD_ADD_STA = 2, RTL871X_HOSTAPD_REMOVE_STA = 3, RTL871X_HOSTAPD_GET_INFO_STA = 4, /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */ RTL871X_HOSTAPD_GET_WPAIE_STA = 5, RTL871X_SET_ENCRYPTION = 6, RTL871X_GET_ENCRYPTION = 7, RTL871X_HOSTAPD_SET_FLAGS_STA = 8, RTL871X_HOSTAPD_GET_RID = 9, RTL871X_HOSTAPD_SET_RID = 10, RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11, RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12, RTL871X_HOSTAPD_MLME = 13, RTL871X_HOSTAPD_SCAN_REQ = 14, RTL871X_HOSTAPD_STA_CLEAR_STATS = 15, RTL871X_HOSTAPD_SET_BEACON = 16, RTL871X_HOSTAPD_SET_WPS_BEACON = 17, RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18, RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19, RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20, RTL871X_HOSTAPD_SET_MACADDR_ACL = 21, RTL871X_HOSTAPD_ACL_ADD_STA = 22, RTL871X_HOSTAPD_ACL_REMOVE_STA = 23, }; /* STA flags */ #define WLAN_STA_AUTH BIT(0) #define WLAN_STA_ASSOC BIT(1) #define WLAN_STA_PS BIT(2) #define WLAN_STA_TIM BIT(3) #define WLAN_STA_PERM BIT(4) #define WLAN_STA_AUTHORIZED BIT(5) #define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ #define WLAN_STA_SHORT_PREAMBLE BIT(7) #define WLAN_STA_PREAUTH BIT(8) #define WLAN_STA_WME BIT(9) #define WLAN_STA_MFP BIT(10) #define WLAN_STA_HT BIT(11) #define WLAN_STA_WPS BIT(12) #define WLAN_STA_MAYBE_WPS BIT(13) #define WLAN_STA_NONERP BIT(31) #endif #define IEEE_CMD_SET_WPA_PARAM 1 #define IEEE_CMD_SET_WPA_IE 2 #define IEEE_CMD_SET_ENCRYPTION 3 #define IEEE_CMD_MLME 4 #define IEEE_PARAM_WPA_ENABLED 1 #define IEEE_PARAM_TKIP_COUNTERMEASURES 2 #define IEEE_PARAM_DROP_UNENCRYPTED 3 #define IEEE_PARAM_PRIVACY_INVOKED 4 #define IEEE_PARAM_AUTH_ALGS 5 #define IEEE_PARAM_IEEE_802_1X 6 #define IEEE_PARAM_WPAX_SELECT 7 #define AUTH_ALG_OPEN_SYSTEM 0x1 #define AUTH_ALG_SHARED_KEY 0x2 #define AUTH_ALG_LEAP 0x00000004 #define IEEE_MLME_STA_DEAUTH 1 #define IEEE_MLME_STA_DISASSOC 2 #define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 #define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 #define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 #define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 #define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 #define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 #define IEEE_CRYPT_ALG_NAME_LEN 16 #define WPA_CIPHER_NONE BIT(0) #define WPA_CIPHER_WEP40 BIT(1) #define WPA_CIPHER_WEP104 BIT(2) #define WPA_CIPHER_TKIP BIT(3) #define WPA_CIPHER_CCMP BIT(4) #define WPA_SELECTOR_LEN 4 //extern u16 RTW_WPA_VERSION ; //extern u8 WPA_AUTH_KEY_MGMT_NONE[]; //extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[]; //extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; //extern u8 WPA_CIPHER_SUITE_WRAP[]; #define RSN_HEADER_LEN 4 #define RSN_SELECTOR_LEN 4 //tern u8 RSN_CIPHER_SUITE_WRAP[]; typedef enum _RATEID_IDX_ { RATEID_IDX_BGN_40M_2SS = 0, RATEID_IDX_BGN_40M_1SS = 1, RATEID_IDX_BGN_20M_2SS_BN = 2, RATEID_IDX_BGN_20M_1SS_BN = 3, RATEID_IDX_GN_N2SS = 4, RATEID_IDX_GN_N1SS = 5, RATEID_IDX_BG = 6, RATEID_IDX_G = 7, RATEID_IDX_B = 8, RATEID_IDX_VHT_2SS = 9, RATEID_IDX_VHT_1SS = 10, } RATEID_IDX, *PRATEID_IDX; enum NETWORK_TYPE { WIRELESS_INVALID = 0, //Sub-Element WIRELESS_11B = BIT(0), // tx: cck only , rx: cck only, hw: cck WIRELESS_11G = BIT(1), // tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only WIRELESS_AUTO = BIT(5), WIRELESS_11AC = BIT(6), //Combination WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), // tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck WIRELESS_11_24AC = (WIRELESS_11G | WIRELESS_11AC), WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC), /* Type for registry default wireless mode */ WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), WIRELESS_MODE_24G = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), WIRELESS_MODE_5G = (WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC), WIRELESS_MODE_MAX = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N | WIRELESS_11AC), }; #define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N) #define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N) #define IsLegacyOnly(NetType) ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A))) #define IsSupported24G(NetType) ((NetType)&SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) #define IsSupported5G(NetType) ((NetType)&SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) #define IsEnableHWCCK(NetType) IsSupported24G(NetType) #define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) #define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) #define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) #define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType) #define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) #define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE) #define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE) #define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE) typedef struct ieee_param { u32 cmd; u8 sta_addr[ETH_ALEN]; union { struct { u8 name; u32 value; } wpa_param; struct { u32 len; u8 reserved[32]; #ifdef __CC_ARM u8 data[1]; #else u8 data[0]; #endif } wpa_ie; struct { int command; int reason_code; } mlme; struct { u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; u8 set_tx; u32 err; u8 idx; u8 seq[8]; /* sequence counter (set: RX, get: TX) */ u16 key_len; #ifdef __CC_ARM u8 key[1]; #else u8 key[0]; #endif } crypt; #ifdef CONFIG_AP_MODE struct { u16 aid; u16 capability; int flags; u8 tx_supp_rates[16]; struct rtw_ieee80211_ht_cap ht_cap; } add_sta; struct { u8 reserved[2]; //for set max_num_sta #ifdef __CC_ARM u8 buf[1]; #else u8 buf[0]; #endif } bcn_ie; #endif } u; } ieee_param; //TODO #if 0 #ifdef CONFIG_AP_MODE typedef struct ieee_param_ex { u32 cmd; u8 sta_addr[ETH_ALEN]; u8 data[0]; }ieee_param_ex; struct sta_data{ u16 aid; u16 capability; int flags; u32 sta_set; u8 tx_supp_rates[16]; u32 tx_supp_rates_len; struct rtw_ieee80211_ht_cap ht_cap; u64 rx_pkts; u64 rx_bytes; u64 rx_drops; u64 tx_pkts; u64 tx_bytes; u64 tx_drops; }; #endif #if WIRELESS_EXT < 17 #define IW_QUAL_QUAL_INVALID 0x10 #define IW_QUAL_LEVEL_INVALID 0x20 #define IW_QUAL_NOISE_INVALID 0x40 #define IW_QUAL_QUAL_UPDATED 0x1 #define IW_QUAL_LEVEL_UPDATED 0x2 #define IW_QUAL_NOISE_UPDATED 0x4 #endif #define IEEE80211_DATA_LEN 2304 /* Maximum size for the MA-UNITDATA primitive, 802.11 standard section 6.2.1.1.2. The figure in section 7.1.2 suggests a body size of up to 2312 bytes is allowed, which is a bit confusing, I suspect this represents the 2304 bytes of real data, plus a possible 8 bytes of WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ #define IEEE80211_HLEN 30 #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) /* this is stolen from ipw2200 driver */ #define IEEE_IBSS_MAC_HASH_SIZE 31 struct ieee_ibss_seq { u8 mac[ETH_ALEN]; u16 seq_num; u16 frag_num; unsigned long packet_time; _list list; }; #endif //#if 0 #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) || defined(PLATFORM_CUSTOMER_RTOS) || defined(PLATFORM_TIZENRT) #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_begin.h" #endif RTW_PACK_STRUCT_BEGIN struct rtw_ieee80211_hdr { u16 frame_ctl; u16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; u16 seq_ctl; u8 addr4[ETH_ALEN]; } RTW_PACK_STRUCT_STRUCT; RTW_PACK_STRUCT_END #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_end.h" #endif #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_begin.h" #endif RTW_PACK_STRUCT_BEGIN struct rtw_ieee80211_hdr_3addr { u16 frame_ctl; u16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; u16 seq_ctl; } RTW_PACK_STRUCT_STRUCT; RTW_PACK_STRUCT_END #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_end.h" #endif #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_begin.h" #endif RTW_PACK_STRUCT_BEGIN struct rtw_ieee80211_hdr_qos { u16 frame_ctl; u16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; u16 seq_ctl; u8 addr4[ETH_ALEN]; u16 qc; } RTW_PACK_STRUCT_STRUCT; RTW_PACK_STRUCT_END #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_end.h" #endif #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_begin.h" #endif RTW_PACK_STRUCT_BEGIN struct rtw_ieee80211_hdr_3addr_qos { u16 frame_ctl; u16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; u16 seq_ctl; u16 qc; } RTW_PACK_STRUCT_STRUCT; RTW_PACK_STRUCT_END #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_end.h" #endif #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_begin.h" #endif RTW_PACK_STRUCT_BEGIN struct eapol { u8 snap[6]; u16 ethertype; u8 version; u8 type; u16 length; } RTW_PACK_STRUCT_STRUCT; RTW_PACK_STRUCT_END #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_end.h" #endif #endif //defined PLATFORM_LINUX/CONFIG_RTL8711FW/PLATFORM_FREEBSD/PLATFORM_ECOSPLATFORM_FREERTOS || defined(PLATFORM_CMSIS_RTOS) //TODO #if 0 #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_begin.h" #endif struct rtw_ieee80211_hdr { u16 frame_ctl; u16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; u16 seq_ctl; u8 addr4[ETH_ALEN]; }; struct rtw_ieee80211_hdr_3addr { u16 frame_ctl; u16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; u16 seq_ctl; }; struct rtw_ieee80211_hdr_qos { struct rtw_ieee80211_hdr wlan_hdr; u16 qc; }; struct rtw_ieee80211_hdr_3addr_qos { struct rtw_ieee80211_hdr_3addr wlan_hdr; u16 qc; }; struct eapol { u8 snap[6]; u16 ethertype; u8 version; u8 type; u16 length; }; #ifdef RTW_PACK_STRUCT_USE_INCLUDES #include "pack_end.h" #endif enum eap_type { EAP_PACKET = 0, EAPOL_START, EAPOL_LOGOFF, EAPOL_KEY, EAPOL_ENCAP_ASF_ALERT }; #endif //#if 0 #define IEEE80211_3ADDR_LEN 24 #define IEEE80211_4ADDR_LEN 30 #define IEEE80211_FCS_LEN 4 #define MIN_FRAG_THRESHOLD 256U #define MAX_FRAG_THRESHOLD 2346U /* Frame control field constants */ #define RTW_IEEE80211_FCTL_VERS 0x0002 #define RTW_IEEE80211_FCTL_FTYPE 0x000c #define RTW_IEEE80211_FCTL_STYPE 0x00f0 #define RTW_IEEE80211_FCTL_TODS 0x0100 #define RTW_IEEE80211_FCTL_FROMDS 0x0200 #define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 #define RTW_IEEE80211_FCTL_RETRY 0x0800 #define RTW_IEEE80211_FCTL_PM 0x1000 #define RTW_IEEE80211_FCTL_MOREDATA 0x2000 #define RTW_IEEE80211_FCTL_WEP 0x4000 #define RTW_IEEE80211_FCTL_ORDER 0x8000 #define RTW_IEEE80211_FTYPE_MGMT 0x0000 #define RTW_IEEE80211_FTYPE_CTL 0x0004 #define RTW_IEEE80211_FTYPE_DATA 0x0008 /* management */ #define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000 #define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010 #define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020 #define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 #define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 #define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 #define RTW_IEEE80211_STYPE_BEACON 0x0080 #define RTW_IEEE80211_STYPE_ATIM 0x0090 #define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 #define RTW_IEEE80211_STYPE_AUTH 0x00B0 #define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 /* control */ #define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 #define RTW_IEEE80211_STYPE_RTS 0x00B0 #define RTW_IEEE80211_STYPE_CTS 0x00C0 #define RTW_IEEE80211_STYPE_ACK 0x00D0 #define RTW_IEEE80211_STYPE_CFEND 0x00E0 #define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 /* data */ #define RTW_IEEE80211_STYPE_DATA 0x0000 #define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 #define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 #define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 #define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 #define RTW_IEEE80211_STYPE_CFACK 0x0050 #define RTW_IEEE80211_STYPE_CFPOLL 0x0060 #define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 #define RTW_IEEE80211_QOS_DATAGRP 0x0080 #define RTW_IEEE80211_QoS_DATAGRP RTW_IEEE80211_QOS_DATAGRP #define RTW_IEEE80211_SCTL_FRAG 0x000F #define RTW_IEEE80211_SCTL_SEQ 0xFFF0 #define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) #define RTW_ERP_INFO_USE_PROTECTION BIT(1) #define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) /* QoS,QOS */ #define NORMAL_ACK 0 #define NO_ACK 1 #define NON_EXPLICIT_ACK 2 #define BLOCK_ACK 3 #ifndef ETH_P_PAE #define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ #endif /* ETH_P_PAE */ #define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ #define ETH_P_ECONET 0x0018 #ifndef ETH_P_80211_RAW #define ETH_P_80211_RAW (ETH_P_ECONET + 1) #endif /* IEEE 802.11 defines */ #define P80211_OUI_LEN 3 #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) || defined(PLATFORM_CUSTOMER_RTOS) || defined(PLATFORM_TIZENRT) RTW_PACK_STRUCT_BEGIN struct ieee80211_snap_hdr { u8 dsap; /* always 0xAA */ u8 ssap; /* always 0xAA */ u8 ctrl; /* always 0x03 */ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ } RTW_PACK_STRUCT_STRUCT; RTW_PACK_STRUCT_END #endif #ifdef PLATFORM_WINDOWS #pragma pack(1) struct ieee80211_snap_hdr { u8 dsap; /* always 0xAA */ u8 ssap; /* always 0xAA */ u8 ctrl; /* always 0x03 */ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ }; #pragma pack() #endif #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) #define WLAN_FC_GET_TYPE(fc) ((fc)&RTW_IEEE80211_FCTL_FTYPE) #define WLAN_FC_GET_STYPE(fc) ((fc)&RTW_IEEE80211_FCTL_STYPE) #define WLAN_QC_GET_TID(qc) ((qc)&0x0f) #define WLAN_GET_SEQ_FRAG(seq) ((seq)&RTW_IEEE80211_SCTL_FRAG) #define WLAN_GET_SEQ_SEQ(seq) ((seq)&RTW_IEEE80211_SCTL_SEQ) /* Authentication algorithms */ #define WLAN_AUTH_OPEN 0 #define WLAN_AUTH_SHARED_KEY 1 #define WLAN_AUTH_CHALLENGE_LEN 128 #define WLAN_CAPABILITY_BSS (1 << 0) #define WLAN_CAPABILITY_IBSS (1 << 1) #define WLAN_CAPABILITY_CF_POLLABLE (1 << 2) #define WLAN_CAPABILITY_CF_POLL_REQUEST (1 << 3) #define WLAN_CAPABILITY_PRIVACY (1 << 4) #define WLAN_CAPABILITY_SHORT_PREAMBLE (1 << 5) #define WLAN_CAPABILITY_PBCC (1 << 6) #define WLAN_CAPABILITY_CHANNEL_AGILITY (1 << 7) #define WLAN_CAPABILITY_SHORT_SLOT (1 << 10) /* Status codes */ #define WLAN_STATUS_SUCCESS 0 #define WLAN_STATUS_UNSPECIFIED_FAILURE 1 #define WLAN_STATUS_CAPS_UNSUPPORTED 10 #define WLAN_STATUS_REASSOC_NO_ASSOC 11 #define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 #define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 #define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 #define WLAN_STATUS_CHALLENGE_FAIL 15 #define WLAN_STATUS_AUTH_TIMEOUT 16 #define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 #define WLAN_STATUS_ASSOC_DENIED_RATES 18 /* 802.11b */ #define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 #define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 #define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 /* Reason codes */ #define WLAN_REASON_UNSPECIFIED 1 #define WLAN_REASON_PREV_AUTH_NOT_VALID 2 #define WLAN_REASON_DEAUTH_LEAVING 3 #define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 #define WLAN_REASON_DISASSOC_AP_BUSY 5 #define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 #define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 #define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 #define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 #define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 /* Information Element IDs */ #define WLAN_EID_SSID 0 #define WLAN_EID_SUPP_RATES 1 #define WLAN_EID_FH_PARAMS 2 #define WLAN_EID_DS_PARAMS 3 #define WLAN_EID_CF_PARAMS 4 #define WLAN_EID_TIM 5 #define WLAN_EID_IBSS_PARAMS 6 #define WLAN_EID_CHALLENGE 16 /* EIDs defined by IEEE 802.11h - START */ #define WLAN_EID_PWR_CONSTRAINT 32 #define WLAN_EID_PWR_CAPABILITY 33 #define WLAN_EID_TPC_REQUEST 34 #define WLAN_EID_TPC_REPORT 35 #define WLAN_EID_SUPPORTED_CHANNELS 36 #define WLAN_EID_CHANNEL_SWITCH 37 #define WLAN_EID_MEASURE_REQUEST 38 #define WLAN_EID_MEASURE_REPORT 39 #define WLAN_EID_QUITE 40 #define WLAN_EID_IBSS_DFS 41 /* EIDs defined by IEEE 802.11h - END */ #define WLAN_EID_ERP_INFO 42 #define WLAN_EID_HT_CAP 45 #define WLAN_EID_RSN 48 #define WLAN_EID_EXT_SUPP_RATES 50 #define WLAN_EID_MOBILITY_DOMAIN 54 #define WLAN_EID_FAST_BSS_TRANSITION 55 #define WLAN_EID_TIMEOUT_INTERVAL 56 #define WLAN_EID_RIC_DATA 57 #define WLAN_EID_HT_OPERATION 61 #define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62 #define WLAN_EID_20_40_BSS_COEXISTENCE 72 #define WLAN_EID_20_40_BSS_INTOLERANT 73 #define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 #define WLAN_EID_MMIE 76 #define WLAN_EID_VHT_CAPABILITY 191 #define WLAN_EID_VHT_OPERATION 192 #define WLAN_EID_VHT_OPERATING_MODE_NOTIFICATION 199 #define WLAN_EID_VENDOR_SPECIFIC 221 #define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) #define IEEE80211_MGMT_HDR_LEN 24 #define IEEE80211_DATA_HDR3_LEN 24 #define IEEE80211_DATA_HDR4_LEN 30 #define IEEE80211_STATMASK_SIGNAL (1 << 0) #define IEEE80211_STATMASK_RSSI (1 << 1) #define IEEE80211_STATMASK_NOISE (1 << 2) #define IEEE80211_STATMASK_RATE (1 << 3) #define IEEE80211_STATMASK_WEMASK 0x7 #define IEEE80211_CCK_MODULATION (1 << 0) #define IEEE80211_OFDM_MODULATION (1 << 1) #define IEEE80211_24GHZ_BAND (1 << 0) #define IEEE80211_52GHZ_BAND (1 << 1) #define IEEE80211_CCK_RATE_LEN 4 #define IEEE80211_NUM_OFDM_RATESLEN 8 #define IEEE80211_CCK_RATE_1MB 0x02 #define IEEE80211_CCK_RATE_2MB 0x04 #define IEEE80211_CCK_RATE_5MB 0x0B #define IEEE80211_CCK_RATE_11MB 0x16 #define IEEE80211_OFDM_RATE_LEN 8 #define IEEE80211_OFDM_RATE_6MB 0x0C #define IEEE80211_OFDM_RATE_9MB 0x12 #define IEEE80211_OFDM_RATE_12MB 0x18 #define IEEE80211_OFDM_RATE_18MB 0x24 #define IEEE80211_OFDM_RATE_24MB 0x30 #define IEEE80211_OFDM_RATE_36MB 0x48 #define IEEE80211_OFDM_RATE_48MB 0x60 #define IEEE80211_OFDM_RATE_54MB 0x6C #define IEEE80211_BASIC_RATE_MASK 0x80 #define IEEE80211_CCK_RATE_1MB_MASK (1 << 0) #define IEEE80211_CCK_RATE_2MB_MASK (1 << 1) #define IEEE80211_CCK_RATE_5MB_MASK (1 << 2) #define IEEE80211_CCK_RATE_11MB_MASK (1 << 3) #define IEEE80211_OFDM_RATE_6MB_MASK (1 << 4) #define IEEE80211_OFDM_RATE_9MB_MASK (1 << 5) #define IEEE80211_OFDM_RATE_12MB_MASK (1 << 6) #define IEEE80211_OFDM_RATE_18MB_MASK (1 << 7) #define IEEE80211_OFDM_RATE_24MB_MASK (1 << 8) #define IEEE80211_OFDM_RATE_36MB_MASK (1 << 9) #define IEEE80211_OFDM_RATE_48MB_MASK (1 << 10) #define IEEE80211_OFDM_RATE_54MB_MASK (1 << 11) #define IEEE80211_CCK_RATES_MASK 0x0000000F #define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ IEEE80211_CCK_RATE_2MB_MASK) #define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ IEEE80211_CCK_RATE_5MB_MASK | \ IEEE80211_CCK_RATE_11MB_MASK) #define IEEE80211_OFDM_RATES_MASK 0x00000FF0 #define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ IEEE80211_OFDM_RATE_12MB_MASK | \ IEEE80211_OFDM_RATE_24MB_MASK) #define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ IEEE80211_OFDM_RATE_9MB_MASK | \ IEEE80211_OFDM_RATE_18MB_MASK | \ IEEE80211_OFDM_RATE_36MB_MASK | \ IEEE80211_OFDM_RATE_48MB_MASK | \ IEEE80211_OFDM_RATE_54MB_MASK) #define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ IEEE80211_CCK_DEFAULT_RATES_MASK) #define IEEE80211_NUM_OFDM_RATES 8 #define IEEE80211_NUM_CCK_RATES 4 #define IEEE80211_OFDM_SHIFT_MASK_A 4 /* BIT 7 HT Rate*/ enum MGN_RATE { MGN_1M = 0x02, MGN_2M = 0x04, MGN_5_5M = 0x0B, MGN_6M = 0x0C, MGN_9M = 0x12, MGN_11M = 0x16, MGN_12M = 0x18, MGN_18M = 0x24, MGN_24M = 0x30, MGN_36M = 0x48, MGN_48M = 0x60, MGN_54M = 0x6C, MGN_MCS32 = 0x7F, MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31, MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4, MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9, MGN_UNKNOWN }; typedef enum _RATR_TABLE_MODE { RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */ RATR_INX_WIRELESS_NG = 1, /* GN or N */ RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */ RATR_INX_WIRELESS_N = 3, RATR_INX_WIRELESS_GB = 4, RATR_INX_WIRELESS_G = 5, RATR_INX_WIRELESS_B = 6, RATR_INX_WIRELESS_MC = 7, RATR_INX_WIRELESS_AC_N = 8, } RATR_TABLE_MODE, *PRATR_TABLE_MODE; #define MGN_MCS0_SG 0xc0 #define MGN_MCS1_SG 0xc1 #define MGN_MCS2_SG 0xc2 #define MGN_MCS3_SG 0xc3 #define MGN_MCS4_SG 0xc4 #define MGN_MCS5_SG 0xc5 #define MGN_MCS6_SG 0xc6 #define MGN_MCS7_SG 0xc7 #define MGN_MCS8_SG 0xc8 #define MGN_MCS9_SG 0xc9 #define MGN_MCS10_SG 0xca #define MGN_MCS11_SG 0xcb #define MGN_MCS12_SG 0xcc #define MGN_MCS13_SG 0xcd #define MGN_MCS14_SG 0xce #define MGN_MCS15_SG 0xcf #define IS_HT_RATE(_rate) (((_rate)&0x80) ? _TRUE : _FALSE) #define IS_CCK_RATE(_rate) (MGN_1M == _rate || _rate == MGN_2M || _rate == MGN_5_5M || _rate == MGN_11M) #define IS_OFDM_RATE(_rate) (MGN_6M <= _rate && _rate <= MGN_54M) /* NOTE: This data is for statistical purposes; not all hardware provides this * information for frames received. Not setting these will not cause * any adverse affects. */ struct ieee80211_rx_stats { //u32 mac_time[2]; s8 rssi; u8 signal; u8 noise; u8 received_channel; u16 rate; /* in 100 kbps */ //u8 control; u8 mask; u8 freq; u16 len; }; /* IEEE 802.11 requires that STA supports concurrent reception of at least * three fragmented frames. This define can be increased to support more * concurrent frames, but it should be noted that each entry can consume about * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ #define IEEE80211_FRAG_CACHE_LEN 4 struct ieee80211_frag_entry { u32 first_frag_time; uint seq; uint last_frag; uint qos; //jackson uint tid; //jackson struct sk_buff *skb; u8 src_addr[ETH_ALEN]; u8 dst_addr[ETH_ALEN]; }; #ifndef PLATFORM_FREEBSD //Baron BSD has already defined struct ieee80211_stats { uint tx_unicast_frames; uint tx_multicast_frames; uint tx_fragments; uint tx_unicast_octets; uint tx_multicast_octets; uint tx_deferred_transmissions; uint tx_single_retry_frames; uint tx_multiple_retry_frames; uint tx_retry_limit_exceeded; uint tx_discards; uint rx_unicast_frames; uint rx_multicast_frames; uint rx_fragments; uint rx_unicast_octets; uint rx_multicast_octets; uint rx_fcs_errors; uint rx_discards_no_buffer; uint tx_discards_wrong_sa; uint rx_discards_undecryptable; uint rx_message_in_msg_fragments; uint rx_message_in_bad_msg_fragments; }; #endif //PLATFORM_FREEBSD struct ieee80211_softmac_stats { uint rx_ass_ok; uint rx_ass_err; uint rx_probe_rq; uint tx_probe_rs; uint tx_beacons; uint rx_auth_rq; uint rx_auth_rs_ok; uint rx_auth_rs_err; uint tx_auth_rq; uint no_auth_rs; uint no_ass_rs; uint tx_ass_rq; uint rx_ass_rq; uint tx_probe_rq; uint reassoc; uint swtxstop; uint swtxawake; }; #define SEC_KEY_1 (1 << 0) #define SEC_KEY_2 (1 << 1) #define SEC_KEY_3 (1 << 2) #define SEC_KEY_4 (1 << 3) #define SEC_ACTIVE_KEY (1 << 4) #define SEC_AUTH_MODE (1 << 5) #define SEC_UNICAST_GROUP (1 << 6) #define SEC_LEVEL (1 << 7) #define SEC_ENABLED (1 << 8) #define SEC_LEVEL_0 0 /* None */ #define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ #define SEC_LEVEL_2 2 /* Level 1 + TKIP */ #define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ #define SEC_LEVEL_3 4 /* Level 2 + CCMP */ #define WEP_KEYS 4 #define WEP_KEY_LEN 13 #ifdef CONFIG_IEEE80211W #define BIP_MAX_KEYID 5 #define BIP_AAD_SIZE 20 #endif /* CONFIG_IEEE80211W */ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) struct ieee80211_security { u16 active_key : 2, enabled : 1, auth_mode : 2, auth_algo : 4, unicast_uses_group : 1; u8 key_sizes[WEP_KEYS]; u8 keys[WEP_KEYS][WEP_KEY_LEN]; u8 level; u16 flags; } __attribute__((packed)); #endif #ifdef PLATFORM_WINDOWS #pragma pack(1) struct ieee80211_security { u16 active_key : 2, enabled : 1, auth_mode : 2, auth_algo : 4, unicast_uses_group : 1; u8 key_sizes[WEP_KEYS]; u8 keys[WEP_KEYS][WEP_KEY_LEN]; u8 level; u16 flags; }; #pragma pack() #endif /* 802.11 data frame from AP ,-------------------------------------------------------------------. Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | |------|------|---------|---------|---------|------|---------|------| Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | | | tion | (BSSID) | | | ence | data | | `-------------------------------------------------------------------' Total: 28-2340 bytes */ struct ieee80211_header_data { u16 frame_ctl; u16 duration_id; u8 addr1[6]; u8 addr2[6]; u8 addr3[6]; u16 seq_ctrl; }; #define BEACON_PROBE_SSID_ID_POSITION 12 /* Management Frame Information Element Types */ #define MFIE_TYPE_SSID 0 #define MFIE_TYPE_RATES 1 #define MFIE_TYPE_FH_SET 2 #define MFIE_TYPE_DS_SET 3 #define MFIE_TYPE_CF_SET 4 #define MFIE_TYPE_TIM 5 #define MFIE_TYPE_IBSS_SET 6 #define MFIE_TYPE_CHALLENGE 16 #define MFIE_TYPE_ERP 42 #define MFIE_TYPE_RSN 48 #define MFIE_TYPE_RATES_EX 50 #define MFIE_TYPE_GENERIC 221 #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) struct ieee80211_info_element_hdr { u8 id; u8 len; } __attribute__((packed)); struct ieee80211_info_element { u8 id; u8 len; u8 data[0]; } __attribute__((packed)); #endif #ifdef PLATFORM_WINDOWS #pragma pack(1) struct ieee80211_info_element_hdr { u8 id; u8 len; }; struct ieee80211_info_element { u8 id; u8 len; u8 data[0]; }; #pragma pack() #endif /* * These are the data types that can make up management packets * u16 auth_algorithm; u16 auth_sequence; u16 beacon_interval; u16 capability; u8 current_ap[ETH_ALEN]; u16 listen_interval; struct { u16 association_id:14, reserved:2; } __attribute__ ((packed)); u32 time_stamp[2]; u16 reason; u16 status; */ #define IEEE80211_DEFAULT_TX_ESSID "Penguin" #define IEEE80211_DEFAULT_BASIC_RATE 10 #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) struct ieee80211_authentication { struct ieee80211_header_data header; u16 algorithm; u16 transaction; u16 status; //struct ieee80211_info_element_hdr info_element; } __attribute__((packed)); struct ieee80211_probe_response { struct ieee80211_header_data header; u32 time_stamp[2]; u16 beacon_interval; u16 capability; struct ieee80211_info_element info_element; } __attribute__((packed)); struct ieee80211_probe_request { struct ieee80211_header_data header; /*struct ieee80211_info_element info_element;*/ } __attribute__((packed)); struct ieee80211_assoc_request_frame { struct rtw_ieee80211_hdr_3addr header; u16 capability; u16 listen_interval; //u8 current_ap[ETH_ALEN]; struct ieee80211_info_element_hdr info_element; } __attribute__((packed)); struct ieee80211_assoc_response_frame { struct rtw_ieee80211_hdr_3addr header; u16 capability; u16 status; u16 aid; // struct ieee80211_info_element info_element; /* supported rates */ } __attribute__((packed)); #endif #ifdef PLATFORM_WINDOWS #pragma pack(1) struct ieee80211_authentication { struct ieee80211_header_data header; u16 algorithm; u16 transaction; u16 status; //struct ieee80211_info_element_hdr info_element; }; struct ieee80211_probe_response { struct ieee80211_header_data header; u32 time_stamp[2]; u16 beacon_interval; u16 capability; struct ieee80211_info_element info_element; }; struct ieee80211_probe_request { struct ieee80211_header_data header; /*struct ieee80211_info_element info_element;*/ }; struct ieee80211_assoc_request_frame { struct rtw_ieee80211_hdr_3addr header; u16 capability; u16 listen_interval; //u8 current_ap[ETH_ALEN]; struct ieee80211_info_element_hdr info_element; }; struct ieee80211_assoc_response_frame { struct rtw_ieee80211_hdr_3addr header; u16 capability; u16 status; u16 aid; // struct ieee80211_info_element info_element; /* supported rates */ }; #pragma pack() #endif /* SWEEP TABLE ENTRIES NUMBER*/ #define MAX_SWEEP_TAB_ENTRIES 42 #define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 /* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs * only use 8, and then use extended rates for the remaining supported * rates. Other APs, however, stick all of their supported rates on the * main rates information element... */ #define MAX_RATES_LENGTH ((u8)12) #define MAX_RATES_EX_LENGTH ((u8)16) #define MAX_NETWORK_COUNT 128 #define MAX_CHANNEL_NUMBER 161 #define IEEE80211_SOFTMAC_SCAN_TIME 400 //(HZ / 2) #define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) #define CRC_LENGTH 4U #define MAX_WPA_IE_LEN (256) #define MAX_WPS_IE_LEN (512) #define MAX_P2P_IE_LEN (256) #define MAX_WFD_IE_LEN (128) #define NETWORK_EMPTY_ESSID (1 << 0) #define NETWORK_HAS_OFDM (1 << 1) #define NETWORK_HAS_CCK (1 << 2) #define IEEE80211_DTIM_MBCAST 4 #define IEEE80211_DTIM_UCAST 2 #define IEEE80211_DTIM_VALID 1 #define IEEE80211_DTIM_INVALID 0 #define IEEE80211_PS_DISABLED 0 #define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST #define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST #define IW_ESSID_MAX_SIZE 32 #define IW_PASSPHRASE_MAX_SIZE 64 #if 0 struct ieee80211_network { /* These entries are used to identify a unique network */ u8 bssid[ETH_ALEN]; u8 channel; /* Ensure null-terminated for any debug msgs */ u8 ssid[IW_ESSID_MAX_SIZE + 1]; u8 ssid_len; u8 rssi; //relative signal strength u8 sq; //signal quality /* These are network statistics */ //struct ieee80211_rx_stats stats; u16 capability; u16 aid; u8 rates[MAX_RATES_LENGTH]; u8 rates_len; u8 rates_ex[MAX_RATES_EX_LENGTH]; u8 rates_ex_len; u8 edca_parmsets[18]; u8 mode; u8 flags; u8 time_stamp[8]; u16 beacon_interval; u16 listen_interval; u16 atim_window; u8 wpa_ie[MAX_WPA_IE_LEN]; size_t wpa_ie_len; u8 rsn_ie[MAX_WPA_IE_LEN]; size_t rsn_ie_len; u8 country[6]; u8 dtim_period; u8 dtim_data; u8 power_constraint; u8 qosinfo; u8 qbssload[5]; u8 network_type; int join_res; unsigned long last_scanned; }; #endif /* join_res: -1: authentication fail -2: association fail > 0: TID */ #ifndef PLATFORM_FREEBSD //Baron BSD has already defined enum ieee80211_state { /* the card is not linked at all */ IEEE80211_NOLINK = 0, /* IEEE80211_ASSOCIATING* are for BSS client mode * the driver shall not perform RX filtering unless * the state is LINKED. * The driver shall just check for the state LINKED and * defaults to NOLINK for ALL the other states (including * LINKED_SCANNING) */ /* the association procedure will start (wq scheduling)*/ IEEE80211_ASSOCIATING, IEEE80211_ASSOCIATING_RETRY, /* the association procedure is sending AUTH request*/ IEEE80211_ASSOCIATING_AUTHENTICATING, /* the association procedure has successfully authentcated * and is sending association request */ IEEE80211_ASSOCIATING_AUTHENTICATED, /* the link is ok. the card associated to a BSS or linked * to a ibss cell or acting as an AP and creating the bss */ IEEE80211_LINKED, /* same as LINKED, but the driver shall apply RX filter * rules as we are in NO_LINK mode. As the card is still * logically linked, but it is doing a syncro site survey * then it will be back to LINKED state. */ IEEE80211_LINKED_SCANNING, }; #endif //PLATFORM_FREEBSD #define DEFAULT_MAX_SCAN_AGE (15 * HZ) #define DEFAULT_FTS 2346 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" #define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] #if defined(PLATFORM_FREEBSD) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CUSTOMER_RTOS) || defined(PLATFORM_TIZENRT) //Baron change func to macro #define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff)) #define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \ (((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && \ (((Addr[4]) & 0xff) == 0xff) && \ (((Addr[5]) & 0xff) == 0xff)) #else #if 0 extern __inline int is_multicast_mac_addr(const u8 *addr) { return ((addr[0] != 0xff) && (0x01 & addr[0])); } extern __inline int is_broadcast_mac_addr(const u8 *addr) { return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); } #endif #endif // PLATFORM_FREEBSD || PLATFORM_FREERTOS #define CFG_IEEE80211_RESERVE_FCS (1 << 0) #define CFG_IEEE80211_COMPUTE_FCS (1 << 1) #define MAXTID 16 #define IEEE_A (1 << 0) #define IEEE_B (1 << 1) #define IEEE_G (1 << 2) #define IEEE_MODE_MASK (IEEE_A | IEEE_B | IEEE_G) //Baron move to ieee80211.c int ieee80211_is_empty_essid(const char *essid, int essid_len); int ieee80211_get_hdrlen(u16 fc); #if 0 /* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */ #define WLAN_ACTION_SPECTRUM_MGMT 0 #define WLAN_ACTION_QOS 1 #define WLAN_ACTION_DLS 2 #define WLAN_ACTION_BLOCK_ACK 3 #define WLAN_ACTION_RADIO_MEASUREMENT 5 #define WLAN_ACTION_FT 6 #define WLAN_ACTION_SA_QUERY 8 #define WLAN_ACTION_WMM 17 #endif /* Action category code */ enum rtw_ieee80211_category { RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, RTW_WLAN_CATEGORY_QOS = 1, RTW_WLAN_CATEGORY_DLS = 2, RTW_WLAN_CATEGORY_BACK = 3, RTW_WLAN_CATEGORY_PUBLIC = 4, //IEEE 802.11 public action frames RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, RTW_WLAN_CATEGORY_FT = 6, RTW_WLAN_CATEGORY_HT = 7, RTW_WLAN_CATEGORY_SA_QUERY = 8, RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */ RTW_WLAN_CATEGORY_TDLS = 12, RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, /* add for CONFIG_IEEE80211W, none 11w also can use */ RTW_WLAN_CATEGORY_WMM = 17, RTW_WLAN_CATEGORY_P2P = 0x7f, //P2P action frames }; /* SPECTRUM_MGMT action code */ enum rtw_ieee80211_spectrum_mgmt_actioncode { RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1, RTW_WLAN_ACTION_SPCT_TPC_REQ = 2, RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3, RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4, RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, }; enum _PUBLIC_ACTION { ACT_PUBLIC_BSSCOEXIST = 0, // 20/40 BSS Coexistence ACT_PUBLIC_DSE_ENABLE = 1, ACT_PUBLIC_DSE_DEENABLE = 2, ACT_PUBLIC_DSE_REG_LOCATION = 3, ACT_PUBLIC_EXT_CHL_SWITCH = 4, ACT_PUBLIC_DSE_MSR_REQ = 5, ACT_PUBLIC_DSE_MSR_RPRT = 6, ACT_PUBLIC_MP = 7, // Measurement Pilot ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, ACT_PUBLIC_VENDOR = 9, // for WIFI_DIRECT ACT_PUBLIC_GAS_INITIAL_REQ = 10, ACT_PUBLIC_GAS_INITIAL_RSP = 11, ACT_PUBLIC_GAS_COMEBACK_REQ = 12, ACT_PUBLIC_GAS_COMEBACK_RSP = 13, ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, ACT_PUBLIC_LOCATION_TRACK = 15, ACT_PUBLIC_MAX }; #ifdef CONFIG_TDLS enum TDLS_ACTION_FIELD { TDLS_SETUP_REQUEST = 0, TDLS_SETUP_RESPONSE = 1, TDLS_SETUP_CONFIRM = 2, TDLS_TEARDOWN = 3, TDLS_PEER_TRAFFIC_INDICATION = 4, TDLS_CHANNEL_SWITCH_REQUEST = 5, TDLS_CHANNEL_SWITCH_RESPONSE = 6, TDLS_PEER_PSM_REQUEST = 7, TDLS_PEER_PSM_RESPONSE = 8, TDLS_PEER_TRAFFIC_RESPONSE = 9, TDLS_DISCOVERY_REQUEST = 10, TDLS_DISCOVERY_RESPONSE = 14, //it's used in public action frame }; #define TUNNELED_PROBE_REQ 15 #define TUNNELED_PROBE_RSP 16 #endif //CONFIG_TDLS /* BACK action code */ enum rtw_ieee80211_back_actioncode { RTW_WLAN_ACTION_ADDBA_REQ = 0, RTW_WLAN_ACTION_ADDBA_RESP = 1, RTW_WLAN_ACTION_DELBA = 2, }; enum rtw_ieee80211_spec_mgnt_actioncode { RTW_WLAN_ACTION_CSA = 4, RTW_WLAN_ACTION_EXTENDED_CSA = 5, }; /* HT features action code */ enum rtw_ieee80211_ht_actioncode { RTW_WLAN_ACTION_NOTIFY_CH_WIDTH = 0, RTW_WLAN_ACTION_SM_PS = 1, RTW_WLAN_ACTION_PSPM = 2, RTW_WLAN_ACTION_PCO_PHASE = 3, RTW_WLAN_ACTION_MIMO_CSI_MX = 4, RTW_WLAN_ACTION_MIMO_NONCP_BF = 5, RTW_WLAN_ACTION_MIMP_CP_BF = 6, RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7, RTW_WLAN_ACTION_HI_INFO_EXCHG = 8, }; /* BACK (block-ack) parties */ enum rtw_ieee80211_back_parties { RTW_WLAN_BACK_RECIPIENT = 0, RTW_WLAN_BACK_INITIATOR = 1, RTW_WLAN_BACK_TIMER = 2, }; enum secondary_ch_offset { RTW_WLAN_SCN = 0, /* no secondary channel */ RTW_WLAN_SCA = 1, /* secondary channel above */ RTW_WLAN_SCB = 3, /* secondary channel below */ }; #define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) \ * 00:50:F2 */ #ifndef PLATFORM_FREEBSD //Baron BSD has defined #define WME_OUI_TYPE 2 #endif //PLATFORM_FREEBSD #define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 #define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 #define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 #define WME_VERSION 1 #define WME_ACTION_CODE_SETUP_REQUEST 0 #define WME_ACTION_CODE_SETUP_RESPONSE 1 #define WME_ACTION_CODE_TEARDOWN 2 #define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0 #define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1 #define WME_SETUP_RESPONSE_STATUS_REFUSED 3 #define WME_TSPEC_DIRECTION_UPLINK 0 #define WME_TSPEC_DIRECTION_DOWNLINK 1 #define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3 #define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ #define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len); u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); void dump_ies(u8 *buf, u32 buf_len); void dump_wps_ie(u8 *ie, u32 ie_len); #ifdef CONFIG_P2P_NEW u8 *rtw_get_p2p_ie(u8 *in_ie, uint in_len, u8 *p2p_ie, uint *p2p_ielen); u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); #endif //CONFIG_P2P #ifdef CONFIG_P2P void dump_p2p_ie(u8 *ie, u32 ie_len); u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); #endif #ifdef CONFIG_WFD int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *attr_content, uint *attr_contentlen); #endif // CONFIG_WFD //struct registry_priv; //int rtw_generate_ie(struct registry_priv *pregistrypriv); void rtw_get_bcn_info(struct wlan_network *pnetwork); void rtw_macaddr_cfg(u8 *mac_addr); u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char *MCS_rate); #endif /* __IEEE80211_H */

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/trunk-nxt/src/rdpartyrobotcdr-3.2.1/lego-temp-test2.c

be61dc1de6e19f8ed4fdbb216e42a26ad41221a9

no_license

cho934/pm-robotix

acc1eaa80069cce297ee52e08961bfdc04110f5a

e88fcfc3d636b428d88797ed612c2461bce58f1b

refs/heads/master

UTF-8

C

c

#pragma config(Sensor, S1, LEGOTMP, sensorI2CCustom) //*!!Code automatically generated by 'ROBOTC' configuration wizard !!*// /** * lego-temp.h provides an API for the Lego Temperature Sensor. This program * demonstrates how to use that API to use the sensor in single-shot mode. * * Changelog: * - 0.1: Initial release * * Credits: * - Big thanks to Sylvain Cacheux for writing the initial drivers. * * License: You may use this code as you wish, provided you give credit where it's due. * * THIS CODE WILL ONLY WORK WITH ROBOTC VERSION 3.55 beta 2 AND HIGHER. * Xander Soldaat (xander_at_botbench.com) * 16 february 2010 * version 0.1 */ #include "drivers/lego-temp.h" // Small function to convert the accuracy level into something humans can read void accuracyToString(tLEGOTMPAccuracy _accuracy, string &text) { strcpy(text, ""); switch (_accuracy) { case A_MIN: text = "A_MIN"; break; case A_MEAN1: text = "A_MEAN1"; break; case A_MEAN2: text = "A_MEAN2"; break; case A_MAX: text = "A_MAX"; break; } } task main() { float temp; tLEGOTMPAccuracy accuracy; string strAcc; nxtDisplayCenteredTextLine(0, "LEGO"); nxtDisplayCenteredBigTextLine(1, "Temp"); nxtDisplayCenteredTextLine(3, "Test 1"); nxtDisplayCenteredTextLine(5, "Connect sensor"); nxtDisplayCenteredTextLine(6, "to S1"); wait1Msec(2000); eraseDisplay(); // Setup the sensor for Single shot mode LEGOTMPsetSingleShot(LEGOTMP); //setting minimum accuracy accuracy = A_MIN; if (!LEGOTMPsetAccuracy(LEGOTMP, accuracy)) { nxtDisplayTextLine(0, "Error setAccuracy"); wait1Msec(5000); StopAllTasks(); } //reads the current accuracy of the sensor if (!LEGOTMPreadAccuracy(LEGOTMP, accuracy)) { nxtDisplayTextLine(0, "Error readAccuracy"); wait1Msec(5000); StopAllTasks(); } accuracyToString(accuracy, strAcc); nxtDisplayTextLine(0, "Accuracy: %s", strAcc); //loop to read temp while (true) { switch(nNxtButtonPressed) { // If the left button is pressed, decrease the accuracy case kLeftButton: switch(accuracy) { case A_MIN: accuracy = A_MAX; break; case A_MEAN1: accuracy = A_MIN; break; case A_MEAN2: accuracy = A_MEAN1; break; case A_MAX: accuracy = A_MEAN2; break; } if (!LEGOTMPsetAccuracy(LEGOTMP, accuracy)) { nxtDisplayTextLine(0, "Error setAccuracy"); wait1Msec(5000); StopAllTasks(); } accuracyToString(accuracy, strAcc); nxtDisplayTextLine(0, "Accuracy: %s", strAcc); // debounce the button while (nNxtButtonPressed != kNoButton) EndTimeSlice(); break; // If the right button is pressed, increase the accuracy case kRightButton: switch(accuracy) { case A_MIN: accuracy = A_MEAN1; break; case A_MEAN1: accuracy = A_MEAN2; break; case A_MEAN2: accuracy = A_MAX; break; case A_MAX: accuracy = A_MIN; break; } if (!LEGOTMPsetAccuracy(LEGOTMP, accuracy)) { nxtDisplayTextLine(0, "Error setAccuracy"); wait1Msec(5000); StopAllTasks(); } accuracyToString(accuracy, strAcc); nxtDisplayTextLine(0, "Accuracy: %s", strAcc); // debounce the button while (nNxtButtonPressed != kNoButton) EndTimeSlice(); break; } if (!LEGOTMPreadTemp(LEGOTMP, temp)) { eraseDisplay(); nxtDisplayTextLine(0, "Temp reading pb"); wait10Msec(100); StopAllTasks(); } nxtDisplayCenteredBigTextLine(2, "Temp:"); // Depending on the level of accuracy, you need to change the // the formatting of the float, makes it look nicer. switch(accuracy) { case A_MIN: nxtDisplayCenteredBigTextLine(4, "%4.1f", temp); break; case A_MEAN1: nxtDisplayCenteredBigTextLine(4, "%5.2f", temp); break; case A_MEAN2: nxtDisplayCenteredBigTextLine(4, "%6.3f", temp); break; case A_MAX: nxtDisplayCenteredBigTextLine(4, "%7.4f", temp); break; } } }

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/83.C

57366377d767e0049ff0800a148df6c9138b367f

no_license

prakashvsb/GUVI-SET-9

22b98cfc4ac50d4ee51dff22e1124747152d501c

85a7abf14b2ddcd74aae2e874bec661bff5a8eec

refs/heads/master

UTF-8

C

c

#include <stdio.h> int main(void) { int n1,n2,i; char sym; printf("\n enter the two numbers:\n"); for(i=1;i<=4;i++) { scanf("%d %c %d",&n1,&sym,&n2); if(sym=='/') { printf("%d\n",n1/n2); } else { printf("%d\n",n1%n2); } } return 0; }

c493ac26401f1b7ed90482d4e3be63415d2c097d

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/src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x96-acc6.c

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permissive

Pandinosaurus/XNNPACK

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refs/heads/master

NOASSERTION

C

UTF-8

C

c

// Auto-generated file. Do not edit! // Template: src/f16-raddstoreexpminusmax/neonfp16arith-rr2-p2.c.in // Generator: tools/xngen // // Copyright 2022 Google LLC // // This source code is licensed under the BSD-style license found in the // LICENSE file in the root directory of this source tree. #include <assert.h> #include <arm_neon.h> #include <xnnpack/common.h> #include <xnnpack/raddstoreexpminusmax.h> void xnn_f16_raddstoreexpminusmax_ukernel__neonfp16arith_rr2_p2_x96_acc6( size_t batch, const void* input, const void* max, void* output, void* sum, const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS { assert(batch % sizeof(__fp16) == 0); const float16x8_t vi_max = vld1q_dup_f16(max); const float16x8_t vlog2e = vreinterpretq_f16_u16(vld1q_dup_u16(&params->neonfp16arith_rr2_p2.log2e)); const float16x8_t vmagic_bias = vreinterpretq_f16_u16(vld1q_dup_u16(&params->neonfp16arith_rr2_p2.magic_bias)); const float16x8_t vminus_ln2_hi = vreinterpretq_f16_u16(vld1q_dup_u16(&params->neonfp16arith_rr2_p2.minus_ln2_hi)); const float16x8_t vminus_ln2_lo = vreinterpretq_f16_u16(vld1q_dup_u16(&params->neonfp16arith_rr2_p2.minus_ln2_lo)); const float16x8_t vc2 = vreinterpretq_f16_u16(vld1q_dup_u16(&params->neonfp16arith_rr2_p2.c2)); const float16x8_t vc1 = vreinterpretq_f16_u16(vld1q_dup_u16(&params->neonfp16arith_rr2_p2.c1)); const float16x8_t vdenorm_cutoff = vreinterpretq_f16_u16(vld1q_dup_u16(&params->neonfp16arith_rr2_p2.denorm_cutoff)); const __fp16* i = (const __fp16*) input; __fp16* o = (__fp16*) output; float16x8_t vacc0 = vmovq_n_f16(0.0f); float16x8_t vacc1 = vmovq_n_f16(0.0f); float16x8_t vacc2 = vmovq_n_f16(0.0f); float16x8_t vacc3 = vmovq_n_f16(0.0f); float16x8_t vacc4 = vmovq_n_f16(0.0f); float16x8_t vacc5 = vmovq_n_f16(0.0f); for (; batch >= 96 * sizeof(__fp16); batch -= 96 * sizeof(__fp16)) { const float16x8_t vi0 = vld1q_f16(i); i += 8; const float16x8_t vi1 = vld1q_f16(i); i += 8; const float16x8_t vi2 = vld1q_f16(i); i += 8; const float16x8_t vi3 = vld1q_f16(i); i += 8; const float16x8_t vi4 = vld1q_f16(i); i += 8; const float16x8_t vi5 = vld1q_f16(i); i += 8; const float16x8_t vi6 = vld1q_f16(i); i += 8; const float16x8_t vi7 = vld1q_f16(i); i += 8; const float16x8_t vi8 = vld1q_f16(i); i += 8; const float16x8_t vi9 = vld1q_f16(i); i += 8; const float16x8_t viA = vld1q_f16(i); i += 8; const float16x8_t viB = vld1q_f16(i); i += 8; const float16x8_t vx0 = vsubq_f16(vi0, vi_max); const float16x8_t vx1 = vsubq_f16(vi1, vi_max); const float16x8_t vx2 = vsubq_f16(vi2, vi_max); const float16x8_t vx3 = vsubq_f16(vi3, vi_max); const float16x8_t vx4 = vsubq_f16(vi4, vi_max); const float16x8_t vx5 = vsubq_f16(vi5, vi_max); const float16x8_t vx6 = vsubq_f16(vi6, vi_max); const float16x8_t vx7 = vsubq_f16(vi7, vi_max); const float16x8_t vx8 = vsubq_f16(vi8, vi_max); const float16x8_t vx9 = vsubq_f16(vi9, vi_max); const float16x8_t vxA = vsubq_f16(viA, vi_max); const float16x8_t vxB = vsubq_f16(viB, vi_max); float16x8_t vn0 = vfmaq_f16(vmagic_bias, vx0, vlog2e); float16x8_t vn1 = vfmaq_f16(vmagic_bias, vx1, vlog2e); float16x8_t vn2 = vfmaq_f16(vmagic_bias, vx2, vlog2e); float16x8_t vn3 = vfmaq_f16(vmagic_bias, vx3, vlog2e); float16x8_t vn4 = vfmaq_f16(vmagic_bias, vx4, vlog2e); float16x8_t vn5 = vfmaq_f16(vmagic_bias, vx5, vlog2e); float16x8_t vn6 = vfmaq_f16(vmagic_bias, vx6, vlog2e); float16x8_t vn7 = vfmaq_f16(vmagic_bias, vx7, vlog2e); float16x8_t vn8 = vfmaq_f16(vmagic_bias, vx8, vlog2e); float16x8_t vn9 = vfmaq_f16(vmagic_bias, vx9, vlog2e); float16x8_t vnA = vfmaq_f16(vmagic_bias, vxA, vlog2e); float16x8_t vnB = vfmaq_f16(vmagic_bias, vxB, vlog2e); const float16x8_t vs0 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn0), 10)); const float16x8_t vs1 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn1), 10)); const float16x8_t vs2 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn2), 10)); const float16x8_t vs3 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn3), 10)); const float16x8_t vs4 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn4), 10)); const float16x8_t vs5 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn5), 10)); const float16x8_t vs6 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn6), 10)); const float16x8_t vs7 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn7), 10)); const float16x8_t vs8 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn8), 10)); const float16x8_t vs9 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn9), 10)); const float16x8_t vsA = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vnA), 10)); const float16x8_t vsB = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vnB), 10)); vn0 = vsubq_f16(vn0, vmagic_bias); vn1 = vsubq_f16(vn1, vmagic_bias); vn2 = vsubq_f16(vn2, vmagic_bias); vn3 = vsubq_f16(vn3, vmagic_bias); vn4 = vsubq_f16(vn4, vmagic_bias); vn5 = vsubq_f16(vn5, vmagic_bias); vn6 = vsubq_f16(vn6, vmagic_bias); vn7 = vsubq_f16(vn7, vmagic_bias); vn8 = vsubq_f16(vn8, vmagic_bias); vn9 = vsubq_f16(vn9, vmagic_bias); vnA = vsubq_f16(vnA, vmagic_bias); vnB = vsubq_f16(vnB, vmagic_bias); float16x8_t vt0 = vfmaq_f16(vx0, vn0, vminus_ln2_hi); float16x8_t vt1 = vfmaq_f16(vx1, vn1, vminus_ln2_hi); float16x8_t vt2 = vfmaq_f16(vx2, vn2, vminus_ln2_hi); float16x8_t vt3 = vfmaq_f16(vx3, vn3, vminus_ln2_hi); float16x8_t vt4 = vfmaq_f16(vx4, vn4, vminus_ln2_hi); float16x8_t vt5 = vfmaq_f16(vx5, vn5, vminus_ln2_hi); float16x8_t vt6 = vfmaq_f16(vx6, vn6, vminus_ln2_hi); float16x8_t vt7 = vfmaq_f16(vx7, vn7, vminus_ln2_hi); float16x8_t vt8 = vfmaq_f16(vx8, vn8, vminus_ln2_hi); float16x8_t vt9 = vfmaq_f16(vx9, vn9, vminus_ln2_hi); float16x8_t vtA = vfmaq_f16(vxA, vnA, vminus_ln2_hi); float16x8_t vtB = vfmaq_f16(vxB, vnB, vminus_ln2_hi); vt0 = vfmaq_f16(vt0, vn0, vminus_ln2_lo); vt1 = vfmaq_f16(vt1, vn1, vminus_ln2_lo); vt2 = vfmaq_f16(vt2, vn2, vminus_ln2_lo); vt3 = vfmaq_f16(vt3, vn3, vminus_ln2_lo); vt4 = vfmaq_f16(vt4, vn4, vminus_ln2_lo); vt5 = vfmaq_f16(vt5, vn5, vminus_ln2_lo); vt6 = vfmaq_f16(vt6, vn6, vminus_ln2_lo); vt7 = vfmaq_f16(vt7, vn7, vminus_ln2_lo); vt8 = vfmaq_f16(vt8, vn8, vminus_ln2_lo); vt9 = vfmaq_f16(vt9, vn9, vminus_ln2_lo); vtA = vfmaq_f16(vtA, vnA, vminus_ln2_lo); vtB = vfmaq_f16(vtB, vnB, vminus_ln2_lo); const float16x8_t vp0 = vfmaq_f16(vc1, vc2, vt0); const float16x8_t vp1 = vfmaq_f16(vc1, vc2, vt1); const float16x8_t vp2 = vfmaq_f16(vc1, vc2, vt2); const float16x8_t vp3 = vfmaq_f16(vc1, vc2, vt3); const float16x8_t vp4 = vfmaq_f16(vc1, vc2, vt4); const float16x8_t vp5 = vfmaq_f16(vc1, vc2, vt5); const float16x8_t vp6 = vfmaq_f16(vc1, vc2, vt6); const float16x8_t vp7 = vfmaq_f16(vc1, vc2, vt7); const float16x8_t vp8 = vfmaq_f16(vc1, vc2, vt8); const float16x8_t vp9 = vfmaq_f16(vc1, vc2, vt9); const float16x8_t vpA = vfmaq_f16(vc1, vc2, vtA); const float16x8_t vpB = vfmaq_f16(vc1, vc2, vtB); vt0 = vmulq_f16(vt0, vs0); vt1 = vmulq_f16(vt1, vs1); vt2 = vmulq_f16(vt2, vs2); vt3 = vmulq_f16(vt3, vs3); vt4 = vmulq_f16(vt4, vs4); vt5 = vmulq_f16(vt5, vs5); vt6 = vmulq_f16(vt6, vs6); vt7 = vmulq_f16(vt7, vs7); vt8 = vmulq_f16(vt8, vs8); vt9 = vmulq_f16(vt9, vs9); vtA = vmulq_f16(vtA, vsA); vtB = vmulq_f16(vtB, vsB); float16x8_t vf0 = vfmaq_f16(vs0, vp0, vt0); const uint16x8_t vm0 = vcltq_f16(vx0, vdenorm_cutoff); float16x8_t vf1 = vfmaq_f16(vs1, vp1, vt1); const uint16x8_t vm1 = vcltq_f16(vx1, vdenorm_cutoff); float16x8_t vf2 = vfmaq_f16(vs2, vp2, vt2); const uint16x8_t vm2 = vcltq_f16(vx2, vdenorm_cutoff); float16x8_t vf3 = vfmaq_f16(vs3, vp3, vt3); const uint16x8_t vm3 = vcltq_f16(vx3, vdenorm_cutoff); float16x8_t vf4 = vfmaq_f16(vs4, vp4, vt4); const uint16x8_t vm4 = vcltq_f16(vx4, vdenorm_cutoff); float16x8_t vf5 = vfmaq_f16(vs5, vp5, vt5); const uint16x8_t vm5 = vcltq_f16(vx5, vdenorm_cutoff); float16x8_t vf6 = vfmaq_f16(vs6, vp6, vt6); const uint16x8_t vm6 = vcltq_f16(vx6, vdenorm_cutoff); float16x8_t vf7 = vfmaq_f16(vs7, vp7, vt7); const uint16x8_t vm7 = vcltq_f16(vx7, vdenorm_cutoff); float16x8_t vf8 = vfmaq_f16(vs8, vp8, vt8); const uint16x8_t vm8 = vcltq_f16(vx8, vdenorm_cutoff); float16x8_t vf9 = vfmaq_f16(vs9, vp9, vt9); const uint16x8_t vm9 = vcltq_f16(vx9, vdenorm_cutoff); float16x8_t vfA = vfmaq_f16(vsA, vpA, vtA); const uint16x8_t vmA = vcltq_f16(vxA, vdenorm_cutoff); float16x8_t vfB = vfmaq_f16(vsB, vpB, vtB); const uint16x8_t vmB = vcltq_f16(vxB, vdenorm_cutoff); vf0 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf0), vm0)); vf1 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf1), vm1)); vf2 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf2), vm2)); vf3 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf3), vm3)); vf4 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf4), vm4)); vf5 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf5), vm5)); vf6 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf6), vm6)); vf7 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf7), vm7)); vf8 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf8), vm8)); vf9 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf9), vm9)); vfA = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vfA), vmA)); vfB = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vfB), vmB)); vst1q_f16(o, vf0); o += 8; vst1q_f16(o, vf1); o += 8; vst1q_f16(o, vf2); o += 8; vst1q_f16(o, vf3); o += 8; vst1q_f16(o, vf4); o += 8; vst1q_f16(o, vf5); o += 8; vst1q_f16(o, vf6); o += 8; vst1q_f16(o, vf7); o += 8; vst1q_f16(o, vf8); o += 8; vst1q_f16(o, vf9); o += 8; vst1q_f16(o, vfA); o += 8; vst1q_f16(o, vfB); o += 8; vacc0 = vaddq_f16(vacc0, vf0); vacc1 = vaddq_f16(vacc1, vf1); vacc2 = vaddq_f16(vacc2, vf2); vacc3 = vaddq_f16(vacc3, vf3); vacc4 = vaddq_f16(vacc4, vf4); vacc5 = vaddq_f16(vacc5, vf5); vacc0 = vaddq_f16(vacc0, vf6); vacc1 = vaddq_f16(vacc1, vf7); vacc2 = vaddq_f16(vacc2, vf8); vacc3 = vaddq_f16(vacc3, vf9); vacc4 = vaddq_f16(vacc4, vfA); vacc5 = vaddq_f16(vacc5, vfB); } vacc0 = vaddq_f16(vacc0, vacc1); vacc2 = vaddq_f16(vacc2, vacc3); vacc4 = vaddq_f16(vacc4, vacc5); vacc0 = vaddq_f16(vacc0, vacc2); vacc0 = vaddq_f16(vacc0, vacc4); float16x8_t vacc = vacc0; for (; batch >= 8 * sizeof(__fp16); batch -= 8 * sizeof(__fp16)) { const float16x8_t vi = vld1q_f16(i); i += 8; const float16x8_t vx = vsubq_f16(vi, vi_max); float16x8_t vn = vfmaq_f16(vmagic_bias, vx, vlog2e); const float16x8_t vs = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn), 10)); vn = vsubq_f16(vn, vmagic_bias); float16x8_t vt = vfmaq_f16(vx, vn, vminus_ln2_hi); vt = vfmaq_f16(vt, vn, vminus_ln2_lo); const float16x8_t vp = vfmaq_f16(vc1, vc2, vt); vt = vmulq_f16(vt, vs); float16x8_t vf = vfmaq_f16(vs, vp, vt); const uint16x8_t vm = vcltq_f16(vx, vdenorm_cutoff); vf = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf), vm)); vst1q_f16(o, vf); o += 8; vacc = vaddq_f16(vacc, vf); } float16x4_t vacc_lo = vadd_f16(vget_low_f16(vacc), vget_high_f16(vacc)); if (batch != 0) { assert(batch >= 1 * sizeof(__fp16)); assert(batch <= 7 * sizeof(__fp16)); const float16x8_t vi = vld1q_f16(i); const float16x8_t vx = vsubq_f16(vi, vi_max); float16x8_t vn = vfmaq_f16(vmagic_bias, vx, vlog2e); const float16x8_t vs = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn), 10)); vn = vsubq_f16(vn, vmagic_bias); float16x8_t vt = vfmaq_f16(vx, vn, vminus_ln2_hi); vt = vfmaq_f16(vt, vn, vminus_ln2_lo); const float16x8_t vp = vfmaq_f16(vc1, vc2, vt); vt = vmulq_f16(vt, vs); float16x8_t vf = vfmaq_f16(vs, vp, vt); const uint16x8_t vm = vcltq_f16(vx, vdenorm_cutoff); vf = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf), vm)); float16x4_t vf_lo = vget_low_f16(vf); if (batch & (4 * sizeof(__fp16))) { vst1_f16(o, vf_lo); o += 4; vacc_lo = vadd_f16(vacc_lo, vf_lo); vf_lo = vget_high_f16(vf); } if (batch & (2 * sizeof(__fp16))) { vst1_lane_u32((void*) o, vreinterpret_u32_f16(vf_lo), 0); o += 2; vacc_lo = vadd_f16(vacc_lo, vreinterpret_f16_u64(vshl_n_u64(vreinterpret_u64_f16(vf_lo), 32))); vf_lo = vext_f16(vf_lo, vf_lo, 2); } if (batch & (1 * sizeof(__fp16))) { vst1_lane_f16(o, vf_lo, 0); vacc_lo = vadd_f16(vacc_lo, vreinterpret_f16_u64(vshl_n_u64(vreinterpret_u64_f16(vf_lo), 48))); } } vacc_lo = vpadd_f16(vacc_lo, vacc_lo); *((__fp16*) sum) = vget_lane_f16(vacc_lo, 0) + vget_lane_f16(vacc_lo, 1); }

add6f0c240fb263783ef04569fc39d5060c4fd7b

186cce62e4de81ad81ec07c3cf83d1b537dc63a0

/drivers/video/console/vgacon.c

5e2f77f5ebc62e5a5b2e1b40ff94304f84744508

no_license

wangxiaochuang/copy2.6.11.12

99286165df4f11615982e9ce6bfb89a8040dd0a8

c197d83e3e1537a2ff6cff311525a5b2b3502e19

refs/heads/main

UTF-8

C

c

#include <linux/config.h> #include <linux/module.h> #include <linux/types.h> #include <linux/sched.h> #include <linux/fs.h> #include <linux/kernel.h> #include <linux/tty.h> #include <linux/console.h> #include <linux/string.h> #include <linux/kd.h> #include <linux/slab.h> #include <linux/vt_kern.h> #include <linux/selection.h> #include <linux/spinlock.h> #include <linux/ioport.h> #include <linux/init.h> #include <linux/smp_lock.h> #include <video/vga.h> #include <asm/io.h> static DEFINE_SPINLOCK(vga_lock); static int cursor_size_lastfrom; static int cursor_size_lastto; static struct vgastate state; #define BLANK 0x0020 #define CAN_LOAD_EGA_FONTS /* undefine if the user must not do this */ #define CAN_LOAD_PALETTE /* undefine if the user must not do this */ /* You really do _NOT_ want to define this, unless you have buggy * Trident VGA which will resize cursor when moving it between column * 15 & 16. If you define this and your VGA is OK, inverse bug will * appear. */ #undef TRIDENT_GLITCH /* * Interface used by the world */ static const char *vgacon_startup(void); static void vgacon_init(struct vc_data *c, int init); static void vgacon_deinit(struct vc_data *c); static void vgacon_cursor(struct vc_data *c, int mode); static int vgacon_switch(struct vc_data *c); static int vgacon_blank(struct vc_data *c, int blank, int mode_switch); static int vgacon_set_palette(struct vc_data *vc, unsigned char *table); static int vgacon_scrolldelta(struct vc_data *c, int lines); static int vgacon_set_origin(struct vc_data *c); static void vgacon_save_screen(struct vc_data *c); static int vgacon_scroll(struct vc_data *c, int t, int b, int dir, int lines); static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity, u8 blink, u8 underline, u8 reverse); static void vgacon_invert_region(struct vc_data *c, u16 * p, int count); static unsigned long vgacon_uni_pagedir[2]; /* Description of the hardware situation */ static unsigned long vga_vram_base; /* Base of video memory */ static unsigned long vga_vram_end; /* End of video memory */ static u16 vga_video_port_reg; /* Video register select port */ static u16 vga_video_port_val; /* Video register value port */ static unsigned int vga_video_num_columns; /* Number of text columns */ static unsigned int vga_video_num_lines; /* Number of text lines */ static int vga_can_do_color = 0; /* Do we support colors? */ static unsigned int vga_default_font_height;/* Height of default screen font */ static unsigned char vga_video_type; /* Card type */ static unsigned char vga_hardscroll_enabled; static unsigned char vga_hardscroll_user_enable = 1; static unsigned char vga_font_is_default = 1; static int vga_vesa_blanked; static int vga_palette_blanked; static int vga_is_gfx; static int vga_512_chars; static int vga_video_font_height; static int vga_scan_lines; static unsigned int vga_rolled_over = 0; static int __init no_scroll(char *str) { /* * Disabling scrollback is required for the Braillex ib80-piezo * Braille reader made by F.H. Papenmeier (Germany). * Use the "no-scroll" bootflag. */ vga_hardscroll_user_enable = vga_hardscroll_enabled = 0; return 1; } __setup("no-scroll", no_scroll); /* * By replacing the four outb_p with two back to back outw, we can reduce * the window of opportunity to see text mislocated to the RHS of the * console during heavy scrolling activity. However there is the remote * possibility that some pre-dinosaur hardware won't like the back to back * I/O. Since the Xservers get away with it, we should be able to as well. */ static inline void write_vga(unsigned char reg, unsigned int val) { unsigned int v1, v2; unsigned long flags; /* * ddprintk might set the console position from interrupt * handlers, thus the write has to be IRQ-atomic. */ spin_lock_irqsave(&vga_lock, flags); #ifndef SLOW_VGA v1 = reg + (val & 0xff00); v2 = reg + 1 + ((val << 8) & 0xff00); outw(v1, vga_video_port_reg); outw(v2, vga_video_port_reg); #else outb_p(reg, vga_video_port_reg); outb_p(val >> 8, vga_video_port_val); outb_p(reg + 1, vga_video_port_reg); outb_p(val & 0xff, vga_video_port_val); #endif spin_unlock_irqrestore(&vga_lock, flags); } static const char __init *vgacon_startup(void) { const char *display_desc = NULL; u16 saved1, saved2; volatile u16 *p; if (ORIG_VIDEO_ISVGA == VIDEO_TYPE_VLFB) { no_vga: #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; return conswitchp->con_startup(); #else return NULL; #endif } /* VGA16 modes are not handled by VGACON */ if ((ORIG_VIDEO_MODE == 0x0D) || /* 320x200/4 */ (ORIG_VIDEO_MODE == 0x0E) || /* 640x200/4 */ (ORIG_VIDEO_MODE == 0x10) || /* 640x350/4 */ (ORIG_VIDEO_MODE == 0x12) || /* 640x480/4 */ (ORIG_VIDEO_MODE == 0x6A)) /* 800x600/4, 0x6A is very common */ goto no_vga; vga_video_num_lines = ORIG_VIDEO_LINES; vga_video_num_columns = ORIG_VIDEO_COLS; state.vgabase = NULL; if (ORIG_VIDEO_MODE == 7) { mypanic("ORIG_VIDEO_MODE == 7"); } else { /* If not, it is color. */ vga_can_do_color = 1; vga_vram_base = 0xb8000; vga_video_port_reg = VGA_CRT_IC; vga_video_port_val = VGA_CRT_DC; if ((ORIG_VIDEO_EGA_BX & 0xff) != 0x10) { int i; vga_vram_end = 0xc0000; if (!ORIG_VIDEO_ISVGA) { mypanic("ORIG_VIDEO_ISVGA"); } else { static struct resource vga_console_resource = { "vga+", 0x3C0, 0x3DF }; vga_video_type = VIDEO_TYPE_VGAC; display_desc = "VGA+"; request_resource(&ioport_resource, &vga_console_resource); #ifdef VGA_CAN_DO_64KB #error "VGA_CAN_DO_64KB" #endif for (i = 0; i < 16; i++) { inb_p(VGA_IS1_RC); outb_p(i, VGA_ATT_W); outb_p(i, VGA_ATT_W); } outb_p(0x20, VGA_ATT_W); /* * Now set the DAC registers back to their * default values */ for (i = 0; i < 16; i++) { outb_p(color_table[i], VGA_PEL_IW); outb_p(default_red[i], VGA_PEL_D); outb_p(default_grn[i], VGA_PEL_D); outb_p(default_blu[i], VGA_PEL_D); } } } else { mypanic("ORIG_VIDEO_EGA_BX & 0xff = 0x10"); } } vga_vram_base = VGA_MAP_MEM(vga_vram_base); vga_vram_end = VGA_MAP_MEM(vga_vram_end); /* * Find out if there is a graphics card present. * Are there smarter methods around? */ p = (volatile u16 *) vga_vram_base; saved1 = scr_readw(p); saved2 = scr_readw(p + 1); scr_writew(0xAA55, p); scr_writew(0x55AA, p + 1); if (scr_readw(p) != 0xAA55 || scr_readw(p + 1) != 0x55AA) { scr_writew(saved1, p); scr_writew(saved2, p + 1); goto no_vga; } scr_writew(0x55AA, p); scr_writew(0xAA55, p + 1); if (scr_readw(p) != 0x55AA || scr_readw(p + 1) != 0xAA55) { scr_writew(saved1, p); scr_writew(saved2, p + 1); goto no_vga; } scr_writew(saved1, p); scr_writew(saved2, p + 1); if (vga_video_type == VIDEO_TYPE_EGAC || vga_video_type == VIDEO_TYPE_VGAC || vga_video_type == VIDEO_TYPE_EGAM) { vga_hardscroll_enabled = vga_hardscroll_user_enable; vga_default_font_height = ORIG_VIDEO_POINTS; vga_video_font_height = ORIG_VIDEO_POINTS; /* This may be suboptimal but is a safe bet - go with it */ vga_scan_lines = vga_video_font_height * vga_video_num_lines; } return display_desc; } static void vgacon_init(struct vc_data *c, int init) { unsigned long p; /* We cannot be loaded as a module, therefore init is always 1 */ c->vc_can_do_color = vga_can_do_color; c->vc_cols = vga_video_num_columns; c->vc_rows = vga_video_num_lines; c->vc_scan_lines = vga_scan_lines; c->vc_font.height = vga_video_font_height; c->vc_complement_mask = 0x7700; p = *c->vc_uni_pagedir_loc; if (c->vc_uni_pagedir_loc == &c->vc_uni_pagedir || !--c->vc_uni_pagedir_loc[1]) con_free_unimap(c->vc_num); c->vc_uni_pagedir_loc = vgacon_uni_pagedir; vgacon_uni_pagedir[1]++; if (!vgacon_uni_pagedir[0] && p) con_set_default_unimap(c->vc_num); } static inline void vga_set_mem_top(struct vc_data *c) { write_vga(12, (c->vc_visible_origin - vga_vram_base) / 2); } static void vgacon_deinit(struct vc_data *c) { } static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity, u8 blink, u8 underline, u8 reverse) { u8 attr = color; if (vga_can_do_color) { if (underline) attr = (attr & 0xf0) | c->vc_ulcolor; else if (intensity == 0) attr = (attr & 0xf0) | c->vc_halfcolor; } if (reverse) attr = ((attr) & 0x88) | ((((attr) >> 4) | ((attr) << 4)) & 0x77); if (blink) attr ^= 0x80; if (intensity == 2) attr ^= 0x08; if (!vga_can_do_color) { if (underline) attr = (attr & 0xf8) | 0x01; else if (intensity == 0) attr = (attr & 0xf0) | 0x08; } return attr; } static void vgacon_invert_region(struct vc_data *c, u16 * p, int count) { int col = vga_can_do_color; while (count--) { u16 a = scr_readw(p); if (col) a = ((a) & 0x88ff) | (((a) & 0x7000) >> 4) | (((a) & 0x0700) << 4); else a ^= ((a & 0x0700) == 0x0100) ? 0x7000 : 0x7700; scr_writew(a, p++); } } static void vgacon_set_cursor_size(int xpos, int from, int to) { unsigned long flags; int curs, cure; #ifdef TRIDENT_GLITCH if (xpos < 16) from--, to--; #endif if ((from == cursor_size_lastfrom) && (to == cursor_size_lastto)) return; cursor_size_lastfrom = from; cursor_size_lastto = to; spin_lock_irqsave(&vga_lock, flags); outb_p(0x0a, vga_video_port_reg); /* Cursor start */ curs = inb_p(vga_video_port_val); outb_p(0x0b, vga_video_port_reg); /* Cursor end */ cure = inb_p(vga_video_port_val); curs = (curs & 0xc0) | from; cure = (cure & 0xe0) | to; outb_p(0x0a, vga_video_port_reg); /* Cursor start */ outb_p(curs, vga_video_port_val); outb_p(0x0b, vga_video_port_reg); /* Cursor end */ outb_p(cure, vga_video_port_val); spin_unlock_irqrestore(&vga_lock, flags); } static void vgacon_cursor(struct vc_data *c, int mode) { if (c->vc_origin != c->vc_visible_origin) vgacon_scrolldelta(c, 0); switch (mode) { case CM_ERASE: write_vga(14, (vga_vram_end - vga_vram_base - 1) / 2); break; case CM_MOVE: case CM_DRAW: write_vga(14, (c->vc_pos - vga_vram_base) / 2); switch (c->vc_cursor_type & 0x0f) { case CUR_UNDERLINE: vgacon_set_cursor_size(c->vc_x, c->vc_font.height - (c->vc_font.height < 10 ? 2 : 3), c->vc_font.height - (c->vc_font.height < 10 ? 1 : 2)); break; case CUR_TWO_THIRDS: vgacon_set_cursor_size(c->vc_x, c->vc_font.height / 3, c->vc_font.height - (c->vc_font.height < 10 ? 1 : 2)); break; case CUR_LOWER_THIRD: vgacon_set_cursor_size(c->vc_x, (c->vc_font.height * 2) / 3, c->vc_font.height - (c->vc_font.height < 10 ? 1 : 2)); break; case CUR_LOWER_HALF: vgacon_set_cursor_size(c->vc_x, c->vc_font.height / 2, c->vc_font.height - (c->vc_font.height < 10 ? 1 : 2)); break; case CUR_NONE: vgacon_set_cursor_size(c->vc_x, 31, 30); break; default: vgacon_set_cursor_size(c->vc_x, 1, c->vc_font.height); break; } break; } } static int vgacon_switch(struct vc_data *c) { return 0; } static void vga_set_palette(struct vc_data *vc, unsigned char *table) { int i, j; for (i = j = 0; i < 16; i++) { vga_w(state.vgabase, VGA_PEL_IW, table[i]); vga_w(state.vgabase, VGA_PEL_D, vc->vc_palette[j++] >> 2); vga_w(state.vgabase, VGA_PEL_D, vc->vc_palette[j++] >> 2); vga_w(state.vgabase, VGA_PEL_D, vc->vc_palette[j++] >> 2); } } static int vgacon_set_palette(struct vc_data *vc, unsigned char *table) { #ifdef CAN_LOAD_PALETTE if (vga_video_type != VIDEO_TYPE_VGAC || vga_palette_blanked || !CON_IS_VISIBLE(vc)) return -EINVAL; vga_set_palette(vc, table); return 0; #else return -EINVAL; #endif } /* structure holding original VGA register settings */ static struct { unsigned char SeqCtrlIndex; /* Sequencer Index reg. */ unsigned char CrtCtrlIndex; /* CRT-Contr. Index reg. */ unsigned char CrtMiscIO; /* Miscellaneous register */ unsigned char HorizontalTotal; /* CRT-Controller:00h */ unsigned char HorizDisplayEnd; /* CRT-Controller:01h */ unsigned char StartHorizRetrace; /* CRT-Controller:04h */ unsigned char EndHorizRetrace; /* CRT-Controller:05h */ unsigned char Overflow; /* CRT-Controller:07h */ unsigned char StartVertRetrace; /* CRT-Controller:10h */ unsigned char EndVertRetrace; /* CRT-Controller:11h */ unsigned char ModeControl; /* CRT-Controller:17h */ unsigned char ClockingMode; /* Seq-Controller:01h */ } vga_state; static void vga_vesa_blank(struct vgastate *state, int mode) { /* save original values of VGA controller registers */ if (!vga_vesa_blanked) { spin_lock_irq(&vga_lock); vga_state.SeqCtrlIndex = vga_r(state->vgabase, VGA_SEQ_I); vga_state.CrtCtrlIndex = inb_p(vga_video_port_reg); vga_state.CrtMiscIO = vga_r(state->vgabase, VGA_MIS_R); spin_unlock_irq(&vga_lock); outb_p(0x00, vga_video_port_reg); /* HorizontalTotal */ vga_state.HorizontalTotal = inb_p(vga_video_port_val); outb_p(0x01, vga_video_port_reg); /* HorizDisplayEnd */ vga_state.HorizDisplayEnd = inb_p(vga_video_port_val); outb_p(0x04, vga_video_port_reg); /* StartHorizRetrace */ vga_state.StartHorizRetrace = inb_p(vga_video_port_val); outb_p(0x05, vga_video_port_reg); /* EndHorizRetrace */ vga_state.EndHorizRetrace = inb_p(vga_video_port_val); outb_p(0x07, vga_video_port_reg); /* Overflow */ vga_state.Overflow = inb_p(vga_video_port_val); outb_p(0x10, vga_video_port_reg); /* StartVertRetrace */ vga_state.StartVertRetrace = inb_p(vga_video_port_val); outb_p(0x11, vga_video_port_reg); /* EndVertRetrace */ vga_state.EndVertRetrace = inb_p(vga_video_port_val); outb_p(0x17, vga_video_port_reg); /* ModeControl */ vga_state.ModeControl = inb_p(vga_video_port_val); vga_state.ClockingMode = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE); } /* assure that video is enabled */ /* "0x20" is VIDEO_ENABLE_bit in register 01 of sequencer */ spin_lock_irq(&vga_lock); vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, vga_state.ClockingMode | 0x20); /* test for vertical retrace in process.... */ if ((vga_state.CrtMiscIO & 0x80) == 0x80) vga_w(state->vgabase, VGA_MIS_W, vga_state.CrtMiscIO & 0xEF); /* * Set <End of vertical retrace> to minimum (0) and * <Start of vertical Retrace> to maximum (incl. overflow) * Result: turn off vertical sync (VSync) pulse. */ if (mode & VESA_VSYNC_SUSPEND) { outb_p(0x10, vga_video_port_reg); /* StartVertRetrace */ outb_p(0xff, vga_video_port_val); /* maximum value */ outb_p(0x11, vga_video_port_reg); /* EndVertRetrace */ outb_p(0x40, vga_video_port_val); /* minimum (bits 0..3) */ outb_p(0x07, vga_video_port_reg); /* Overflow */ outb_p(vga_state.Overflow | 0x84, vga_video_port_val); /* bits 9,10 of vert. retrace */ } if (mode & VESA_HSYNC_SUSPEND) { /* * Set <End of horizontal retrace> to minimum (0) and * <Start of horizontal Retrace> to maximum * Result: turn off horizontal sync (HSync) pulse. */ outb_p(0x04, vga_video_port_reg); /* StartHorizRetrace */ outb_p(0xff, vga_video_port_val); /* maximum */ outb_p(0x05, vga_video_port_reg); /* EndHorizRetrace */ outb_p(0x00, vga_video_port_val); /* minimum (0) */ } /* restore both index registers */ vga_w(state->vgabase, VGA_SEQ_I, vga_state.SeqCtrlIndex); outb_p(vga_state.CrtCtrlIndex, vga_video_port_reg); spin_unlock_irq(&vga_lock); } static void vga_vesa_unblank(struct vgastate *state) { /* restore original values of VGA controller registers */ spin_lock_irq(&vga_lock); vga_w(state->vgabase, VGA_MIS_W, vga_state.CrtMiscIO); outb_p(0x00, vga_video_port_reg); /* HorizontalTotal */ outb_p(vga_state.HorizontalTotal, vga_video_port_val); outb_p(0x01, vga_video_port_reg); /* HorizDisplayEnd */ outb_p(vga_state.HorizDisplayEnd, vga_video_port_val); outb_p(0x04, vga_video_port_reg); /* StartHorizRetrace */ outb_p(vga_state.StartHorizRetrace, vga_video_port_val); outb_p(0x05, vga_video_port_reg); /* EndHorizRetrace */ outb_p(vga_state.EndHorizRetrace, vga_video_port_val); outb_p(0x07, vga_video_port_reg); /* Overflow */ outb_p(vga_state.Overflow, vga_video_port_val); outb_p(0x10, vga_video_port_reg); /* StartVertRetrace */ outb_p(vga_state.StartVertRetrace, vga_video_port_val); outb_p(0x11, vga_video_port_reg); /* EndVertRetrace */ outb_p(vga_state.EndVertRetrace, vga_video_port_val); outb_p(0x17, vga_video_port_reg); /* ModeControl */ outb_p(vga_state.ModeControl, vga_video_port_val); /* ClockingMode */ vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, vga_state.ClockingMode); /* restore index/control registers */ vga_w(state->vgabase, VGA_SEQ_I, vga_state.SeqCtrlIndex); outb_p(vga_state.CrtCtrlIndex, vga_video_port_reg); spin_unlock_irq(&vga_lock); } static void vga_pal_blank(struct vgastate *state) { int i; for (i = 0; i < 16; i++) { vga_w(state->vgabase, VGA_PEL_IW, i); vga_w(state->vgabase, VGA_PEL_D, 0); vga_w(state->vgabase, VGA_PEL_D, 0); vga_w(state->vgabase, VGA_PEL_D, 0); } } static int vgacon_blank(struct vc_data *c, int blank, int mode_switch) { switch (blank) { case 0: /* Unblank */ if (vga_vesa_blanked) { vga_vesa_unblank(&state); vga_vesa_blanked = 0; } if (vga_palette_blanked) { vga_set_palette(c, color_table); vga_palette_blanked = 0; return 0; } vga_is_gfx = 0; /* Tell console.c that it has to restore the screen itself */ return 1; case 1: /* Normal blanking */ case -1: /* Obsolete */ if (!mode_switch && vga_video_type == VIDEO_TYPE_VGAC) { vga_pal_blank(&state); vga_palette_blanked = 1; return 0; } vgacon_set_origin(c); scr_memsetw((void *) vga_vram_base, BLANK, c->vc_screenbuf_size); if (mode_switch) vga_is_gfx = 1; return 1; default: /* VESA blanking */ if (vga_video_type == VIDEO_TYPE_VGAC) { vga_vesa_blank(&state, blank - 1); vga_vesa_blanked = blank; } return 0; } } #ifdef CAN_LOAD_EGA_FONTS static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512) { return 0; } /* * Adjust the screen to fit a font of a certain height */ static int vgacon_adjust_height(struct vc_data *vc, unsigned fontheight) { return 0; } static int vgacon_font_set(struct vc_data *c, struct console_font *font, unsigned flags) { return 0; } static int vgacon_font_get(struct vc_data *c, struct console_font *font) { return 0; } #else #define vgacon_font_set NULL #define vgacon_font_get NULL #endif static int vgacon_scrolldelta(struct vc_data *c, int lines) { if (!lines) /* Turn scrollback off */ c->vc_visible_origin = c->vc_origin; else { int vram_size = vga_vram_end - vga_vram_base; int margin = c->vc_size_row * 4; int ul, we, p, st; if (vga_rolled_over > (c->vc_scr_end - vga_vram_base) + margin) { ul = c->vc_scr_end - vga_vram_base; we = vga_rolled_over + c->vc_size_row; } else { ul = 0; we = vram_size; } p = (c->vc_visible_origin - vga_vram_base - ul + we) % we + lines * c->vc_size_row; st = (c->vc_origin - vga_vram_base - ul + we) % we; if (st < 2 * margin) margin = 0; if (p < margin) p = 0; if (p > st - margin) p = st; c->vc_visible_origin = vga_vram_base + (p + ul) % we; } vga_set_mem_top(c); return 1; } static int vgacon_set_origin(struct vc_data *c) { if (vga_is_gfx || /* We don't play origin tricks in graphic modes */ (console_blanked && !vga_palette_blanked)) /* Nor we write to blanked screens */ return 0; c->vc_origin = c->vc_visible_origin = vga_vram_base; vga_set_mem_top(c); vga_rolled_over = 0; return 1; } static void vgacon_save_screen(struct vc_data *c) { static int vga_bootup_console = 0; if (!vga_bootup_console) { /* This is a gross hack, but here is the only place we can * set bootup console parameters without messing up generic * console initialization routines. */ vga_bootup_console = 1; c->vc_x = ORIG_X; c->vc_y = ORIG_Y; } if (!vga_is_gfx) scr_memcpyw((u16 *) c->vc_screenbuf, (u16 *) c->vc_origin, c->vc_screenbuf_size); } static int vgacon_scroll(struct vc_data *c, int t, int b, int dir, int lines) { unsigned long oldo; unsigned int delta; if (t || b != c->vc_rows || vga_is_gfx) return 0; if (c->vc_origin != c->vc_visible_origin) vgacon_scrolldelta(c, 0); if (!vga_hardscroll_enabled || lines >= c->vc_rows / 2) return 0; oldo = c->vc_origin; delta = lines * c->vc_size_row; if (dir == SM_UP) { if (c->vc_scr_end + delta >= vga_vram_end) { scr_memcpyw((u16 *) vga_vram_base, (u16 *) (oldo + delta), c->vc_screenbuf_size - delta); c->vc_origin = vga_vram_base; vga_rolled_over = oldo - vga_vram_base; } else c->vc_origin += delta; scr_memsetw((u16 *) (c->vc_origin + c->vc_screenbuf_size - delta), c->vc_video_erase_char, delta); } else { if (oldo - delta < vga_vram_base) { scr_memmovew((u16 *) (vga_vram_end - c->vc_screenbuf_size + delta), (u16 *) oldo, c->vc_screenbuf_size - delta); c->vc_origin = vga_vram_end - c->vc_screenbuf_size; vga_rolled_over = 0; } else c->vc_origin -= delta; c->vc_scr_end = c->vc_origin + c->vc_screenbuf_size; scr_memsetw((u16 *) (c->vc_origin), c->vc_video_erase_char, delta); } c->vc_scr_end = c->vc_origin + c->vc_screenbuf_size; c->vc_visible_origin = c->vc_origin; vga_set_mem_top(c); c->vc_pos = (c->vc_pos - oldo) + c->vc_origin; return 1; } /* * The console `switch' structure for the VGA based console */ static int vgacon_dummy(struct vc_data *c) { return 0; } #define DUMMY (void *) vgacon_dummy const struct consw vga_con = { .owner = THIS_MODULE, .con_startup = vgacon_startup, .con_init = vgacon_init, .con_deinit = vgacon_deinit, .con_clear = DUMMY, .con_putc = DUMMY, .con_putcs = DUMMY, .con_cursor = vgacon_cursor, .con_scroll = vgacon_scroll, .con_bmove = DUMMY, .con_switch = vgacon_switch, .con_blank = vgacon_blank, .con_font_set = vgacon_font_set, .con_font_get = vgacon_font_get, .con_set_palette = vgacon_set_palette, .con_scrolldelta = vgacon_scrolldelta, .con_set_origin = vgacon_set_origin, .con_save_screen = vgacon_save_screen, .con_build_attr = vgacon_build_attr, .con_invert_region = vgacon_invert_region, }; MODULE_LICENSE("GPL");

64ea39ab7ea8cd12e35c42b6f6ee70b49127b492

6d084fbe91e46c9a7165f2f7c9823fa362e103c3

/tp-2014-1c-sistemasoperativos/UMV/src/memoria.h

28e5b1cf2824454da345b53eb201728cec1f2bea

no_license

mapeb/Marilu

b5ffa2748b686e55d26ce290d8eef1d7cb261435

0e773522f7dd9c16f93e45d12632b6e0c4a09652

refs/heads/master

UTF-8

C

h

#include <stdbool.h> #include <stdint.h> #include <stdlib.h> #include "Segmento.h" #include "Consola.h" #include "commons/collections/list.h" #include "commons/log.h" #include "commons/sockets.h" #ifndef MEMORIA_H_ #define MEMORIA_H_ #define WORSTFIT 1 #define FIRSTFIT 0 #define SEGMENTOVACIO 0 #define PorCONSOLA 0 #define PorARCHIVO 1 bool segmentoEsAnterior( void * seg1, void * seg2 ); t_list * crearListaEspacioDisponible(); Segmento * crearYllenarSegmento( uint32_t tamanio, void * segmento ); Segmento * crearSegmento ( uint32_t tamanio ); Segmento * crearSegmentoFirstFit ( uint32_t tamanio ); Segmento * crearSegmentoWorstFit( uint32_t tamanio ); Segmento * buscarSegmentoEnTabla( uint32_t idSeg); void borrarSegmento( Segmento * segmentoABorrar ); void moverSegmento(Segmento * segmento, uint32_t posicion) ; uint32_t tamanioSegmento(Segmento * segmento); void ordenarTablaSegmentos(); void compactar(); uint32_t memoriaOcupada(); uint32_t memoriaLibre(); bool solicitarPosicionDeMemoria( uint32_t base, uint32_t offset, uint32_t tamanio); void imprimirBytes( uint32_t base, uint32_t offset, uint32_t tamanio, char porDondeImprimo); void mostrarCaracteres( uint32_t cantidad, unsigned char * mem, char porDondeImprimo); bool escribirPosicionDeMemoria( uint32_t base, uint32_t offset, uint32_t tamanio, uint32_t buffer[]); bool chequearSegmentatiosFault( Segmento * segmento, uint32_t offset, uint32_t tamanio); #endif /* MEMORIA_H_ */

8771ce7b51ef81409f44b76cc3924a9a97fbc5e7

2875e427d9931ab8cfe2e066e1568c3130fcc3f2

/Solaris_2.6/os_net/src_ws/usr/src/uts/sun/sys/cg6thc.h

4643152a7ab7c903330c66396f65e9f26e696bc1

no_license

legacy-codedigger/Solaris-2.6-Source-Code

3afaff70487fb96c864d55bd5845dd11c6c5c871

60a0b3093caa7d84e63dd891a23df0e8e720bf3d

refs/heads/master

UTF-8

C

h

/* * Copyright 1989, Sun Microsystems, Inc. */ #ifndef _SYS_CG6THC_H #define _SYS_CG6THC_H #pragma ident "@(#)cg6thc.h 1.3 92/07/14 SMI" #ifdef __cplusplus extern "C" { #endif /* * TEC Hardware Configuration registers. * * Hardware register offsets from base address. These offsets are * intended to be added to a pointer-to-integer whose value is the * base address of the CG6 memory mapped register area. */ /* hardware configuration registers */ #define L_THC_HCHS (0x800 / sizeof (int)) #define L_THC_HCHSDVB (0x804 / sizeof (int)) #define L_THC_HCHD (0x808 / sizeof (int)) #define L_THC_HCVS (0x80C / sizeof (int)) #define L_THC_HCVD (0x810 / sizeof (int)) #define L_THC_HCREFRESH (0x814 / sizeof (int)) #define L_THC_HCMISC (0x818 / sizeof (int)) #define THC_HCMISC_REV_SHIFT 16 #define THC_HCMISC_REV_MASK 15 #define THC_HCMISC_RESET 0x1000 #define THC_HCMISC_VIDEO 0x0400 #define THC_HCMISC_SYNC 0x0200 #define THC_HCMISC_VSYNC 0x0100 #define THC_HCMISC_SYNCEN 0x0080 #define THC_HCMISC_CURSOR_RES 0x0040 #define THC_HCMISC_INTEN 0x0020 #define THC_HCMISC_INT 0x0010 #define THC_HCMISC_INIT 0x009f #define THC_HCMISC_CLEAR_VBLANK_IRQ 0x008f #define thc_set_video(thc, on) \ ((thc)->l_thc_hcmisc = \ (thc)->l_thc_hcmisc & ~THC_HCMISC_VIDEO | \ ((on) ? THC_HCMISC_VIDEO : 0)) #define thc_get_video(thc) \ ((thc)->l_thc_hcmisc & THC_HCMISC_VIDEO) #define thc_int_enable(thc) \ ((thc)->l_thc_hcmisc |= THC_HCMISC_INTEN) #define thc_int_disable(thc) \ ((thc)->l_thc_hcmisc = \ (thc)->l_thc_hcmisc & ~THC_HCMISC_INTEN | THC_HCMISC_INT) #define thc_int_pending(thc) \ ((thc)->l_thc_hcmisc & THC_HCMISC_INT) /* cursor address register */ #define L_THC_ADDRESS (0x8FC / sizeof (int)) /* cursor data registers, plane A */ #define L_THC_CURSORA00 (0x900 / sizeof (int)) #define L_THC_CURSORA01 (0x904 / sizeof (int)) #define L_THC_CURSORA02 (0x908 / sizeof (int)) #define L_THC_CURSORA03 (0x90C / sizeof (int)) #define L_THC_CURSORA04 (0x910 / sizeof (int)) #define L_THC_CURSORA05 (0x914 / sizeof (int)) #define L_THC_CURSORA06 (0x918 / sizeof (int)) #define L_THC_CURSORA07 (0x91C / sizeof (int)) #define L_THC_CURSORA08 (0x920 / sizeof (int)) #define L_THC_CURSORA09 (0x924 / sizeof (int)) #define L_THC_CURSORA10 (0x928 / sizeof (int)) #define L_THC_CURSORA11 (0x92C / sizeof (int)) #define L_THC_CURSORA12 (0x930 / sizeof (int)) #define L_THC_CURSORA13 (0x934 / sizeof (int)) #define L_THC_CURSORA14 (0x938 / sizeof (int)) #define L_THC_CURSORA15 (0x93C / sizeof (int)) #define L_THC_CURSORA16 (0x940 / sizeof (int)) #define L_THC_CURSORA17 (0x944 / sizeof (int)) #define L_THC_CURSORA18 (0x948 / sizeof (int)) #define L_THC_CURSORA19 (0x94C / sizeof (int)) #define L_THC_CURSORA20 (0x950 / sizeof (int)) #define L_THC_CURSORA21 (0x954 / sizeof (int)) #define L_THC_CURSORA22 (0x958 / sizeof (int)) #define L_THC_CURSORA23 (0x95C / sizeof (int)) #define L_THC_CURSORA24 (0x960 / sizeof (int)) #define L_THC_CURSORA25 (0x964 / sizeof (int)) #define L_THC_CURSORA26 (0x968 / sizeof (int)) #define L_THC_CURSORA27 (0x96C / sizeof (int)) #define L_THC_CURSORA28 (0x970 / sizeof (int)) #define L_THC_CURSORA29 (0x974 / sizeof (int)) #define L_THC_CURSORA30 (0x978 / sizeof (int)) #define L_THC_CURSORA31 (0x97C / sizeof (int)) /* cursor data registers, plane B */ #define L_THC_CURSORB00 (0x980 / sizeof (int)) #define L_THC_CURSORB01 (0x984 / sizeof (int)) #define L_THC_CURSORB02 (0x988 / sizeof (int)) #define L_THC_CURSORB03 (0x98C / sizeof (int)) #define L_THC_CURSORB04 (0x990 / sizeof (int)) #define L_THC_CURSORB05 (0x994 / sizeof (int)) #define L_THC_CURSORB06 (0x998 / sizeof (int)) #define L_THC_CURSORB07 (0x99C / sizeof (int)) #define L_THC_CURSORB08 (0x9A0 / sizeof (int)) #define L_THC_CURSORB09 (0x9A4 / sizeof (int)) #define L_THC_CURSORB10 (0x9A8 / sizeof (int)) #define L_THC_CURSORB11 (0x9AC / sizeof (int)) #define L_THC_CURSORB12 (0x9B0 / sizeof (int)) #define L_THC_CURSORB13 (0x9B4 / sizeof (int)) #define L_THC_CURSORB14 (0x9B8 / sizeof (int)) #define L_THC_CURSORB15 (0x9BC / sizeof (int)) #define L_THC_CURSORB16 (0x9C0 / sizeof (int)) #define L_THC_CURSORB17 (0x9C4 / sizeof (int)) #define L_THC_CURSORB18 (0x9C8 / sizeof (int)) #define L_THC_CURSORB19 (0x9CC / sizeof (int)) #define L_THC_CURSORB20 (0x9D0 / sizeof (int)) #define L_THC_CURSORB21 (0x9D4 / sizeof (int)) #define L_THC_CURSORB22 (0x9D8 / sizeof (int)) #define L_THC_CURSORB23 (0x9DC / sizeof (int)) #define L_THC_CURSORB24 (0x9E0 / sizeof (int)) #define L_THC_CURSORB25 (0x9E4 / sizeof (int)) #define L_THC_CURSORB26 (0x9E8 / sizeof (int)) #define L_THC_CURSORB27 (0x9EC / sizeof (int)) #define L_THC_CURSORB28 (0x9F0 / sizeof (int)) #define L_THC_CURSORB29 (0x9F4 / sizeof (int)) #define L_THC_CURSORB30 (0x9F8 / sizeof (int)) #define L_THC_CURSORB31 (0x9FC / sizeof (int)) /* * THC Cursor ADDRESS register bits. */ struct l_thc_cursor { unsigned l_thc_cursor_x : 16; /* X co-ordinate */ unsigned l_thc_cursor_y : 16; /* Y co-ordinate */ }; /* * THC Video Timing registers bits. */ struct l_thc_hchs { unsigned : 9; /* not used */ unsigned l_thc_hchs_hss : 7; /* hor. sync start */ unsigned : 9; /* not used */ unsigned l_thc_hchs_hse : 7; /* hor. sync end */ }; struct l_thc_hchsdvs { unsigned : 9; /* not used */ unsigned l_thc_hchsdvs_hss : 7; /* hor. sync end DVS */ unsigned : 5; /* not used */ unsigned l_thc_hchsdvs_hse : 11; /* current vert. line */ }; struct l_thc_hchd { unsigned : 9; /* not used */ unsigned l_thc_hchd_hds : 7; /* hor. display start */ unsigned : 9; /* not used */ unsigned l_thc_hchd_hde : 7; /* hor. display end */ }; struct l_thc_hcvs { unsigned : 5; /* not used */ unsigned l_thc_hcvs_vss : 11; /* vert. sync start */ unsigned : 5; /* not used */ unsigned l_thc_hcvs_hse : 11; /* vert. sync end */ }; struct l_thc_hcvd { unsigned : 5; /* not used */ unsigned l_thc_hcvd_vds : 11; /* vert. display start */ unsigned : 5; /* not used */ unsigned l_thc_hcvd_hde : 11; /* vert. display end */ }; struct l_thc_hcr { unsigned : 21; /* not used */ unsigned l_thc_hcr_clk : 11; /* refresh counter */ }; /* * THC HCMISC register bits. */ typedef enum { L_THC_HCMISC_VID_BLANK, L_THC_HCMISC_VID_DISPLAY } l_thc_hcmisc_vid_t; typedef enum { L_THC_HCMISC_INTR_IGNORE, L_THC_HCMISC_INTR_CLEAR, L_THC_HCMISC_INTR_SET } l_thc_hcmisc_intr_t; struct l_thc_hcmisc { unsigned : 12; /* unused */ unsigned l_thc_hcmisc_rev : 4; /* chip revision */ unsigned : 3; /* unused */ unsigned l_thc_hcmisc_reset : 1; /* reset */ unsigned : 1; /* unused */ l_thc_hcmisc_vid_t l_thc_hcmisc_vid : 1; /* enable video */ unsigned l_thc_hcmisc_sync : 1; /* sync */ unsigned l_thc_hcmisc_vsync : 1; /* vsync */ unsigned l_thc_hcmisc_ensync : 1; /* enable sync */ unsigned l_thc_hcmisc_cures : 1; /* cursor resolution */ l_thc_hcmisc_intr_t l_thc_hcmisc_intr : 2; /* enable interrupt */ unsigned l_thc_hcmisc_cycles : 4; /* cycles before xfer */ }; /* * define THC registers as a structure. */ struct thc { u_int l_thc_pad_0[512-0]; #ifdef structures struct l_thc_hchs l_thc_hchs; /* 512 */ struct l_thc_hchsdvs l_thc_hchsdvs; /* 513 */ struct l_thc_hchd l_thc_hchd; /* 514 */ struct l_thc_hcvs l_thc_hcvs; /* 515 */ struct l_thc_hcvd l_thc_hcvd; /* 516 */ struct l_thc_hcr l_thc_hcr; /* 517 */ struct l_thc_hcmisc l_thc_hcmisc; /* 518 */ u_int l_thc_pad_519[575-519]; struct l_thc_cursor l_thc_cursor; /* 575 */ #else u_int l_thc_hchs; /* 512 */ u_int l_thc_hchsdvs; /* 513 */ u_int l_thc_hchd; /* 514 */ u_int l_thc_hcvs; /* 515 */ u_int l_thc_hcvd; /* 516 */ u_int l_thc_hcr; /* 517 */ u_int l_thc_hcmisc; /* 518 */ u_int l_thc_pad_519[575-519]; u_int l_thc_cursor; /* 575 */ #endif u_int l_thc_cursora00; /* 576 */ u_int l_thc_cursora01; /* 577 */ u_int l_thc_cursora02; /* 578 */ u_int l_thc_cursora03; /* 579 */ u_int l_thc_cursora04; /* 580 */ u_int l_thc_cursora05; /* 581 */ u_int l_thc_cursora06; /* 582 */ u_int l_thc_cursora07; /* 583 */ u_int l_thc_cursora08; /* 584 */ u_int l_thc_cursora09; /* 585 */ u_int l_thc_cursora10; /* 586 */ u_int l_thc_cursora11; /* 587 */ u_int l_thc_cursora12; /* 588 */ u_int l_thc_cursora13; /* 589 */ u_int l_thc_cursora14; /* 590 */ u_int l_thc_cursora15; /* 591 */ u_int l_thc_cursora16; /* 592 */ u_int l_thc_cursora17; /* 593 */ u_int l_thc_cursora18; /* 594 */ u_int l_thc_cursora19; /* 595 */ u_int l_thc_cursora20; /* 596 */ u_int l_thc_cursora21; /* 597 */ u_int l_thc_cursora22; /* 598 */ u_int l_thc_cursora23; /* 599 */ u_int l_thc_cursora24; /* 600 */ u_int l_thc_cursora25; /* 601 */ u_int l_thc_cursora26; /* 602 */ u_int l_thc_cursora27; /* 603 */ u_int l_thc_cursora28; /* 604 */ u_int l_thc_cursora29; /* 605 */ u_int l_thc_cursora30; /* 606 */ u_int l_thc_cursora31; /* 607 */ u_int l_thc_cursorb00; /* 608 */ u_int l_thc_cursorb01; /* 609 */ u_int l_thc_cursorb02; /* 610 */ u_int l_thc_cursorb03; /* 611 */ u_int l_thc_cursorb04; /* 612 */ u_int l_thc_cursorb05; /* 613 */ u_int l_thc_cursorb06; /* 614 */ u_int l_thc_cursorb07; /* 615 */ u_int l_thc_cursorb08; /* 616 */ u_int l_thc_cursorb09; /* 617 */ u_int l_thc_cursorb10; /* 618 */ u_int l_thc_cursorb11; /* 619 */ u_int l_thc_cursorb12; /* 620 */ u_int l_thc_cursorb13; /* 621 */ u_int l_thc_cursorb14; /* 622 */ u_int l_thc_cursorb15; /* 623 */ u_int l_thc_cursorb16; /* 624 */ u_int l_thc_cursorb17; /* 625 */ u_int l_thc_cursorb18; /* 626 */ u_int l_thc_cursorb19; /* 627 */ u_int l_thc_cursorb20; /* 628 */ u_int l_thc_cursorb21; /* 629 */ u_int l_thc_cursorb22; /* 630 */ u_int l_thc_cursorb23; /* 631 */ u_int l_thc_cursorb24; /* 632 */ u_int l_thc_cursorb25; /* 633 */ u_int l_thc_cursorb26; /* 634 */ u_int l_thc_cursorb27; /* 635 */ u_int l_thc_cursorb28; /* 636 */ u_int l_thc_cursorb29; /* 637 */ u_int l_thc_cursorb30; /* 638 */ u_int l_thc_cursorb31; /* 639 */ }; #ifdef __cplusplus } #endif #endif /* _SYS_CG6THC_H */

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/windows_embedded_compact_2013_2015M09/WINCE800/private/winceos/COREOS/core/corelibc/crtw32/stdcpp/xstoul.c

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fanzcsoft/windows_embedded_compact_2013_2015M09

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// // Copyright (c) Microsoft Corporation. All rights reserved. // // // Use of this source code is subject to the terms of the Microsoft shared // source or premium shared source license agreement under which you licensed // this source code. If you did not accept the terms of the license agreement, // you are not authorized to use this source code. For the terms of the license, // please see the license agreement between you and Microsoft or, if applicable, // see the SOURCE.RTF on your install media or the root of your tools installation. // THE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES. // /* _Stoul function */ #include <stdlib.h> #include <ctype.h> #include <errno.h> #include <limits.h> #include <stddef.h> #include <string.h> #include "xmath.h" #pragma warning(disable: 4701) #if (ULONG_MAX >> 16) >> 16 != 0xffffffff && ULONG_MAX != 0xffffffff #error LONGS TOO LARGE FOR _Stoul #endif /* longs too large */ _C_STD_BEGIN /* macros */ #define BASE_MAX 36 /* largest valid base */ /* static data */ static const char digits[] = /* valid digits */ "0123456789abcdefghijklmnopqrstuvwxyz"; #if (ULONG_MAX >> 16) >> 16 == 0xffffffff static const char ndigs[BASE_MAX + 1] = { /* 64-bits! */ 0, 0, 65, 41, 33, 28, 25, 23, 22, 21, 20, 19, 18, 18, 17, 17, 17, 16, 16, 16, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13,}; #else /* (ULONG_MAX >> 16) >> 16 == 0xffffffff */ static const char ndigs[BASE_MAX+1] = { /* 32-bits! */ 0, 0, 33, 21, 17, 14, 13, 12, 11, 11, 10, 10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,}; #endif /* (ULONG_MAX >> 16) >> 16 == 0xffffffff */ #if defined(__cplusplus) && !defined(MRTDLL) extern "C" #endif _CRTIMP2_PURE unsigned long __CLRCALL_PURE_OR_CDECL _Stoulx(const char *s, char **endptr, int base, int *perr) { /* convert string to unsigned long, with checking */ const char *sc, *sd; const char *s1, *s2; char dig, sign; ptrdiff_t n; unsigned long x, y; if (perr != 0) *perr = 0; for (sc = s; isspace((unsigned char)*sc); ++sc) ; sign = *sc == '-' || *sc == '+' ? *sc++ : '+'; if (base < 0 || base == 1 || BASE_MAX < base) { /* silly base */ if (endptr != 0) *endptr = (char *)s; return (0); } else if (0 < base) { /* strip 0x or 0X */ if (base == 16 && *sc == '0' && (sc[1] == 'x' || sc[1] == 'X')) sc += 2; } else if (*sc != '0') base = 10; else if (sc[1] == 'x' || sc[1] == 'X') base = 16, sc += 2; else base = 8; for (s1 = sc; *sc == '0'; ++sc) ; /* skip leading zeros */ x = 0; for (s2 = sc, y = 0; (sd = (char *)memchr(&digits[0], tolower(*sc), base)) != 0; ++sc) { /* accumulate digits */ y = x; dig = (char)(sd - digits); /* for overflow checking */ x = x * base + dig; } if (s1 == sc) { /* check string validity */ if (endptr != 0) *endptr = (char *)s; return (0); } n = sc - s2 - ndigs[base]; if (n < 0) ; else if (0 < n || x < x - dig || (x - dig) / base != y) { /* overflow */ errno = ERANGE; if (perr != 0) *perr = 1; x = ULONG_MAX, sign = '+'; } if (sign == '-') /* get final value */ x = 0 - x; if (endptr != 0) *endptr = (char *)sc; return (x); } _CRTIMP2_PURE unsigned long __CLRCALL_PURE_OR_CDECL _Stoul(const char *s, char **endptr, int base) { /* convert string, discard error code */ return (_Stoulx(s, endptr, base, 0)); } _C_STD_END /* * Copyright (c) 1992-2006 by P.J. Plauger. ALL RIGHTS RESERVED. * Consult your license regarding permissions and restrictions. V5.02:0009 */

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/lexer.h

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#ifndef __LEXER_H #define __LEXER_H /* DO NOT MODIFY THIS FILE */ #include <stdio.h> typedef enum { LPAREN_TOK, RPAREN_TOK, DEFINE_TOK, LAMBDA_TOK, NUM_TOK, ID_TOK, IF_TOK, EOF_TOK } token_ty_t; typedef struct _token_t { token_ty_t type; union { char *s; int i; } val; } token_t; token_t *get_token(FILE *in); void print_token(FILE *out, token_t *t); #endif

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/jeu.h

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DuarteVi/Snake

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#ifndef JEU_H_ #define JEU_H_ int jeu(); #endif

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/Server/Sources/main.c

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Scythe14/Zappy

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refs/heads/master

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C

c

/* ** main.c for zappy in /home/bouca-_d/rendu/Zappy/Server ** ** Made by Dany Bouca Nova ** Login <[email protected]> ** ** Started on Sun Jul 5 02:05:22 2015 Dany Bouca Nova ** Last update Sun Jul 5 16:00:24 2015 Dany Bouca Nova */ #include <unistd.h> #include <stdlib.h> #include <stdio.h> #include <signal.h> #include <time.h> #include "server.h" t_serv g_serv; void print_conf() { t_elem *tmp; printf("Configuration : Max(%i) WorldX(%i) WorldY(%i) T(%i)\n", g_serv.opt.nb_players, g_serv.opt.x, g_serv.opt.y, g_serv.opt.delay); printf("Teams :\n"); tmp = g_serv.opt.team.first; while (tmp != NULL) { printf("\tName(%s) Max(%i)\n", ((t_team*)tmp->data)->name, g_serv.opt.nb_players); tmp = tmp->next; } } int main(int ac, char **av) { srandom(time(NULL) * getpid()); signal(SIGINT, handle_sigint_server); if (handle_options(ac, av, 0, 0) == FAIL) return (FAIL); if (init_server(1) == FAIL || init_map() == FAIL) { close(g_serv.sock); return (FAIL); } print_conf(); if (atexit(&free_server) != 0) { free_server(); return (FAIL); } start_server(); return (NONE); }

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/src/libraries/Native/Unix/System.Globalization.Native/pal_icushim_internal.h

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refs/heads/master

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C#

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h

// Licensed to the .NET Foundation under one or more agreements. // The .NET Foundation licenses this file to you under the MIT license. // // Enable calling ICU functions through shims to enable support for // multiple versions of ICU. #pragma once #if defined(TARGET_UNIX) #include "config.h" #if defined(TARGET_ANDROID) #include "pal_icushim_internal_android.h" #else #define U_DISABLE_RENAMING 1 // All ICU headers need to be included here so that all function prototypes are // available before the function pointers are declared below. #include <unicode/uclean.h> #include <unicode/ucurr.h> #include <unicode/ucal.h> #include <unicode/uchar.h> #include <unicode/ucol.h> #include <unicode/udat.h> #include <unicode/udata.h> #include <unicode/udatpg.h> #include <unicode/uenum.h> #include <unicode/uidna.h> #include <unicode/uldnames.h> #include <unicode/ulocdata.h> #include <unicode/unorm2.h> #include <unicode/unum.h> #include <unicode/ures.h> #include <unicode/usearch.h> #include <unicode/utf16.h> #include <unicode/utypes.h> #include <unicode/urename.h> #include <unicode/ustring.h> #endif #elif defined(TARGET_WINDOWS) #include "icu.h" #define HAVE_SET_MAX_VARIABLE 1 #define UDAT_STANDALONE_SHORTER_WEEKDAYS 1 #endif #include "pal_compiler.h" #if !defined(STATIC_ICU) // List of all functions from the ICU libraries that are used in the System.Globalization.Native.so #define FOR_ALL_UNCONDITIONAL_ICU_FUNCTIONS \ PER_FUNCTION_BLOCK(u_charsToUChars, libicuuc) \ PER_FUNCTION_BLOCK(u_getVersion, libicuuc) \ PER_FUNCTION_BLOCK(u_strlen, libicuuc) \ PER_FUNCTION_BLOCK(u_strncpy, libicuuc) \ PER_FUNCTION_BLOCK(u_tolower, libicuuc) \ PER_FUNCTION_BLOCK(u_toupper, libicuuc) \ PER_FUNCTION_BLOCK(ucal_add, libicui18n) \ PER_FUNCTION_BLOCK(ucal_close, libicui18n) \ PER_FUNCTION_BLOCK(ucal_get, libicui18n) \ PER_FUNCTION_BLOCK(ucal_getAttribute, libicui18n) \ PER_FUNCTION_BLOCK(ucal_getKeywordValuesForLocale, libicui18n) \ PER_FUNCTION_BLOCK(ucal_getLimit, libicui18n) \ PER_FUNCTION_BLOCK(ucal_getTimeZoneDisplayName, libicui18n) \ PER_FUNCTION_BLOCK(ucal_open, libicui18n) \ PER_FUNCTION_BLOCK(ucal_set, libicui18n) \ PER_FUNCTION_BLOCK(ucol_close, libicui18n) \ PER_FUNCTION_BLOCK(ucol_closeElements, libicui18n) \ PER_FUNCTION_BLOCK(ucol_getRules, libicui18n) \ PER_FUNCTION_BLOCK(ucol_getSortKey, libicui18n) \ PER_FUNCTION_BLOCK(ucol_getStrength, libicui18n) \ PER_FUNCTION_BLOCK(ucol_getVersion, libicui18n) \ PER_FUNCTION_BLOCK(ucol_next, libicui18n) \ PER_FUNCTION_BLOCK(ucol_previous, libicui18n) \ PER_FUNCTION_BLOCK(ucol_open, libicui18n) \ PER_FUNCTION_BLOCK(ucol_openElements, libicui18n) \ PER_FUNCTION_BLOCK(ucol_openRules, libicui18n) \ PER_FUNCTION_BLOCK(ucol_safeClone, libicui18n) \ PER_FUNCTION_BLOCK(ucol_setAttribute, libicui18n) \ PER_FUNCTION_BLOCK(ucol_strcoll, libicui18n) \ PER_FUNCTION_BLOCK(udat_close, libicui18n) \ PER_FUNCTION_BLOCK(udat_countSymbols, libicui18n) \ PER_FUNCTION_BLOCK(udat_getSymbols, libicui18n) \ PER_FUNCTION_BLOCK(udat_open, libicui18n) \ PER_FUNCTION_BLOCK(udat_setCalendar, libicui18n) \ PER_FUNCTION_BLOCK(udat_toPattern, libicui18n) \ PER_FUNCTION_BLOCK(udatpg_close, libicui18n) \ PER_FUNCTION_BLOCK(udatpg_getBestPattern, libicui18n) \ PER_FUNCTION_BLOCK(udatpg_open, libicui18n) \ PER_FUNCTION_BLOCK(uenum_close, libicuuc) \ PER_FUNCTION_BLOCK(uenum_count, libicuuc) \ PER_FUNCTION_BLOCK(uenum_next, libicuuc) \ PER_FUNCTION_BLOCK(uidna_close, libicuuc) \ PER_FUNCTION_BLOCK(uidna_nameToASCII, libicuuc) \ PER_FUNCTION_BLOCK(uidna_nameToUnicode, libicuuc) \ PER_FUNCTION_BLOCK(uidna_openUTS46, libicuuc) \ PER_FUNCTION_BLOCK(uloc_canonicalize, libicuuc) \ PER_FUNCTION_BLOCK(uloc_countAvailable, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getAvailable, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getBaseName, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getCharacterOrientation, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getCountry, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getDefault, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getDisplayCountry, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getDisplayLanguage, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getDisplayName, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getISO3Country, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getISO3Language, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getKeywordValue, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getLanguage, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getLCID, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getName, libicuuc) \ PER_FUNCTION_BLOCK(uloc_getParent, libicuuc) \ PER_FUNCTION_BLOCK(uloc_setKeywordValue, libicuuc) \ PER_FUNCTION_BLOCK(ulocdata_getCLDRVersion, libicui18n) \ PER_FUNCTION_BLOCK(ulocdata_getMeasurementSystem, libicui18n) \ PER_FUNCTION_BLOCK(unorm2_getNFCInstance, libicuuc) \ PER_FUNCTION_BLOCK(unorm2_getNFDInstance, libicuuc) \ PER_FUNCTION_BLOCK(unorm2_getNFKCInstance, libicuuc) \ PER_FUNCTION_BLOCK(unorm2_getNFKDInstance, libicuuc) \ PER_FUNCTION_BLOCK(unorm2_isNormalized, libicuuc) \ PER_FUNCTION_BLOCK(unorm2_normalize, libicuuc) \ PER_FUNCTION_BLOCK(unum_close, libicui18n) \ PER_FUNCTION_BLOCK(unum_getAttribute, libicui18n) \ PER_FUNCTION_BLOCK(unum_getSymbol, libicui18n) \ PER_FUNCTION_BLOCK(unum_open, libicui18n) \ PER_FUNCTION_BLOCK(unum_toPattern, libicui18n) \ PER_FUNCTION_BLOCK(ures_close, libicuuc) \ PER_FUNCTION_BLOCK(ures_getByKey, libicuuc) \ PER_FUNCTION_BLOCK(ures_getSize, libicuuc) \ PER_FUNCTION_BLOCK(ures_getStringByIndex, libicuuc) \ PER_FUNCTION_BLOCK(ures_open, libicuuc) \ PER_FUNCTION_BLOCK(usearch_close, libicui18n) \ PER_FUNCTION_BLOCK(usearch_first, libicui18n) \ PER_FUNCTION_BLOCK(usearch_getMatchedLength, libicui18n) \ PER_FUNCTION_BLOCK(usearch_last, libicui18n) \ PER_FUNCTION_BLOCK(usearch_openFromCollator, libicui18n) #if HAVE_SET_MAX_VARIABLE #define FOR_ALL_SET_VARIABLE_ICU_FUNCTIONS \ PER_FUNCTION_BLOCK(ucol_setMaxVariable, libicui18n) #else #define FOR_ALL_SET_VARIABLE_ICU_FUNCTIONS \ PER_FUNCTION_BLOCK(ucol_setVariableTop, libicui18n) #endif #if defined(TARGET_WINDOWS) #define FOR_ALL_OS_CONDITIONAL_ICU_FUNCTIONS \ PER_FUNCTION_BLOCK(ucurr_forLocale, libicuuc) \ PER_FUNCTION_BLOCK(ucurr_getName, libicuuc) \ PER_FUNCTION_BLOCK(uldn_close, libicuuc) \ PER_FUNCTION_BLOCK(uldn_keyValueDisplayName, libicuuc) \ PER_FUNCTION_BLOCK(uldn_open, libicuuc) #else // Unix ICU is dynamically resolved at runtime and these APIs in old versions // of ICU were in libicui18n #define FOR_ALL_OS_CONDITIONAL_ICU_FUNCTIONS \ PER_FUNCTION_BLOCK(ucurr_forLocale, libicui18n) \ PER_FUNCTION_BLOCK(ucurr_getName, libicui18n) \ PER_FUNCTION_BLOCK(uldn_close, libicui18n) \ PER_FUNCTION_BLOCK(uldn_keyValueDisplayName, libicui18n) \ PER_FUNCTION_BLOCK(uldn_open, libicui18n) #endif #define FOR_ALL_ICU_FUNCTIONS \ FOR_ALL_UNCONDITIONAL_ICU_FUNCTIONS \ FOR_ALL_SET_VARIABLE_ICU_FUNCTIONS \ FOR_ALL_OS_CONDITIONAL_ICU_FUNCTIONS // Declare pointers to all the used ICU functions #define PER_FUNCTION_BLOCK(fn, lib) EXTERN_C TYPEOF(fn)* fn##_ptr; FOR_ALL_ICU_FUNCTIONS #undef PER_FUNCTION_BLOCK // Redefine all calls to ICU functions as calls through pointers that are set // to the functions of the selected version of ICU in the initialization. #define u_charsToUChars(...) u_charsToUChars_ptr(__VA_ARGS__) #define u_getVersion(...) u_getVersion_ptr(__VA_ARGS__) #define u_strlen(...) u_strlen_ptr(__VA_ARGS__) #define u_strncpy(...) u_strncpy_ptr(__VA_ARGS__) #define u_tolower(...) u_tolower_ptr(__VA_ARGS__) #define u_toupper(...) u_toupper_ptr(__VA_ARGS__) #define ucal_add(...) ucal_add_ptr(__VA_ARGS__) #define ucal_close(...) ucal_close_ptr(__VA_ARGS__) #define ucal_get(...) ucal_get_ptr(__VA_ARGS__) #define ucal_getAttribute(...) ucal_getAttribute_ptr(__VA_ARGS__) #define ucal_getKeywordValuesForLocale(...) ucal_getKeywordValuesForLocale_ptr(__VA_ARGS__) #define ucal_getLimit(...) ucal_getLimit_ptr(__VA_ARGS__) #define ucal_getTimeZoneDisplayName(...) ucal_getTimeZoneDisplayName_ptr(__VA_ARGS__) #define ucal_open(...) ucal_open_ptr(__VA_ARGS__) #define ucal_set(...) ucal_set_ptr(__VA_ARGS__) #define ucol_close(...) ucol_close_ptr(__VA_ARGS__) #define ucol_closeElements(...) ucol_closeElements_ptr(__VA_ARGS__) #define ucol_getRules(...) ucol_getRules_ptr(__VA_ARGS__) #define ucol_getSortKey(...) ucol_getSortKey_ptr(__VA_ARGS__) #define ucol_getStrength(...) ucol_getStrength_ptr(__VA_ARGS__) #define ucol_getVersion(...) ucol_getVersion_ptr(__VA_ARGS__) #define ucol_next(...) ucol_next_ptr(__VA_ARGS__) #define ucol_previous(...) ucol_previous_ptr(__VA_ARGS__) #define ucol_open(...) ucol_open_ptr(__VA_ARGS__) #define ucol_openElements(...) ucol_openElements_ptr(__VA_ARGS__) #define ucol_openRules(...) ucol_openRules_ptr(__VA_ARGS__) #define ucol_safeClone(...) ucol_safeClone_ptr(__VA_ARGS__) #define ucol_setAttribute(...) ucol_setAttribute_ptr(__VA_ARGS__) #if HAVE_SET_MAX_VARIABLE #define ucol_setMaxVariable(...) ucol_setMaxVariable_ptr(__VA_ARGS__) #else #define ucol_setVariableTop(...) ucol_setVariableTop_ptr(__VA_ARGS__) #endif #define ucol_strcoll(...) ucol_strcoll_ptr(__VA_ARGS__) #define ucurr_forLocale(...) ucurr_forLocale_ptr(__VA_ARGS__) #define ucurr_getName(...) ucurr_getName_ptr(__VA_ARGS__) #define udat_close(...) udat_close_ptr(__VA_ARGS__) #define udat_countSymbols(...) udat_countSymbols_ptr(__VA_ARGS__) #define udat_getSymbols(...) udat_getSymbols_ptr(__VA_ARGS__) #define udat_open(...) udat_open_ptr(__VA_ARGS__) #define udat_setCalendar(...) udat_setCalendar_ptr(__VA_ARGS__) #define udat_toPattern(...) udat_toPattern_ptr(__VA_ARGS__) #define udatpg_close(...) udatpg_close_ptr(__VA_ARGS__) #define udatpg_getBestPattern(...) udatpg_getBestPattern_ptr(__VA_ARGS__) #define udatpg_open(...) udatpg_open_ptr(__VA_ARGS__) #define uenum_close(...) uenum_close_ptr(__VA_ARGS__) #define uenum_count(...) uenum_count_ptr(__VA_ARGS__) #define uenum_next(...) uenum_next_ptr(__VA_ARGS__) #define uidna_close(...) uidna_close_ptr(__VA_ARGS__) #define uidna_nameToASCII(...) uidna_nameToASCII_ptr(__VA_ARGS__) #define uidna_nameToUnicode(...) uidna_nameToUnicode_ptr(__VA_ARGS__) #define uidna_openUTS46(...) uidna_openUTS46_ptr(__VA_ARGS__) #define uldn_close(...) uldn_close_ptr(__VA_ARGS__) #define uldn_keyValueDisplayName(...) uldn_keyValueDisplayName_ptr(__VA_ARGS__) #define uldn_open(...) uldn_open_ptr(__VA_ARGS__) #define uloc_canonicalize(...) uloc_canonicalize_ptr(__VA_ARGS__) #define uloc_countAvailable(...) uloc_countAvailable_ptr(__VA_ARGS__) #define uloc_getAvailable(...) uloc_getAvailable_ptr(__VA_ARGS__) #define uloc_getBaseName(...) uloc_getBaseName_ptr(__VA_ARGS__) #define uloc_getCharacterOrientation(...) uloc_getCharacterOrientation_ptr(__VA_ARGS__) #define uloc_getCountry(...) uloc_getCountry_ptr(__VA_ARGS__) #define uloc_getDefault(...) uloc_getDefault_ptr(__VA_ARGS__) #define uloc_getDisplayCountry(...) uloc_getDisplayCountry_ptr(__VA_ARGS__) #define uloc_getDisplayLanguage(...) uloc_getDisplayLanguage_ptr(__VA_ARGS__) #define uloc_getDisplayName(...) uloc_getDisplayName_ptr(__VA_ARGS__) #define uloc_getISO3Country(...) uloc_getISO3Country_ptr(__VA_ARGS__) #define uloc_getISO3Language(...) uloc_getISO3Language_ptr(__VA_ARGS__) #define uloc_getKeywordValue(...) uloc_getKeywordValue_ptr(__VA_ARGS__) #define uloc_getLanguage(...) uloc_getLanguage_ptr(__VA_ARGS__) #define uloc_getLCID(...) uloc_getLCID_ptr(__VA_ARGS__) #define uloc_getName(...) uloc_getName_ptr(__VA_ARGS__) #define uloc_getParent(...) uloc_getParent_ptr(__VA_ARGS__) #define uloc_setKeywordValue(...) uloc_setKeywordValue_ptr(__VA_ARGS__) #define ulocdata_getCLDRVersion(...) ulocdata_getCLDRVersion_ptr(__VA_ARGS__) #define ulocdata_getMeasurementSystem(...) ulocdata_getMeasurementSystem_ptr(__VA_ARGS__) #define unorm2_getNFCInstance(...) unorm2_getNFCInstance_ptr(__VA_ARGS__) #define unorm2_getNFDInstance(...) unorm2_getNFDInstance_ptr(__VA_ARGS__) #define unorm2_getNFKCInstance(...) unorm2_getNFKCInstance_ptr(__VA_ARGS__) #define unorm2_getNFKDInstance(...) unorm2_getNFKDInstance_ptr(__VA_ARGS__) #define unorm2_isNormalized(...) unorm2_isNormalized_ptr(__VA_ARGS__) #define unorm2_normalize(...) unorm2_normalize_ptr(__VA_ARGS__) #define unum_close(...) unum_close_ptr(__VA_ARGS__) #define unum_getAttribute(...) unum_getAttribute_ptr(__VA_ARGS__) #define unum_getSymbol(...) unum_getSymbol_ptr(__VA_ARGS__) #define unum_open(...) unum_open_ptr(__VA_ARGS__) #define unum_toPattern(...) unum_toPattern_ptr(__VA_ARGS__) #define ures_close(...) ures_close_ptr(__VA_ARGS__) #define ures_getByKey(...) ures_getByKey_ptr(__VA_ARGS__) #define ures_getSize(...) ures_getSize_ptr(__VA_ARGS__) #define ures_getStringByIndex(...) ures_getStringByIndex_ptr(__VA_ARGS__) #define ures_open(...) ures_open_ptr(__VA_ARGS__) #define usearch_close(...) usearch_close_ptr(__VA_ARGS__) #define usearch_first(...) usearch_first_ptr(__VA_ARGS__) #define usearch_getMatchedLength(...) usearch_getMatchedLength_ptr(__VA_ARGS__) #define usearch_last(...) usearch_last_ptr(__VA_ARGS__) #define usearch_openFromCollator(...) usearch_openFromCollator_ptr(__VA_ARGS__) #endif // !defined(STATIC_ICU)

90635079897281114772eae8d8b7e2224c176551

8cfac6918a6024f22582d39a43670abc23e5324c

/project/ll-insertion/libft/ft_bitgetfour.c

c6a613af7cff45b02a810c2275df2e6e58851699

no_license

koloux/push_swap

66249aa1d01e6248fa857a8e1abf3937519b2646

1f10886051f7aba3bd281dfe59f2663417dd429d

refs/heads/master

UTF-8

C

c

/* ************************************************************************** */ /* */ /* ::: :::::::: */ /* ft_bitgetfour.c :+: :+: :+: */ /* +:+ +:+ +:+ */ /* By: nhuber <[email protected]> +#+ +:+ +#+ */ /* +#+#+#+#+#+ +#+ */ /* Created: 2016/03/06 13:48:28 by nhuber #+# #+# */ /* Updated: 2016/03/12 20:26:26 by nhuber ### ########.fr */ /* */ /* ************************************************************************** */ #include "libft.h" unsigned int ft_bitgetfour(unsigned int i, unsigned int index) { return (i >> index * 4 & 15); }

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ada21c1885cea007376ea4eba4798b584e9d8dcc

/003_DATA_STRUCTURE/012_BINARY_TREE/BinaryTreeFromPointer/BinaryTreeFromPointer/BinaryTree.h

619c96ac1b0234f8f129ccfee4c61fbe2b4db29f

permissive

JooHyeon-Roh/Cpp

e5f1d036306407b93fd109d216a825217e8a8af3

fe5cfce4872587f979a8b3ff0898cd9fe303cfb0

refs/heads/master

UTF-8

C

h

#pragma once #ifndef __BINARY_TREE_H__ #define __BINARY_TREE_H__ typedef struct _Node { int data; _Node* leftChild; _Node* rightChild; }Node; typedef struct _Tree { _Node* root; }Tree; void Init(Tree* tree); bool Insert(Tree* tree, int data); bool Delete(Tree* tree); void PrintData(Tree* tree); #endif

77b2eb637cb5ea8fcc90340254f314c2b2045b00

1456438321efcb4e8998a373ea0ded11740c9fdb

/formattedInput.c

1df0c80d7d25e751687aada8a4477b29c5039f48

no_license

cathyatseneca/ipc144mm-f15

30007919fc80e46da4723f011e8519da26251af7

9db76ceefcc8a59232c695b688eb1f5f022234b0

refs/heads/master

UTF-8

C

c

#include <stdio.h> /*this function validates user input*/ int validateInput(const char* prompt){ int input; int rc; //print prompt: printf("%s", prompt); rc=scanf("%d",&input); if(rc == 1){ printf("input was an integer!\n"); } else{ printf("input was bad\n"); } return input; } int main(void){ int input = validateInput("Enter total sought: "); printf("input is: %d\n",input); }

a3def628f2da0a65beffb4716d1087f322499f09

0652edefdb3ce11f6f23684a2610584b88ea2249

/source/adc.c

e72087c267c7b5622fa8a97817cb3adb4a999b44

no_license

cenriq07/CC_2021_12x

cddc9860974d88dae4ef3f0991ae8b25b83a31dd

639889c629e71af53a85faffd4e9ceeb6a857bcd

refs/heads/master

UTF-8

C

c

/** @file adc.c * @brief ADC Driver Source File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - API Functions * - Interrupt Handlers * . * which are relevant for the ADC driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Include Files */ #include "adc.h" #include "sys_vim.h" /* USER CODE BEGIN (1) */ /* USER CODE END */ /** @fn void adcInit(void) * @brief Initializes ADC Driver * * This function initializes the ADC driver. * */ /* USER CODE BEGIN (2) */ /* USER CODE END */ /* SourceId : ADC_SourceId_001 */ /* DesignId : ADC_DesignId_001 */ /* Requirements : HL_SR185 */ void adcInit(void) { /* USER CODE BEGIN (3) */ /* USER CODE END */ /** @b Initialize @b ADC1: */ /** - Reset ADC module */ adcREG1->RSTCR = 1U; adcREG1->RSTCR = 0U; /** - Enable 12-BIT ADC */ adcREG1->OPMODECR |= 0x80000000U; /** - Setup prescaler */ adcREG1->CLOCKCR = 7U; /** - Setup memory boundaries */ adcREG1->BNDCR = (uint32)((uint32)8U << 16U) | (8U + 8U); adcREG1->BNDEND = (adcREG1->BNDEND & 0xFFFF0000U) | (2U); /** - Setup event group conversion mode * - Setup data format * - Enable/Disable channel id in conversion result * - Enable/Disable continuous conversion */ adcREG1->GxMODECR[0U] = (uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U; /** - Setup event group hardware trigger * - Setup hardware trigger edge * - Setup hardware trigger source */ adcREG1->EVSRC = (uint32)0x00000000U | (uint32)ADC1_EVENT; /** - Setup event group sample window */ adcREG1->EVSAMP = 1U; /** - Setup event group sample discharge * - Setup discharge prescaler * - Enable/Disable discharge */ adcREG1->EVSAMPDISEN = (uint32)((uint32)0U << 8U) | (uint32)0x00000000U; /** - Setup group 1 conversion mode * - Setup data format * - Enable/Disable channel id in conversion result * - Enable/Disable continuous conversion */ adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U; /** - Setup group 1 hardware trigger * - Setup hardware trigger edge * - Setup hardware trigger source */ adcREG1->G1SRC = (uint32)0x00000000U | (uint32)ADC1_EVENT; /** - Setup group 1 sample window */ adcREG1->G1SAMP = 1U; /** - Setup group 1 sample discharge * - Setup discharge prescaler * - Enable/Disable discharge */ adcREG1->G1SAMPDISEN = (uint32)((uint32)0U << 8U) | (uint32)0x00000000U; /** - Setup group 2 conversion mode * - Setup data format * - Enable/Disable channel id in conversion result * - Enable/Disable continuous conversion */ adcREG1->GxMODECR[2U] = (uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U; /** - Setup group 2 hardware trigger * - Setup hardware trigger edge * - Setup hardware trigger source */ adcREG1->G2SRC = (uint32)0x00000000U | (uint32)ADC1_EVENT; /** - Setup group 2 sample window */ adcREG1->G2SAMP = 1U; /** - Setup group 2 sample discharge * - Setup discharge prescaler * - Enable/Disable discharge */ adcREG1->G2SAMPDISEN = (uint32)((uint32)0U << 8U) | (uint32)0x00000000U; /** - ADC1 EVT pin output value */ adcREG1->EVTOUT = 0U; /** - ADC1 EVT pin direction */ adcREG1->EVTDIR = 0U; /** - ADC1 EVT pin open drain enable */ adcREG1->EVTPDR = 0U; /** - ADC1 EVT pin pullup / pulldown selection */ adcREG1->EVTPSEL = 1U; /** - ADC1 EVT pin pullup / pulldown enable*/ adcREG1->EVTDIS = 0U; /** - Enable ADC module */ adcREG1->OPMODECR |= 0x80140001U; /** - Wait for buffer initialization complete */ /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ while (((adcREG1->BNDEND & 0xFFFF0000U) >> 16U ) != 0U) { } /* Wait */ /** - Setup parity */ adcREG1->PARCR = 0x00000005U; /* USER CODE BEGIN (4) */ /* USER CODE END */ } /* USER CODE BEGIN (5) */ /* USER CODE END */ /** - s_adcSelect is used as constant table for channel selection */ static const uint32 s_adcSelect[2U][3U] = { {0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U}, {0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U , 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U} }; /** - s_adcFiFoSize is used as constant table for channel selection */ static const uint32 s_adcFiFoSize[2U][3U] = { {16U, 16U, 16U}, {16U, 16U, 16U} }; /* USER CODE BEGIN (6) */ /* USER CODE END */ /** @fn void adcStartConversion(adcBASE_t *adc, uint32 group) * @brief Starts an ADC conversion * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * * This function starts a conversion of the ADC hardware group. * */ /* SourceId : ADC_SourceId_002 */ /* DesignId : ADC_DesignId_002 */ /* Requirements : HL_SR186 */ void adcStartConversion(adcBASE_t *adc, uint32 group) { uint32 index = (adc == adcREG1) ? 0U : 1U; /* USER CODE BEGIN (7) */ /* USER CODE END */ /** - Setup FiFo size */ adc->GxINTCR[group] = s_adcFiFoSize[index][group]; /** - Start Conversion */ adc->GxSEL[group] = s_adcSelect[index][group]; /** @note The function adcInit has to be called before this function can be used. */ /* USER CODE BEGIN (8) */ /* USER CODE END */ } /* USER CODE BEGIN (9) */ /* USER CODE END */ /** @fn void adcStopConversion(adcBASE_t *adc, uint32 group) * @brief Stops an ADC conversion * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * * This function stops a conversion of the ADC hardware group. * */ /* SourceId : ADC_SourceId_003 */ /* DesignId : ADC_DesignId_003 */ /* Requirements : HL_SR187 */ void adcStopConversion(adcBASE_t *adc, uint32 group) { /* USER CODE BEGIN (10) */ /* USER CODE END */ /** - Stop Conversion */ adc->GxSEL[group] = 0U; /** @note The function adcInit has to be called before this function can be used. */ /* USER CODE BEGIN (11) */ /* USER CODE END */ } /* USER CODE BEGIN (12) */ /* USER CODE END */ /** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group) * @brief Resets FiFo read and write pointer. * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * * This function resets the FiFo read and write pointers. * */ /* SourceId : ADC_SourceId_004 */ /* DesignId : ADC_DesignId_004*/ /* Requirements : HL_SR188 */ void adcResetFiFo(adcBASE_t *adc, uint32 group) { /* USER CODE BEGIN (13) */ /* USER CODE END */ /** - Reset FiFo */ adc->GxFIFORESETCR[group] = 1U; /** @note The function adcInit has to be called before this function can be used.\n * the conversion should be stopped before calling this function. */ /* USER CODE BEGIN (14) */ /* USER CODE END */ } /* USER CODE BEGIN (15) */ /* USER CODE END */ /** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) * @brief Gets converted a ADC values * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * @param[out] data Pointer to store ADC converted data * @return The function will return the number of converted values copied into data buffer: * * This function writes a ADC message into a ADC message box. * */ /* SourceId : ADC_SourceId_005 */ /* DesignId : ADC_DesignId_005 */ /* Requirements : HL_SR189 */ uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) { uint32 i; uint32 buf; uint32 mode; uint32 index = (adc == adcREG1) ? 0U : 1U; uint32 intcr_reg = adc->GxINTCR[group]; uint32 count = (intcr_reg >= 256U) ? s_adcFiFoSize[index][group] : (s_adcFiFoSize[index][group] - (uint32)(intcr_reg & 0xFFU)); adcData_t *ptr = data; /* USER CODE BEGIN (16) */ /* USER CODE END */ mode = (adc->OPMODECR & ADC_12_BIT_MODE); if(mode == ADC_12_BIT_MODE) { /** - Get conversion data and channel/pin id */ for (i = 0U; i < count; i++) { buf = adc->GxBUF[group].BUF0; /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ ptr->value = (uint16)(buf & 0xFFFU); ptr->id = (uint32)((buf >> 16U) & 0x1FU); /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ ptr++; } } else { /** - Get conversion data and channel/pin id */ for (i = 0U; i < count; i++) { buf = adc->GxBUF[group].BUF0; /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ ptr->value = (uint16)(buf & 0x3FFU); ptr->id = (uint32)((buf >> 10U) & 0x1FU); /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ ptr++; } } adc->GxINTFLG[group] = 9U; /** @note The function adcInit has to be called before this function can be used.\n * The user is responsible to initialize the message box. */ /* USER CODE BEGIN (17) */ /* USER CODE END */ return count; } /* USER CODE BEGIN (18) */ /* USER CODE END */ /** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) * @brief Checks if FiFo buffer is full * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * @return The function will return: * - 0: When FiFo buffer is not full * - 1: When FiFo buffer is full * - 3: When FiFo buffer overflow occurred * * This function checks FiFo buffer status. * */ /* SourceId : ADC_SourceId_006 */ /* DesignId : ADC_DesignId_006 */ /* Requirements : HL_SR190 */ uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) { uint32 flags; /* USER CODE BEGIN (19) */ /* USER CODE END */ /** - Read FiFo flags */ flags = adc->GxINTFLG[group] & 3U; /** @note The function adcInit has to be called before this function can be used. */ /* USER CODE BEGIN (20) */ /* USER CODE END */ return flags; } /* USER CODE BEGIN (21) */ /* USER CODE END */ /** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) * @brief Checks if Conversion is complete * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * @return The function will return: * - 0: When is not finished * - 8: When conversion is complete * * This function checks if conversion is complete. * */ /* SourceId : ADC_SourceId_007 */ /* DesignId : ADC_DesignId_007 */ /* Requirements : HL_SR191 */ uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) { uint32 flags; /* USER CODE BEGIN (22) */ /* USER CODE END */ /** - Read conversion flags */ flags = adc->GxINTFLG[group] & 8U; /** @note The function adcInit has to be called before this function can be used. */ /* USER CODE BEGIN (23) */ /* USER CODE END */ return flags; } /* USER CODE BEGIN (24) */ /* USER CODE END */ /** @fn void adcCalibration(adcBASE_t *adc) * @brief Computes offset error using Calibration mode * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * This function computes offset error using Calibration mode * */ /* SourceId : ADC_SourceId_008 */ /* DesignId : ADC_DesignId_010 */ /* Requirements : HL_SR194 */ void adcCalibration(adcBASE_t *adc) { /* USER CODE BEGIN (25) */ /* USER CODE END */ uint32 conv_val[5U]={0U,0U,0U,0U,0U}; uint32 loop_index=0U; uint32 offset_error=0U; uint32 backup_mode; /** - Backup Mode before Calibration */ backup_mode = adc->OPMODECR; /** - Enable 12-BIT ADC */ adc->OPMODECR |= 0x80000000U; /* Disable all channels for conversion */ adc->GxSEL[0U]=0x00U; adc->GxSEL[1U]=0x00U; adc->GxSEL[2U]=0x00U; for(loop_index=0U;loop_index<4U;loop_index++) { /* Disable Self Test and Calibration mode */ adc->CALCR=0x0U; switch(loop_index) { case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */ adc->CALCR=0x0U; break; case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */ adc->CALCR=0x0100U; break; case 2U : /* Test 1 : Bride En = 1 , HiLo =0 */ adc->CALCR=0x0200U; break; case 3U : /* Test 1 : Bride En = 1 , HiLo =1 */ adc->CALCR=0x0300U; break; default : break; } /* Enable Calibration mode */ adc->CALCR|=0x1U; /* Start calibration conversion */ adc->CALCR|=0x00010000U; /* Wait for calibration conversion to complete */ /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ while((adc->CALCR & 0x00010000U)==0x00010000U) { } /* Wait */ /* Read converted value */ conv_val[loop_index]= adc->CALR; } /* Disable Self Test and Calibration mode */ adc->CALCR=0x0U; /* Compute the Offset error correction value */ conv_val[4U]=conv_val[0U]+ conv_val[1U] + conv_val[2U] + conv_val[3U]; conv_val[4U]=(conv_val[4U]/4U); offset_error=conv_val[4U]-0x7FFU; /*Write the offset error to the Calibration register */ /* Load 2;s complement of the computed value to ADCALR register */ offset_error=~offset_error; offset_error=offset_error & 0xFFFU; offset_error=offset_error+1U; adc->CALR = offset_error; /** - Restore Mode after Calibration */ adc->OPMODECR = backup_mode; /** @note The function adcInit has to be called before using this function. */ /* USER CODE BEGIN (26) */ /* USER CODE END */ } /** @fn void adcMidPointCalibration(adcBASE_t *adc) * @brief Computes offset error using Mid Point Calibration mode * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @return This function will return offset error using Mid Point Calibration mode * * This function computes offset error using Mid Point Calibration mode * */ /* SourceId : ADC_SourceId_009 */ /* DesignId : ADC_DesignId_011 */ /* Requirements : HL_SR195 */ uint32 adcMidPointCalibration(adcBASE_t *adc) { /* USER CODE BEGIN (27) */ /* USER CODE END */ uint32 conv_val[3U]={0U,0U,0U}; uint32 loop_index=0U; uint32 offset_error=0U; uint32 backup_mode; /** - Backup Mode before Calibration */ backup_mode = adc->OPMODECR; /** - Enable 12-BIT ADC */ adc->OPMODECR |= 0x80000000U; /* Disable all channels for conversion */ adc->GxSEL[0U]=0x00U; adc->GxSEL[1U]=0x00U; adc->GxSEL[2U]=0x00U; for(loop_index=0U;loop_index<2U;loop_index++) { /* Disable Self Test and Calibration mode */ adc->CALCR=0x0U; switch(loop_index) { case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */ adc->CALCR=0x0U; break; case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */ adc->CALCR=0x0100U; break; default : break; } /* Enable Calibration mode */ adc->CALCR|=0x1U; /* Start calibration conversion */ adc->CALCR|=0x00010000U; /* Wait for calibration conversion to complete */ /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ while((adc->CALCR & 0x00010000U)==0x00010000U) { } /* Wait */ /* Read converted value */ conv_val[loop_index]= adc->CALR; } /* Disable Self Test and Calibration mode */ adc->CALCR=0x0U; /* Compute the Offset error correction value */ conv_val[2U]=(conv_val[0U])+ (conv_val[1U]); conv_val[2U]=(conv_val[2U]/2U); offset_error=conv_val[2U]-0x7FFU; /* Write the offset error to the Calibration register */ /* Load 2's complement of the computed value to ADCALR register */ offset_error=~offset_error; offset_error=offset_error+1U; offset_error=offset_error & 0xFFFU; adc->CALR = offset_error; /** - Restore Mode after Calibration */ adc->OPMODECR = backup_mode; return(offset_error); /** @note The function adcInit has to be called before this function can be used. */ /* USER CODE BEGIN (28) */ /* USER CODE END */ } /* USER CODE BEGIN (29) */ /* USER CODE END */ /** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group) * @brief Enable notification * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * * This function will enable the notification of a conversion. * In single conversion mode for conversion complete and * in continuous conversion mode when the FiFo buffer is full. * */ /* SourceId : ADC_SourceId_010 */ /* DesignId : ADC_DesignId_008 */ /* Requirements : HL_SR192 */ void adcEnableNotification(adcBASE_t *adc, uint32 group) { uint32 notif = (((uint32)(adc->GxMODECR[group]) & 2U) == 2U) ? 1U : 8U; /* USER CODE BEGIN (30) */ /* USER CODE END */ adc->GxINTENA[group] = notif; /** @note The function adcInit has to be called before this function can be used.\n * This function should be called before the conversion is started */ /* USER CODE BEGIN (31) */ /* USER CODE END */ } /* USER CODE BEGIN (32) */ /* USER CODE END */ /** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group) * @brief Disable notification * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group Hardware group of ADC module: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * * This function will disable the notification of a conversion. */ /* SourceId : ADC_SourceId_011 */ /* DesignId : ADC_DesignId_009 */ /* Requirements : HL_SR193 */ void adcDisableNotification(adcBASE_t *adc, uint32 group) { /* USER CODE BEGIN (33) */ /* USER CODE END */ adc->GxINTENA[group] = 0U; /** @note The function adcInit has to be called before this function can be used. */ /* USER CODE BEGIN (34) */ /* USER CODE END */ } /** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value) * @brief Set ADCEVT pin * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * @param[in] value Value to be set: 0 or 1 * * This function will set the ADC EVT pin if configured as an output pin. */ /* SourceId : ADC_SourceId_020 */ /* DesignId : ADC_DesignId_014 */ /* Requirements : HL_SR529 */ void adcSetEVTPin(adcBASE_t *adc, uint32 value) { adc->EVTOUT = value; } /** @fn uint32 adcGetEVTPin(adcBASE_t *adc) * @brief Set ADCEVT pin * @param[in] adc Pointer to ADC module: * - adcREG1: ADC1 module pointer * @return Value of the ADC EVT pin: 0 or 1 * * This function will return the value of ADC EVT pin. */ /* SourceId : ADC_SourceId_021 */ /* DesignId : ADC_DesignId_015 */ /* Requirements : HL_SR529 */ uint32 adcGetEVTPin(adcBASE_t *adc) { return adc->EVTIN; } /** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) * @brief Get the initial or current values of the configuration registers * * @param[in] *config_reg: pointer to the struct to which the initial or current * value of the configuration registers need to be stored * @param[in] type: whether initial or current value of the configuration registers need to be stored * - InitialValue: initial value of the configuration registers will be stored * in the struct pointed by config_reg * - CurrentValue: initial value of the configuration registers will be stored * in the struct pointed by config_reg * * This function will copy the initial or current value (depending on the parameter 'type') * of the configuration registers to the struct pointed by config_reg * */ /* SourceId : ADC_SourceId_012 */ /* DesignId : ADC_DesignId_012 */ /* Requirements : HL_SR203 */ void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) { if (type == InitialValue) { config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE; config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE; config_reg->CONFIG_GxMODECR[0U] = ADC1_G0MODECR_CONFIGVALUE; config_reg->CONFIG_GxMODECR[1U] = ADC1_G1MODECR_CONFIGVALUE; config_reg->CONFIG_GxMODECR[2U] = ADC1_G2MODECR_CONFIGVALUE; config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE; config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE; config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE; config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE; config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE; config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE; config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE; config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE; config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE; config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE; config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE; config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE; } else { config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR; config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR; config_reg->CONFIG_GxMODECR[0U] = adcREG1->GxMODECR[0U]; config_reg->CONFIG_GxMODECR[1U] = adcREG1->GxMODECR[1U]; config_reg->CONFIG_GxMODECR[2U] = adcREG1->GxMODECR[2U]; config_reg->CONFIG_G0SRC = adcREG1->EVSRC; config_reg->CONFIG_G1SRC = adcREG1->G1SRC; config_reg->CONFIG_G2SRC = adcREG1->G2SRC; config_reg->CONFIG_BNDCR = adcREG1->BNDCR; config_reg->CONFIG_BNDEND = adcREG1->BNDEND; config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP; config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP; config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP; config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN; config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN; config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN; config_reg->CONFIG_PARCR = adcREG1->PARCR; } } /* USER CODE BEGIN (35) */ /* USER CODE END */

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/Code/Drivers/Motors.h

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no_license

fnafnio/explorerbot

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/* Bluetooth Robot Copyright (C) Dean Camera, 2011. dean [at] fourwalledcubicle [dot] com www.fourwalledcubicle.com */ /* Copyright 2011 Dean Camera (dean [at] fourwalledcubicle [dot] com) Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that the copyright notice and this permission notice and warranty disclaimer appear in supporting documentation, and that the name of the author not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. The author disclaim all warranties with regard to this software, including all implied warranties of merchantability and fitness. In no event shall the author be liable for any special, indirect or consequential damages or any damages whatsoever resulting from loss of use, data or profits, whether in an action of contract, negligence or other tortious action, arising out of or in connection with the use or performance of this software. */ /** \file * * Header file for Motors.c. */ #ifndef _MOTORS_H_ #define _MOTORS_H_ /* Includes: */ #include <avr/io.h> #include <avr/interrupt.h> #include <stdbool.h> #include <stdlib.h> #include <LUFA/Common/Common.h> /* Macros: */ /** Sets the maximum motor PWM value which may be set. Motor power values above this absolute value will * be clamped to this value instead. */ #define MAX_MOTOR_POWER 0x0EEE /* Function Prototypes: */ void Motors_Init(void); void Motors_SetChannelSpeed(const int16_t LeftPower, const int16_t RightPower); #endif

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bowen-xu/SPIXE

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#ifndef _SPIXE_KERNEL_H_ #define _SPIXE_KERNEL_H_ #endif // !_SPIXE_KERNEL_H_

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refs/heads/master

MIT

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C

c

/* $OpenBSD: ec_key.c,v 1.26 2021/04/20 17:23:37 tb Exp $ */ /* * Written by Nils Larsch for the OpenSSL project. */ /* ==================================================================== * Copyright (c) 1998-2005 The OpenSSL Project. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * 3. All advertising materials mentioning features or use of this * software must display the following acknowledgment: * "This product includes software developed by the OpenSSL Project * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" * * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to * endorse or promote products derived from this software without * prior written permission. For written permission, please contact * [email protected]. * * 5. Products derived from this software may not be called "OpenSSL" * nor may "OpenSSL" appear in their names without prior written * permission of the OpenSSL Project. * * 6. Redistributions of any form whatsoever must retain the following * acknowledgment: * "This product includes software developed by the OpenSSL Project * for use in the OpenSSL Toolkit (http://www.openssl.org/)" * * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * ==================================================================== * * This product includes cryptographic software written by Eric Young * ([email protected]). This product includes software written by Tim * Hudson ([email protected]). * */ /* ==================================================================== * Copyright 2002 Sun Microsystems, Inc. ALL RIGHTS RESERVED. * Portions originally developed by SUN MICROSYSTEMS, INC., and * contributed to the OpenSSL project. */ #include <string.h> #include <openssl/opensslconf.h> #ifndef OPENSSL_NO_ENGINE #include <openssl/engine.h> #endif #include <openssl/err.h> #include "bn_lcl.h" #include "ec_lcl.h" EC_KEY * EC_KEY_new(void) { return EC_KEY_new_method(NULL); } EC_KEY * EC_KEY_new_by_curve_name(int nid) { EC_KEY *ret = EC_KEY_new(); if (ret == NULL) return NULL; ret->group = EC_GROUP_new_by_curve_name(nid); if (ret->group == NULL) { EC_KEY_free(ret); return NULL; } if (ret->meth->set_group != NULL && ret->meth->set_group(ret, ret->group) == 0) { EC_KEY_free(ret); return NULL; } return ret; } void EC_KEY_free(EC_KEY * r) { int i; if (r == NULL) return; i = CRYPTO_add(&r->references, -1, CRYPTO_LOCK_EC); if (i > 0) return; if (r->meth != NULL && r->meth->finish != NULL) r->meth->finish(r); #ifndef OPENSSL_NO_ENGINE ENGINE_finish(r->engine); #endif CRYPTO_free_ex_data(CRYPTO_EX_INDEX_EC_KEY, r, &r->ex_data); EC_GROUP_free(r->group); EC_POINT_free(r->pub_key); BN_clear_free(r->priv_key); EC_EX_DATA_free_all_data(&r->method_data); freezero(r, sizeof(EC_KEY)); } EC_KEY * EC_KEY_copy(EC_KEY * dest, const EC_KEY * src) { EC_EXTRA_DATA *d; if (dest == NULL || src == NULL) { ECerror(ERR_R_PASSED_NULL_PARAMETER); return NULL; } if (src->meth != dest->meth) { if (dest->meth != NULL && dest->meth->finish != NULL) dest->meth->finish(dest); #ifndef OPENSSL_NO_ENGINE if (ENGINE_finish(dest->engine) == 0) return 0; dest->engine = NULL; #endif } /* copy the parameters */ if (src->group) { const EC_METHOD *meth = EC_GROUP_method_of(src->group); /* clear the old group */ EC_GROUP_free(dest->group); dest->group = EC_GROUP_new(meth); if (dest->group == NULL) return NULL; if (!EC_GROUP_copy(dest->group, src->group)) return NULL; } /* copy the public key */ if (src->pub_key && src->group) { EC_POINT_free(dest->pub_key); dest->pub_key = EC_POINT_new(src->group); if (dest->pub_key == NULL) return NULL; if (!EC_POINT_copy(dest->pub_key, src->pub_key)) return NULL; } /* copy the private key */ if (src->priv_key) { if (dest->priv_key == NULL) { dest->priv_key = BN_new(); if (dest->priv_key == NULL) return NULL; } if (!BN_copy(dest->priv_key, src->priv_key)) return NULL; } /* copy method/extra data */ EC_EX_DATA_free_all_data(&dest->method_data); for (d = src->method_data; d != NULL; d = d->next) { void *t = d->dup_func(d->data); if (t == NULL) return 0; if (!EC_EX_DATA_set_data(&dest->method_data, t, d->dup_func, d->free_func, d->clear_free_func)) return 0; } /* copy the rest */ dest->enc_flag = src->enc_flag; dest->conv_form = src->conv_form; dest->version = src->version; dest->flags = src->flags; if (!CRYPTO_dup_ex_data(CRYPTO_EX_INDEX_EC_KEY, &dest->ex_data, &((EC_KEY *)src)->ex_data)) /* XXX const */ return NULL; if (src->meth != dest->meth) { #ifndef OPENSSL_NO_ENGINE if (src->engine != NULL && ENGINE_init(src->engine) == 0) return 0; dest->engine = src->engine; #endif dest->meth = src->meth; } if (src->meth != NULL && src->meth->copy != NULL && src->meth->copy(dest, src) == 0) return 0; return dest; } EC_KEY * EC_KEY_dup(const EC_KEY * ec_key) { EC_KEY *ret; if ((ret = EC_KEY_new_method(ec_key->engine)) == NULL) return NULL; if (EC_KEY_copy(ret, ec_key) == NULL) { EC_KEY_free(ret); return NULL; } return ret; } int EC_KEY_up_ref(EC_KEY * r) { int i = CRYPTO_add(&r->references, 1, CRYPTO_LOCK_EC); return ((i > 1) ? 1 : 0); } int EC_KEY_set_ex_data(EC_KEY *r, int idx, void *arg) { return CRYPTO_set_ex_data(&r->ex_data, idx, arg); } void * EC_KEY_get_ex_data(const EC_KEY *r, int idx) { return CRYPTO_get_ex_data(&r->ex_data, idx); } int EC_KEY_generate_key(EC_KEY *eckey) { if (eckey->meth->keygen != NULL) return eckey->meth->keygen(eckey); ECerror(EC_R_NOT_IMPLEMENTED); return 0; } int ossl_ec_key_gen(EC_KEY *eckey) { int ok = 0; BN_CTX *ctx = NULL; BIGNUM *priv_key = NULL, *order = NULL; EC_POINT *pub_key = NULL; if (!eckey || !eckey->group) { ECerror(ERR_R_PASSED_NULL_PARAMETER); return 0; } if ((order = BN_new()) == NULL) goto err; if ((ctx = BN_CTX_new()) == NULL) goto err; if ((priv_key = eckey->priv_key) == NULL) { if ((priv_key = BN_new()) == NULL) goto err; } if (!EC_GROUP_get_order(eckey->group, order, ctx)) goto err; if (!bn_rand_interval(priv_key, BN_value_one(), order)) goto err; if ((pub_key = eckey->pub_key) == NULL) { if ((pub_key = EC_POINT_new(eckey->group)) == NULL) goto err; } if (!EC_POINT_mul(eckey->group, pub_key, priv_key, NULL, NULL, ctx)) goto err; eckey->priv_key = priv_key; eckey->pub_key = pub_key; ok = 1; err: BN_free(order); if (eckey->pub_key == NULL) EC_POINT_free(pub_key); if (eckey->priv_key == NULL) BN_free(priv_key); BN_CTX_free(ctx); return (ok); } int EC_KEY_check_key(const EC_KEY * eckey) { int ok = 0; BN_CTX *ctx = NULL; const BIGNUM *order = NULL; EC_POINT *point = NULL; if (!eckey || !eckey->group || !eckey->pub_key) { ECerror(ERR_R_PASSED_NULL_PARAMETER); return 0; } if (EC_POINT_is_at_infinity(eckey->group, eckey->pub_key) > 0) { ECerror(EC_R_POINT_AT_INFINITY); goto err; } if ((ctx = BN_CTX_new()) == NULL) goto err; if ((point = EC_POINT_new(eckey->group)) == NULL) goto err; /* testing whether the pub_key is on the elliptic curve */ if (EC_POINT_is_on_curve(eckey->group, eckey->pub_key, ctx) <= 0) { ECerror(EC_R_POINT_IS_NOT_ON_CURVE); goto err; } /* testing whether pub_key * order is the point at infinity */ order = &eckey->group->order; if (BN_is_zero(order)) { ECerror(EC_R_INVALID_GROUP_ORDER); goto err; } if (!EC_POINT_mul(eckey->group, point, NULL, eckey->pub_key, order, ctx)) { ECerror(ERR_R_EC_LIB); goto err; } if (EC_POINT_is_at_infinity(eckey->group, point) <= 0) { ECerror(EC_R_WRONG_ORDER); goto err; } /* * in case the priv_key is present : check if generator * priv_key == * pub_key */ if (eckey->priv_key) { if (BN_cmp(eckey->priv_key, order) >= 0) { ECerror(EC_R_WRONG_ORDER); goto err; } if (!EC_POINT_mul(eckey->group, point, eckey->priv_key, NULL, NULL, ctx)) { ECerror(ERR_R_EC_LIB); goto err; } if (EC_POINT_cmp(eckey->group, point, eckey->pub_key, ctx) != 0) { ECerror(EC_R_INVALID_PRIVATE_KEY); goto err; } } ok = 1; err: BN_CTX_free(ctx); EC_POINT_free(point); return (ok); } int EC_KEY_set_public_key_affine_coordinates(EC_KEY * key, BIGNUM * x, BIGNUM * y) { BN_CTX *ctx = NULL; BIGNUM *tx, *ty; EC_POINT *point = NULL; int ok = 0; if (!key || !key->group || !x || !y) { ECerror(ERR_R_PASSED_NULL_PARAMETER); return 0; } ctx = BN_CTX_new(); if (!ctx) goto err; point = EC_POINT_new(key->group); if (!point) goto err; if ((tx = BN_CTX_get(ctx)) == NULL) goto err; if ((ty = BN_CTX_get(ctx)) == NULL) goto err; if (!EC_POINT_set_affine_coordinates(key->group, point, x, y, ctx)) goto err; if (!EC_POINT_get_affine_coordinates(key->group, point, tx, ty, ctx)) goto err; /* * Check if retrieved coordinates match originals: if not values are * out of range. */ if (BN_cmp(x, tx) || BN_cmp(y, ty)) { ECerror(EC_R_COORDINATES_OUT_OF_RANGE); goto err; } if (!EC_KEY_set_public_key(key, point)) goto err; if (EC_KEY_check_key(key) == 0) goto err; ok = 1; err: BN_CTX_free(ctx); EC_POINT_free(point); return ok; } const EC_GROUP * EC_KEY_get0_group(const EC_KEY * key) { return key->group; } int EC_KEY_set_group(EC_KEY * key, const EC_GROUP * group) { if (key->meth->set_group != NULL && key->meth->set_group(key, group) == 0) return 0; EC_GROUP_free(key->group); key->group = EC_GROUP_dup(group); return (key->group == NULL) ? 0 : 1; } const BIGNUM * EC_KEY_get0_private_key(const EC_KEY * key) { return key->priv_key; } int EC_KEY_set_private_key(EC_KEY * key, const BIGNUM * priv_key) { if (key->meth->set_private != NULL && key->meth->set_private(key, priv_key) == 0) return 0; BN_clear_free(key->priv_key); key->priv_key = BN_dup(priv_key); return (key->priv_key == NULL) ? 0 : 1; } const EC_POINT * EC_KEY_get0_public_key(const EC_KEY * key) { return key->pub_key; } int EC_KEY_set_public_key(EC_KEY * key, const EC_POINT * pub_key) { if (key->meth->set_public != NULL && key->meth->set_public(key, pub_key) == 0) return 0; EC_POINT_free(key->pub_key); key->pub_key = EC_POINT_dup(pub_key, key->group); return (key->pub_key == NULL) ? 0 : 1; } unsigned int EC_KEY_get_enc_flags(const EC_KEY * key) { return key->enc_flag; } void EC_KEY_set_enc_flags(EC_KEY * key, unsigned int flags) { key->enc_flag = flags; } point_conversion_form_t EC_KEY_get_conv_form(const EC_KEY * key) { return key->conv_form; } void EC_KEY_set_conv_form(EC_KEY * key, point_conversion_form_t cform) { key->conv_form = cform; if (key->group != NULL) EC_GROUP_set_point_conversion_form(key->group, cform); } void * EC_KEY_get_key_method_data(EC_KEY *key, void *(*dup_func) (void *), void (*free_func) (void *), void (*clear_free_func) (void *)) { void *ret; CRYPTO_r_lock(CRYPTO_LOCK_EC); ret = EC_EX_DATA_get_data(key->method_data, dup_func, free_func, clear_free_func); CRYPTO_r_unlock(CRYPTO_LOCK_EC); return ret; } void * EC_KEY_insert_key_method_data(EC_KEY * key, void *data, void *(*dup_func) (void *), void (*free_func) (void *), void (*clear_free_func) (void *)) { EC_EXTRA_DATA *ex_data; CRYPTO_w_lock(CRYPTO_LOCK_EC); ex_data = EC_EX_DATA_get_data(key->method_data, dup_func, free_func, clear_free_func); if (ex_data == NULL) EC_EX_DATA_set_data(&key->method_data, data, dup_func, free_func, clear_free_func); CRYPTO_w_unlock(CRYPTO_LOCK_EC); return ex_data; } void EC_KEY_set_asn1_flag(EC_KEY * key, int flag) { if (key->group != NULL) EC_GROUP_set_asn1_flag(key->group, flag); } int EC_KEY_precompute_mult(EC_KEY * key, BN_CTX * ctx) { if (key->group == NULL) return 0; return EC_GROUP_precompute_mult(key->group, ctx); } int EC_KEY_get_flags(const EC_KEY * key) { return key->flags; } void EC_KEY_set_flags(EC_KEY * key, int flags) { key->flags |= flags; } void EC_KEY_clear_flags(EC_KEY * key, int flags) { key->flags &= ~flags; }

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/WSLiveStreamExample/Pods/Headers/Public/WSLiveStream/GPUImageMovieWriter.h

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wenrisheng/WSLiveStream

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refs/heads/master

UTF-8

C

h

../../../../../WSLiveStream/Sources/Vendors/GPUImage/iOS/GPUImageMovieWriter.h

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/src/04_FILE_DIR/ftw8.c

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JmyTest/apue

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refs/heads/master

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C

c

/** * @file 测试DIR相关 * * apue示例程序 - ftw8.c * * @author Steve & r00tk1t * */ #include "apue.h" #include <dirent.h> #include <limits.h> #include <sys/stat.h> /* function type that is called for each filename */ typedef int Myfunc(const char *, const struct stat *, int); static Myfunc myfunc; static int myftw(char *, Myfunc *); static int dopath(Myfunc *); static long nreg, ndir, nblk, nchr, nfifo, nslink, nsock, ntot; int main(int argc, char *argv[]) { int ret; if (argc != 2) err_quit("usage: ftw <starting-pathname>"); ret = myftw(argv[1], myfunc); /* does it all */ ntot = nreg + ndir + nblk + nchr + nfifo + nslink + nsock; if (ntot == 0) ntot = 1; /* avoid divide by 0; print 0 for all counts */ printf("regular files = %7ld, %5.2f %%\n", nreg, nreg*100.0/ntot); printf("directories = %7ld, %5.2f %%\n", ndir, ndir*100.0/ntot); printf("block special = %7ld, %5.2f %%\n", nblk, nblk*100.0/ntot); printf("char special = %7ld, %5.2f %%\n", nchr, nchr*100.0/ntot); printf("FIFOs = %7ld, %5.2f %%\n", nfifo, nfifo*100.0/ntot); printf("symbolic links = %7ld, %5.2f %%\n", nslink, nslink*100.0/ntot); printf("sockets = %7ld, %5.2f %%\n", nsock, nsock*100.0/ntot); exit(ret); } /* * Descend through the hierarchy, starting at "pathname". * The caller's func() is called for every file. */ #define FTW_F 1 /* file other than directory */ #define FTW_D 2 /* directory */ #define FTW_DNR 3 /* directory that can't be read */ #define FTW_NS 4 /* file that we can't stat */ static char *fullpath; /* contains full pathname for every file */ static size_t pathlen; static int /* we return whatever func() returns */ myftw(char *pathname, Myfunc *func) { fullpath = path_alloc(&pathlen); /* malloc PATH_MAX+1 bytes */ /* ({Prog pathalloc}) */ if (pathlen <= strlen(pathname)) { pathlen = strlen(pathname) * 2; if ((fullpath = realloc(fullpath, pathlen)) == NULL) err_sys("realloc failed"); } strcpy(fullpath, pathname); return dopath(func); } /* * Descend through the hierarchy, starting at "fullpath". * If "fullpath" is anything other than a directory, we lstat() it, * call func(), and return. For a directory, we call ourself * recursively for each name in the directory. */ static int /* we return whatever func() returns */ dopath(Myfunc* func) { struct stat statbuf; struct dirent *dirp; DIR *dp; int ret, n; if (lstat(fullpath, &statbuf) < 0) /* stat error */ return(func(fullpath, &statbuf, FTW_NS)); if (S_ISDIR(statbuf.st_mode) == 0) /* not a directory */ return(func(fullpath, &statbuf, FTW_F)); /* * It's a directory. First call func() for the directory, * then process each filename in the directory. */ if ((ret = func(fullpath, &statbuf, FTW_D)) != 0) return(ret); n = strlen(fullpath); if (n + NAME_MAX + 2 > pathlen) { /* expand path buffer */ pathlen *= 2; if ((fullpath = realloc(fullpath, pathlen)) == NULL) err_sys("realloc failed"); } fullpath[n++] = '/'; fullpath[n] = 0; if ((dp = opendir(fullpath)) == NULL) /* can't read directory */ return(func(fullpath, &statbuf, FTW_DNR)); while ((dirp = readdir(dp)) != NULL) { if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) continue; /* ignore dot and dot-dot */ strcpy(&fullpath[n], dirp->d_name); /* append name after "/" */ if ((ret = dopath(func)) != 0) /* recursive */ break; /* time to leave */ } fullpath[n-1] = 0; /* erase everything from slash onward */ if (closedir(dp) < 0) err_ret("can't close directory %s", fullpath); return(ret); } static int myfunc(const char *pathname, const struct stat *statptr, int type) { switch (type) { case FTW_F: switch (statptr->st_mode & S_IFMT) { case S_IFREG: nreg++; break; case S_IFBLK: nblk++; break; case S_IFCHR: nchr++; break; case S_IFIFO: nfifo++; break; case S_IFLNK: nslink++; break; case S_IFSOCK: nsock++; break; case S_IFDIR: /* directories should have type = FTW_D */ err_dump("for S_IFDIR for %s", pathname); } break; case FTW_D: ndir++; break; case FTW_DNR: err_ret("can't read directory %s", pathname); break; case FTW_NS: err_ret("stat error for %s", pathname); break; default: err_dump("unknown type %d for pathname %s", type, pathname); } return(0); }

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sfaroult/sqlite_libs

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UTF-8

C

c

/* * pg_degrees.c * * This program is used in SQLite and will convert a number from radians to * degrees * * Input - A number in radians Output - The number in degrees * */ #include <stdio.h> #include <math.h> #include <ksu_common.h> /* * Converts a number from radians to degrees. */ extern void pg_degrees(sqlite3_context * context, int argc, sqlite3_value ** argv) { double x; if (ksu_prm_ok(context, argc, argv, "degrees", KSU_PRM_NUMERIC)) { x = sqlite3_value_double(argv[0]); sqlite3_result_double(context, ((x * 180) / M_PI)); } }

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/samples/platforms/zc702_hdmi/samples/motion_demo/hw/img_filters.h

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nguyencanhtrung/SDSoC

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refs/heads/master

UTF-8

C

h

/***************************************************************************** * * Author: Xilinx, Inc. (c) Copyright 2012 Xilinx Inc. * All rights reserved. * * This file may be used under the terms of the GNU General Public * License version 3.0 as published by the Free Software Foundation * and appearing in the file LICENSE.GPL included in the packaging of * this file. Please review the following information to ensure the * GNU General Public License version 3.0 requirements will be met. * http://www.gnu.org/copyleft/gpl.html. * * With respect to any license that requires Xilinx to make available to * recipients of object code distributed by Xilinx pursuant to such * license the corresponding source code, and if you desire to receive * such source code from Xilinx and cannot access the internet to obtain * a copy thereof, then Xilinx hereby offers (which offer is valid for as * long as required by the applicable license; and we may charge you the * cost thereof unless prohibited by the license) to provide you with a * copy of such source code; and to accept such offer send a letter * requesting such source code (please be specific by identifying the * particular Xilinx Software you are inquiring about (name and version * number), to: Xilinx, Inc., Legal Department, Attention: Software * Compliance Officer, 2100 Logic Drive, San Jose, CA U.S.A. 95124. * * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * * CRITICAL APPLICATIONS WARRANTIES * Xilinx products are not designed or intended to be fail-safe, or * for use in any application requiring fail-safe performance, such as * life-support or safety devices or systems, Class III medical devices, * nuclear facilities, applications related to the deployment of airbags, * or any other applications that could lead to death, personal injury, * or severe property or environmental damage (individually and * collectively, "Critical Applications"). Customer assumes the sole * risk and liability of any use of Xilinx products in Critical * Applications, subject only to applicable laws and regulations * governing limitations on product liability. * * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF * THIS FILE AT ALL TIMES. * * This file is a part of sobel_qt application, which is based in part * on the work of the Qwt project (http://qwt.sf.net). * *****************************************************************************/ /***************************************************************************** * * @file img_filters.h * * Header that provides sw sobel filter interface to the user. * ******************************************************************************/ #ifndef IMG_FILTERS_H_ #define IMG_FILTERS_H_ #ifdef __cplusplus extern "C" { #endif /* Sobel Modules declarations */ void img_process(unsigned int *rgb_prev_strm, unsigned int *rgb_in_strm, unsigned int *rgb_out_strm, int param0, int param1, int param2); #ifdef __cplusplus }; #endif #endif /* IMG_FILTERS_H_ */

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/0x07-pointers_arrays_strings/5-strstr.c

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no_license

JSalmen13/holbertonschool-low_level_programming

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refs/heads/master

UTF-8

C

c

#include "holberton.h" #include <stdio.h> /** * _strstr - find occurence * @haystack: str 1 * @needle: str 2 * Return: occurance */ char *_strstr(char *haystack, char *needle) { int i, j, k; j = 0; if (needle[0] == '\0') return (haystack); for (k = 0; needle[k]; k++) ; for (i = 0; haystack[i]; i++) { if (needle[0] == haystack[i]) { for (j = 0; needle[j]; j++) { if (needle[j] != haystack[i + j]) { break; } } } if (j == k) return (&haystack[i]); } return (0); }

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/User/bsp/bsp.c

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Shikunliu/Alcohol_vending_robot_flow_control_module

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6aa83e7f7533aa1de85e082f619435da9e512f53

refs/heads/master

GB18030

C

c

/* ********************************************************************************************************* * * 模块名称 : BSP模块 * 文件名称 : bsp.c * 版 本 : V1.0 * 说 明 : 这是硬件底层驱动程序模块的主文件。主要提供 bsp_Init()函数供主程序调用。 * 主程序的每个c文件可以在开头 添加 #include "bsp.h" 来包含所有的外设驱动模块。 * * 修改记录 : * 版本号 日期 作者 * V1.0 2017-12-01 Shikun Liu * ********************************************************************************************************* */ #include "bsp.h" void bsp_Init(void) { /* 由于ST固件库的启动文件已经执行了CPU系统时钟的初始化，所以不必再次重复配置系统时钟。 启动文件配置了CPU主时钟频率、内部Flash访问速度和可选的外部SRAM FSMC初始化。 系统时钟缺省配置为72MHz，如果需要更改，可以修改 system_stm32f10x.c 文件 */ /* 优先级分组设置为4 */ //NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); bsp_InitTimer(); BUTTON_Configuration(); EXTI_Configuration(); LEVEL_SENSOR_INPUT_Configuration(); NVIC_Configuration(); //测试额外timer，配置中断 RELAY_Configuration(); //继电器初始化 LED_Configuration(); //LED初始化 bsp_InitUart(); //串口初始化 } /***************************** (END OF FILE) *********************************/

12b1e23680b91fe0e3fff422a403c65ac2682969

07db481e38bb48a7f9323ae5dcdb8e4d82397a93

/LAB 4/Laborator4/Laborator4/P5_modificat_P1.c

4e92dfc1d9ebde32114d11928dcb0045dd6bbc2b

no_license

stefana-matei/TP

0b2618dbbb43fd1232843babab30b464384b6dd2

3552f5273bfad81745772b38a8626178344ead1e

refs/heads/master

UTF-8

C

c

/*Sa se modifice P1 astfel incat la adaugarea unui produs, daca numele respectiv exista deja in baza de date, acesta sa nu mai fie adaugat ci sa fie schimbat pretul vechi cu cel nou introdus.*/ #define _CRT_SECURE_NO_WARNINGS #include <stdio.h> #include <string.h> typedef struct { char nume[50]; float pret; } produse; int produs_deja_existent(char produs[50], produse *stock, int n) { int i; for (i = 0; i < n; i++) { if (strcmp(stock[i].nume, produs) == 0) { return i; } } return -1; } int main() { produse prds[100]; int i,optiune, n = 0,index; char nume_produs[50]; while (1) { printf("1.Adaugare "); printf("\n2.Afisare "); printf("\n0.Iesire \n\n"); printf(" Optiunea dvs : "); scanf("%d", &optiune); printf("\n"); switch (optiune) { case 1: getchar(); printf("Nume : "); gets(nume_produs); index = produs_deja_existent(nume_produs, prds, n); if (index >= 0) { printf("Produsul este deja in baza de date!\n"); printf("Noul pret: "); scanf("%g", &prds[index].pret); n--; } else { strcpy(prds[n].nume, nume_produs); printf("Pret: "); scanf("%g", &prds[n].pret); } n++; printf("\n"); break; case 2: for (i = 0; i < n; i++) { printf("%s %g\n", prds[i].nume, prds[i].pret); } break; case 0: exit(0); break; default: printf("\Optiunea nu exista!\n"); break; } } system("pause"); return 0; }

a49fb32d2aa5c80c41d8d8400291f07eae0ac4e5

54fad01b6a7bcd03ae081f9127b34399fb2d21bd

/Microchip/TCPIP-BSD/netpkt.h

5fa6c18efc64ded992fe232c7dbff4962e52aeae

no_license

douglaskatz/PIC32-Mass-Storage

442a227469945f83d55bd9fc65fede2046b9d1b4

fdcf4dfefae66f0b9ce41e792419c90bb4f1d833

refs/heads/master

WINDOWS-1252

C

h

/********************************************************************* * * Packet Buffer Header File * ********************************************************************* * FileName: NetPkt.h * Description: internal packet buffer definition * Company: Microchip Technology, Inc. * * Software License Agreement * * The software supplied herewith by Microchip Technology Incorporated * (the “Company”) for its PICmicro® Microcontroller is intended and * supplied to you, the Company’s customer, for use solely and * exclusively on Microchip PICmicro Microcontroller products. The * software is owned by the Company and/or its supplier, and is * protected under applicable copyright laws. All rights are reserved. * Any use in violation of the foregoing restrictions may subject the * user to criminal sanctions under applicable laws, as well as to * civil liability for the breach of the terms and conditions of this * license. * * THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * * $Id: NetPkt.h,v 1.4 2006/10/24 16:39:06 C12923 Exp $ * */ #ifndef __NET_PKT_H__ #define __NET_PKT_H__ typedef enum { // packet queueing masks ARP_QUE_MASK = 0x01, // packet part of the ARP queue MACTX_QUE_MASK = 0x02, // part of MAC TX queue CNXN_QUE_MASK = 0x04, // part of Conexion queue RXMSG_QUE_MASK = 0x08, // part of RX message queue // PKT_QUEUES_MASK = (ARP_QUE_MASK|MACTX_QUE_MASK|CNXN_QUE_MASK|RXMSG_QUE_MASK), // any queue mask // rx/tx packet flags PKT_FLAG_RX = 0x10, // it's an Rx packet PKT_FLAG_TX = 0x20, // it's an TX packet PKT_TX_AUTO_DEALLOC = 0x40, // TX packet can perform auto de-allocate after transfer PKT_FLAG_ZC_ALLOC = 0x80 // zero copy allocation needed // flags that are not stored in the buffer // used for allocation type }NET_PKT_FLAGS; // net packet flags typedef enum { BUFF_MGR_ALLOC = 0x01, // packet/buffer allocated by the stack manager, not by the user BUFF_ZC_ALLOC = 0x02, // buffer part of a zero copy operation: // for TX: a user supplied buffer // for RX: a buffer that was supplied to the Eth Controller and is sticky BUFF_ZC_WACK = 0x04, // ZC buffer waitig for the RX acknowledge // }NET_PKT_BUFF_FLAGS; // packet/buffer flags typedef struct { sBuffDcpt bDcpt; short int bFlags; // NET_PKT_BUFF_FLAGS value } __attribute__ ((__packed__)) pktMgrDcpt; // a packet manager descriptor typedef struct NetPacket { struct NetPacket *pNext; BYTE* pTransportLayer; BYTE* pNetworkLayer; #ifdef _STACK_USE_ZC pktMgrDcpt PktDcpt[2]; // - for TX: // if ZC is not supported/requested // NET_PKT is allocated to contain the whole packet // the 1st buffer descriptor pBuff=NET_PKT.pPktLoad, nBytes=PktLen; // the 2nd buffer descriptor pBuff=0, nBytes=0; // else (ZC) // NET_PKT is allocated to contain the headers (ETH, IP, UDP/TCP) // the 1st buffer descriptor pBuff=NET_PKT.pPktLoad, nBytes=headerLen; // the 2nd buffer descriptor pBuff=pUsrBuffer, nBytes=loadLen; // - for RX: // if ZC is not supported/requested or the received packet is split across // multiple buffers (depending on size of RX buffers) // NET_PKT is allocated to contain the whole packet // the 1st buffer descriptor pBuff=NET_PKT.pPktLoad, nBytes=PktLen; // the 2nd buffer descriptor pBuff=0, nBytes=0; // else (ZC && contiguous buffer) // NET_PKT is allocated to contain just the NET_PKT itself, with no data // the 1st buffer descriptor pBuff=0 and nBytes=0 // the 2nd buffer descriptor pBuff=the pointer to the Ethernet RX buffer, nBytes=pkt size pzSendAckF buffXmitAck; // the TX acknowledge call back function #else pktMgrDcpt PktDcpt[1]; // - for TX: everything in one large buffer. User buffer is copied here // - for RX: one large buffer. Whole packet copied here #endif // _STACK_USE_ZC struct NetPacket *pTcpNext; struct MCSocket * pOwnerSocket; DWORD TCPACKNum; TICK TimeStamp; //Time when rcvd or queued for xmit TICK ARPTickStart; WORD PktLen; BYTE PktType; // valid only for Rx Packets BYTE PktFlags; // a NET_PKT_FLAGS value //real packet data //DO NOT ADD FIELDS BELOW THIS LINE #ifdef _STACK_USE_ZC struct NetPacket *pOwner; // owner of the RX buffer #endif DWORD pPktLoad[0]; }NET_PKT; #endif

1206ab3f7db33a292315f31fc8cfaf33ff065518

43369807c33c0643b07033d9d4e200debe302862

/eve_server/sample/EIFGENs/sample/W_code/C12/ty389d.c

44b0c766c38058382973463ff44435bb385e484a

no_license

jvelilla/Eiffel_Web_Server

8ebcc06b3d81ea1bf4bba9a557ad5b753db6d0c6

d194d75ff2322a0e195a2d23aa063943660bce75

refs/heads/master

UTF-8

C

c

/* * Class reference TYPED_POINTER [POINTER] */ #include "eif_macros.h" #ifdef __cplusplus extern "C" { #endif static EIF_TYPE_INDEX gen_type0_389 [] = {0xFF11,170,0xFFFF}; static EIF_TYPE_INDEX gen_type1_389 [] = {0xFF11,180,388,160,0xFFFF}; static EIF_TYPE_INDEX gen_type2_389 [] = {0xFF11,388,160,0xFFFF}; static EIF_TYPE_INDEX gen_type3_389 [] = {0,0xFFFF}; static EIF_TYPE_INDEX gen_type4_389 [] = {0,0xFFFF}; static EIF_TYPE_INDEX gen_type5_389 [] = {0xFF11,388,160,0xFFFF}; static EIF_TYPE_INDEX gen_type6_389 [] = {0xFF11,388,160,0xFFFF}; static EIF_TYPE_INDEX gen_type7_389 [] = {0,0xFFFF}; static EIF_TYPE_INDEX gen_type8_389 [] = {0xFF11,11,0xFFFF}; static EIF_TYPE_INDEX gen_type9_389 [] = {0xFF11,170,0xFFFF}; static EIF_TYPE_INDEX gen_type10_389 [] = {0xFF11,170,0xFFFF}; static EIF_TYPE_INDEX gen_type11_389 [] = {0xFF11,10,0xFFFF}; static EIF_TYPE_INDEX gen_type12_389 [] = {0xFF11,388,160,0xFFFF}; static EIF_TYPE_INDEX gen_type13_389 [] = {0xFF11,388,160,0xFFFF}; static EIF_TYPE_INDEX gen_type14_389 [] = {0xFF11,159,0xFFFF}; static EIF_TYPE_INDEX gen_type15_389 [] = {0xFFF8,1,0xFFFF}; static struct desc_info desc_389[] = { {(BODY_INDEX) -1, (BODY_INDEX) -1, INVALID_DTYPE, NULL}, {0, (BODY_INDEX)-1, 170, gen_type0_389}, {1, (BODY_INDEX)-1, 180, gen_type1_389}, {2, (BODY_INDEX)-1, 154, NULL}, {3, (BODY_INDEX)-1, 154, NULL}, {8767, (BODY_INDEX)-1, 154, NULL}, {5, (BODY_INDEX)-1, 154, NULL}, {6, (BODY_INDEX)-1, 154, NULL}, {7, (BODY_INDEX)-1, 154, NULL}, {8, (BODY_INDEX)-1, 154, NULL}, {9, (BODY_INDEX)-1, 154, NULL}, {10, (BODY_INDEX)-1, 388, gen_type2_389}, {11, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {12, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {13, (BODY_INDEX)-1, 0, gen_type3_389}, {14, (BODY_INDEX)-1, 0, gen_type4_389}, {15, (BODY_INDEX)-1, 388, gen_type5_389}, {16, (BODY_INDEX)-1, 388, gen_type6_389}, {17, (BODY_INDEX)-1, 0, gen_type7_389}, {18, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {19, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {20, (BODY_INDEX)-1, 11, gen_type8_389}, {8782, (BODY_INDEX)-1, 170, gen_type9_389}, {22, (BODY_INDEX)-1, 170, gen_type10_389}, {23, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {24, (BODY_INDEX)-1, 10, gen_type11_389}, {25, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {26, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {27, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {28, (BODY_INDEX)-1, 388, gen_type12_389}, {29, (BODY_INDEX)-1, 160, NULL}, {30, (BODY_INDEX)-1, 388, gen_type13_389}, {31, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {32, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {549, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {550, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {551, (BODY_INDEX)-1, 154, NULL}, {8765, (BODY_INDEX)-1, 121, NULL}, {8768, (BODY_INDEX)-1, 154, NULL}, {8764, 0, 160, NULL}, {8766, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8769, (BODY_INDEX)-1, 154, NULL}, {8770, (BODY_INDEX)-1, 160, NULL}, {8771, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8772, (BODY_INDEX)-1, 159, gen_type14_389}, {8773, (BODY_INDEX)-1, 121, NULL}, {8774, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8775, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8776, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8777, (BODY_INDEX)-1, 160, NULL}, {8778, (BODY_INDEX)-1, 160, NULL}, {8779, (BODY_INDEX)-1, 160, NULL}, {8780, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8781, (BODY_INDEX)-1, 154, NULL}, {8783, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8784, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8758, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {8759, (BODY_INDEX)-1, 121, NULL}, {8760, (BODY_INDEX)-1, 160, NULL}, {8761, (BODY_INDEX)-1, 160, NULL}, {8762, (BODY_INDEX)-1, 160, NULL}, {8763, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, NULL}, {(BODY_INDEX)-1, (BODY_INDEX)-1, (EIF_TYPE_INDEX)-1, gen_type15_389}, }; extern void Init389(void); void Init389(void) { IDSC(desc_389, 0, 388); IDSC(desc_389 + 1, 2, 388); IDSC(desc_389 + 34, 123, 388); IDSC(desc_389 + 37, 49, 388); IDSC(desc_389 + 39, 43, 388); IDSC(desc_389 + 62, 11, 388); } #ifdef __cplusplus } #endif

93f84bf7ae6981cb4d87eb0b68cc9fee1818b8af

976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f

/source/SoftEtherVPN/src/vpntest/extr_vpntest.c_memory_leak_test.c

05a944d2042c20c26f69b27e3621754702f08c15

no_license

isabella232/AnghaBench

7ba90823cf8c0dd25a803d1688500eec91d1cf4e

9a5f60cdc907a0475090eef45e5be43392c25132

refs/heads/master

UTF-8

C

c

#define NULL ((void*)0) typedef unsigned long size_t; // Customize by platform. typedef long intptr_t; typedef unsigned long uintptr_t; typedef long scalar_t__; // Either arithmetic or pointer type. /* By default, we understand bool (as a convenience). */ typedef int bool; #define false 0 #define true 1 /* Forward declarations */ /* Type definitions */ typedef int /*<<< orphan*/ UINT ; /* Variables and functions */ char* Malloc (int) ; int /*<<< orphan*/ Print (char*) ; void memory_leak_test(UINT num, char **arg) { char *a = Malloc(1); Print("Hello, I am the great dictator of this kingdom!\n"); Print("Just now I called Malloc(1) and never free! Ha ha ha !!\n"); }

f21babab8985e21225a8d4f424c90e47ef27adff

c9407242b82993b5c5893c40b1f5a1fe9afb25b9

/Core/Src/system_stm32f4xx.c

4eecdf7186d6c586fbd0c895f6591f69faabcc34

no_license

softqmisg/acm_HW02_Bootloader_Usage

354487b82d4dce9e3add825e45b5d123fad6d67c

fc3c52fb6b948dbaf6e2dca15a028abbc33a228e

refs/heads/master

UTF-8

C

c

/** ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from * user application: * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * ****************************************************************************** * @attention * * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx_system * @{ */ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ #include "stm32f4xx.h" #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Defines * @{ */ /************************* Miscellaneous Configuration ************************/ /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ STM32F412Zx || STM32F412Vx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* #define DATA_IN_ExtSDRAM */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ STM32F479xx */ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Variables * @{ */ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ uint32_t SystemCoreClock = 16000000; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} */ /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes * @{ */ #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the FPU setting, vector table location and External memory * configuration. * @param None * @retval None */ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else //SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * depends on the application requirements), user has to ensure that HSE_VALUE * is same as the real frequency of the crystal used. Otherwise, this function * may have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; break; case 0x04: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; break; case 0x08: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) { /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; SystemCoreClock = pllvco/pllp; break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK frequency --------------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK frequency */ SystemCoreClock >>= tmp; } #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. * This function configures the external memories (SRAM/SDRAM) * This SRAM/SDRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { __IO uint32_t tmp = 0x00; register uint32_t tmpreg = 0, timeout = 0xFFFF; register __IO uint32_t index; /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001F8; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); FMC_Bank5_6->SDCR[0] = 0x000019E4; FMC_Bank5_6->SDTR[0] = 0x01115351; /* SDRAM initialization sequence */ /* Clock enable command */ FMC_Bank5_6->SDCMR = 0x00000011; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); /* PALL command */ FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); /* Disable write protection */ tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001091; FMC_Bank1->BTCR[3] = 0x00110212; FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ (void)(tmp); } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. * This function configures the external memories (SRAM/SDRAM) * This SRAM/SDRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { __IO uint32_t tmp = 0x00; #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #if defined (DATA_IN_ExtSDRAM) register uint32_t tmpreg = 0, timeout = 0xFFFF; register __IO uint32_t index; #if defined(STM32F446xx) /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface clock */ RCC->AHB1ENR |= 0x0000007D; #else /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001F8; #endif /* STM32F446xx */ /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); #if defined(STM32F446xx) /* Connect PAx pins to FMC Alternate function */ GPIOA->AFR[0] |= 0xC0000000; GPIOA->AFR[1] |= 0x00000000; /* Configure PDx pins in Alternate function mode */ GPIOA->MODER |= 0x00008000; /* Configure PDx pins speed to 50 MHz */ GPIOA->OSPEEDR |= 0x00008000; /* Configure PDx pins Output type to push-pull */ GPIOA->OTYPER |= 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOA->PUPDR |= 0x00000000; /* Connect PCx pins to FMC Alternate function */ GPIOC->AFR[0] |= 0x00CC0000; GPIOC->AFR[1] |= 0x00000000; /* Configure PDx pins in Alternate function mode */ GPIOC->MODER |= 0x00000A00; /* Configure PDx pins speed to 50 MHz */ GPIOC->OSPEEDR |= 0x00000A00; /* Configure PDx pins Output type to push-pull */ GPIOC->OTYPER |= 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOC->PUPDR |= 0x00000000; #endif /* STM32F446xx */ /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[1] = 0xCC000CCC; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xA02A000A; /* Configure PDx pins speed to 50 MHz */ GPIOD->OSPEEDR = 0xA02A000A; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; /* Configure PEx pins speed to 50 MHz */ GPIOE->OSPEEDR = 0xAAAA800A; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F469xx) || defined(STM32F479xx) /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); /* Configure and enable SDRAM bank1 */ #if defined(STM32F446xx) FMC_Bank5_6->SDCR[0] = 0x00001954; #else FMC_Bank5_6->SDCR[0] = 0x000019E4; #endif /* STM32F446xx */ FMC_Bank5_6->SDTR[0] = 0x01115351; /* SDRAM initialization sequence */ /* Clock enable command */ FMC_Bank5_6->SDCMR = 0x00000011; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); /* PALL command */ FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Auto refresh command */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x000000F3; #else FMC_Bank5_6->SDCMR = 0x00000073; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* MRD register program */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x00044014; #else FMC_Bank5_6->SDCMR = 0x00046014; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; #if defined(STM32F446xx) FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); #else FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); #endif /* STM32F446xx */ /* Disable write protection */ tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #endif /* DATA_IN_ExtSDRAM */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) #if defined(DATA_IN_ExtSRAM) /*-- GPIOs Configuration -----------------------------------------------------*/ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHB1ENR |= 0x00000078; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[1] = 0xCCCC0000; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA000AAA; /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xFF000FFF; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[1] = 0x000000C0; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00085AAA; /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000CAFFF; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /*-- FMC/FSMC Configuration --------------------------------------------------*/ /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001091; FMC_Bank1->BTCR[3] = 0x00110212; FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ || defined(STM32F412Zx) || defined(STM32F412Vx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); /* Configure and enable Bank1_SRAM2 */ FSMC_Bank1->BTCR[2] = 0x00001011; FSMC_Bank1->BTCR[3] = 0x00000201; FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ (void)(tmp); } #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Administrator@DESKTOP-NBKRGK5

c655d49b82f8a3c79207d1ad025b2ae446a8603d

5792b184e71a9de7779e0bd21b6833f8ddfdb4b5

/sysvr3/301/usr/src/uts/3b2/sys/immu.h

52eb6697d6a3e4a1d79ccd47b245dec33c855124

no_license

ryanwoodsmall/oldsysv

1637a3e62bb1b9426a224e832f44a46f1e1a31d4

e68293af91e2dc39f5f29c20d7e429f9e0cabc75

refs/heads/master

UTF-8

C

h

/* Copyright (c) 1984 AT&T */ /* All Rights Reserved */ /* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF AT&T */ /* The copyright notice above does not evidence any */ /* actual or intended publication of such source code. */ #ident "@(#)kern-port:sys/immu.h 10.5" /* * Page Descriptor (Table) Entry Definitions */ typedef union pde { /* page descriptor (table) entry */ /* */ /* +---------------------+---+--+--+--+-+--+-+-+-+-+ */ /* | pfn |lck|nr| | |r|cw| |l|m|p| */ /* +---------------------+---+--+--+--+-+--+-+-+-+-+ */ /* 21 1 1 1 2 1 1 1 1 1 1 */ /* */ struct { uint pg_pfn : 21, /* Physical page frame number */ pg_lock : 1, /* Lock in core (software) */ pg_ndref : 1, /* Needs reference (software). */ : 1, /* Unused software bit. */ : 2, /* Reserved by hardware. */ pg_ref : 1, /* Page has been referenced */ pg_cw : 1, /* Copy on write (fault) */ : 1, /* Reserved by hardware. */ pg_last : 1, /* Last (partial) page in segment */ pg_mod : 1, /* Page has been modified */ pg_pres : 1; /* Page is present in memory */ } pgm; struct { uint pg_pde; /* Full page descriptor (table) entry */ } pgi; } pde_t; #define pg_v pg_pres /* present bit = valid bit */ /* * Page Table */ #define NPGPT 64 /* Nbr of pages per page table (seg). */ typedef union ptbl { int page[NPGPT]; } ptbl_t; /* Page descriptor (table) entry dependent constants */ #define NBPP 2048 /* Number of bytes per page */ #define NBPPT 256 /* Number of bytes per page table */ #define BPTSHFT 8 /* LOG2(NBPPT) if exact */ #define NDPP 4 /* Number of disk blocks per page */ #define DPPSHFT 2 /* Shift for disk blocks per page. */ #define PNUMSHFT 11 /* Shift for page number from addr. */ #define PNUMMASK 0x3F /* Mask for page number in segment. */ #define POFFMASK 0x7FF /* Mask for offset into page. */ #define PNDXMASK 0x7FFFF /* Mask for page index into section.*/ #define PGFNMASK 0x1FFFFF /* Mask page frame nbr after shift. */ #define NPTPP 8 /* Nbr of page tables per page. */ #define NPTPPSHFT 3 /* Shift for NPTPP. */ /* Page descriptor (table) entry field masks */ #define PG_ADDR 0xFFFFF800 /* physical page address */ #define PG_LOCK 0x00000400 /* page lock bit (software) */ #define PG_NDREF 0x00000200 /* need reference bit (software) */ #define PG_REF 0x00000020 /* reference bit */ #define PG_COPYW 0x00000010 /* copy on write bit */ #define PG_LAST 0x00000004 /* Last page bit */ #define PG_M 0x00000002 /* modify bit */ #define PG_P 0x00000001 /* page present bit */ #define ONEPAGE 255 #define DZ_PAGE (unsigned char) 8 #define PTSIZE 256 /* page table size in bytes */ #define PTSZSHFT 8 /* page table size shift count */ /* byte addr to virtual page */ #define pnum(X) ((uint)(X) >> PNUMSHFT) /* page offset */ #define poff(X) ((uint)(X) & POFFMASK) /* The page number within a section. */ #define pgndx(X) (((X) >> PNUMSHFT) & PNDXMASK) /* Round up page table address */ #define ptround(p) ((int *) (((int)p + PTSIZE-1) & ~(PTSIZE-1))) /* Round down page table address */ #define ptalign(p) ((int *) ((int)p & ~(PTSIZE-1))) /* Disk blocks (sectors) and pages. */ #define ptod(PP) ((PP) << DPPSHFT) #define dtop(DD) (((DD) + NDPP - 1) >> DPPSHFT) #define dtopt(DD) ((DD) >> DPPSHFT) /* Disk blocks (sectors) and bytes. */ #define dtob(DD) ((DD) << SCTRSHFT) #define btod(BB) (((BB) + NBPSCTR - 1) >> SCTRSHFT) #define btodt(BB) ((BB) >> SCTRSHFT) /* Page tables (64 entries == 256 bytes) to pages. */ #define pttopgs(X) ((X + NPTPP - 1) >> NPTPPSHFT) #define pttob(X) ((X) << BPTSHFT) #define btopt(X) (((X) + NBPPT - 1) >> BPTSHFT) union ptbl *getptbl(); /* page table allocator */ extern int nptalloced; extern int nptfree; /* Form page descriptor (table) entry from modes and page frame ** number */ #define mkpde(mode,pfn) (mode | ((pfn) << PNUMSHFT)) /* The following macros are used to check the value * of the bits in a page descriptor (table) entry */ #define pg_isvalid(pde) ((pde)->pgm.pg_pres) #define pg_islocked(pde) ((pde)->pgm.pg_lock) /* The following macros are used to set the value * of the bits in a page descrptor (table) entry * * Atomic instruction is available to clear the present bit, * other bits are set or cleared in a word operation. */ #define pg_setvalid(P) ((P)->pgi.pg_pde |= PG_P) /* Set valid bit. */ #define pg_clrvalid(P) ((P)->pgi.pg_pde &= ~PG_P) /* Clear valid bit. */ #define pg_setndref(P) ((P)->pgi.pg_pde |= PG_NDREF) /* Set need ref bit. */ #define pg_clrndref(P) ((P)->pgi.pg_pde &= ~PG_NDREF) /* Clr need ref bit. */ #define pg_setlock(P) ((P)->pgi.pg_pde |= PG_LOCK) /* Set lock bit. */ #define pg_clrlock(P) ((P)->pgi.pg_pde &= ~PG_LOCK) /* Clear lock bit. */ #define pg_setmod(P) ((P)->pgi.pg_pde |= PG_M) /* Set modify bit. */ #define pg_clrmod(P) ((P)->pgi.pg_pde &= ~PG_M) /* Clear modify bit. */ #define pg_setcw(P) ((P)->pgi.pg_pde |= PG_COPYW) /* Set copy on write.*/ #define pg_clrcw(P) ((P)->pgi.pg_pde &= ~PG_COPYW) /* Clr copy on write.*/ #define pg_setref(P) ((P)->pgi.pg_pde |= PG_REF) /* Set ref bit. */ #define pg_clrref(P) ((P)->pgi.pg_pde &= ~PG_REF) /* Clear ref bit. */ #define pg_setprot(P,b) /* * Segment Descriptor (Table) Entry Definitions */ typedef struct sde { /* segment descriptor (table) entry */ /* */ /* +--------+--------------+--+--------+ +--------------------------------+ */ /* | prot | len | | flags | | address | */ /* +--------+--------------+--+--------+ +--------------------------------+ */ /* 8 14 2 8 32 */ /* */ /* +--------------------------+-+-+-+ */ /* (V0): | |N|W|S| */ /* +--------------------------+-+-+-+ */ /* 29 1 1 1 */ /* */ uint seg_prot : 8, /* Segment protection bits */ seg_len : 14, /* Segment length in doublewords */ : 2, /* Reserved */ seg_flags : 8; /* Segment descriptor flags */ union { uint address; /* Address of PDT or physical segment (cont.) */ struct { uint : 29, /* Not used */ wanted : 1, /* "N" bit */ shmswap : 1, /* "W" bit */ sanity : 1; /* "S" bit */ } V0; } wd2; } sde_t; /* access modes */ #define KNONE (unsigned char) 0x00 #define KEO (unsigned char) 0x40 /* KRO on WE32000 */ #define KRE (unsigned char) 0x80 #define KRWE (unsigned char) 0xC0 /* KRW on WE32000 */ #define UNONE (unsigned char) 0x00 #define UEO (unsigned char) 0x01 /* URO on WE32000 */ #define URE (unsigned char) 0x02 #define URWE (unsigned char) 0x03 /* URW on WE32000 */ #define UACCESS (unsigned char) 0x03 #define KACCESS (unsigned char) 0xC0 #define SEG_RO (KRWE|URE) #define SEG_RW (KRWE|URWE) /* descriptor bits */ #define SDE_I_bit (unsigned char) 0x80 #define SDE_V_bit (unsigned char) 0x40 #define SDE_T_bit (unsigned char) 0x10 #define SDE_C_bit (unsigned char) 0x04 #define SDE_P_bit (unsigned char) 0x01 #define SDE_flags (unsigned char) 0x41 /* sets V_bit and P_bit */ #define SDE_kflags (unsigned char) 0x45 /* sets V_bit, C_bit and */ /* P_bit. */ #define SDE_SOFT 7 #define isvalid(sde) ((sde)->seg_flags & SDE_V_bit) #define indirect(sde) ((sde)->seg_flags & SDE_I_bit) #define iscontig(sde) ((sde)->seg_flags & SDE_C_bit) #define istrap(sde) ((sde)->seg_flags & SDE_T_bit) #define segbytes(sde) (int)((((sde)->seg_len) + 1) << 3) #define lastpg(sde) (((sde)->seg_len) >> 8) #define u_access(sde) (((sde)->seg_prot) & UACCESS) #define k_access(sde) (((sde)->seg_prot) & KACCESS) #define segindex(addr) ((int)addr & MSK_IDXSEG) #define sde_clrvalid(sde) ((sde)->seg_flags &= ~SDE_V_bit) /* Segment descriptor (table) dependent constants. */ #define NBPS 0x20000 /* Number of bytes per segment */ #define SNUMSHFT 17 /* Shift for segment number from address. */ #define SNUMMASK 0x1FFF /* Mask for segment number after shift. */ #define SOFFMASK 0x1FFFF /* Mask for offset into segment. */ #define PPSSHFT 6 /* Shift for pages per segment. */ #define snum(X) (((uint)(X) >> SNUMSHFT) & SNUMMASK) #define soff(X) ((uint)(X) & SOFFMASK) /* * Memory Management Unit Definitions */ typedef struct _VAR { /* virtual address */ uint v_sid : 2, /* section number */ v_ssl : 13, /* segment number */ v_psl : 6, /* page number */ v_byte : 11; /* offset within page */ } VAR; /* masks to extract portions of a VAR */ #define MSK_IDXSEG 0x1ffff /* lower 17 bits == PSL || BYTE */ typedef struct _FLTCR { /* fault code register */ uint : 21, reqacc : 4, xlevel : 2, ftype : 5; } FLTCR; /* access types */ #define AT_SPOPWRITE 1 #define AT_SPOPFTCH 3 #define AT_ADFTCH 8 #define AT_OPFTCH 9 #define AT_WRITE 11 #define AT_IFTCH 13 #define AT_IFAD 12 #define AT_IPFTCH 14 #define AT_MT 0 /* access execution level */ #define XLVL_K 0 #define XLVL_U 3 /* Fault types */ #define F_NONE 0x0 #define F_MPROC 0x1 #define F_RMUPDATE 0x2 #define F_SDTLEN 0x3 #define F_PWRITE 0x4 #define F_PDTLEN 0x5 #define F_INVALID 0x6 #define F_SEG_N_P 0x7 #define F_OBJECT 0x8 #define F_PDT_N_P 0x9 #define F_P_N_P 0xa #define F_INDIRECT 0xb #define F_ACCESS 0xd #define F_OFFSET 0xe #define F_ACC_OFF 0xf #define F_D_P_HIT 0x1f typedef struct _CONFIG { /* configuration register */ uint : 30, ref : 1, mod : 1; } CR; typedef int SRAMA; /* Segment descriptor table address */ typedef struct _SRAMB { /* SRAMB Area */ /* * +---------+-------------+----------+ * | reserve | # segs | reserve | * +---------+-------------+----------+ * 9 13 10 */ unsigned int : 9; /* reserved */ unsigned int SDTlen : 13; /* number of segments in section */ unsigned int : 10; /* reserved */ } SRAMB; /* Virtual start address of sections */ #define VSECT0 0x00000000 #define VSECT1 0x40000000 #define VSECT2 0x80000000 #define VSECT3 0xC0000000 #define SRAMBSHIFT 10 #define MAXSDTSEG 8192 /* Maxmum number of SDT entries */ #define OFF 0 #define ON 1 /* MMU-specific addresses */ extern char *mmusrama, *mmusramb, *mmufltcr, *mmufltar, *mmucr, *mmuvar; #define srama ((SRAMA *) (&mmusrama)) #define sramb ((SRAMB *) (&mmusramb)) #define fltcr ((FLTCR *) (&mmufltcr)) #define fltar ((int *) (&mmufltar)) #define crptr ((CR *) (&mmucr)) #define varptr ((int *) (&mmuvar)) /* * Peripheral mode functions */ #define flushaddr(vaddr) (*((int *)(varptr)) = (int)(vaddr)) #define flushsect(sectno) (*((SRAMA *)(srama + (sectno))) = \ (*(SRAMA *)(srama + (sectno)))) /* The following variables describe the memory managed by ** the kernel. This includes all memory above the kernel ** itself. */ extern int kpbase; /* The address of the start of */ /* the first physical page of */ /* memory above the kernel. */ /* Physical memory from here to */ /* the end of physical memory */ /* is represented in the pfdat. */ extern int syssegs[]; /* Start of the system segment */ /* from which kernel space is */ /* allocated. The actual value */ /* is defined in the vuifile. */ extern int win_ublk[]; /* A window into which a */ /* u-block can be mapped. */ extern pde_t *kptbl; /* Kernel page table. Used to */ /* map sysseg. */ extern int maxmem; /* Maximum available free */ /* memory. */ extern int freemem; /* Current free memory. */ extern int availrmem; /* Available resident (not */ /* swapable) memory in pages. */ extern int availsmem; /* Available swapable memory in */ /* pages. */ /* Conversion macros */ /* Get page number from system virtual address. */ #define svtop(X) ((uint)(X) >> PNUMSHFT) /* Get system virtual address from page number. */ #define ptosv(X) ((uint)(X) << PNUMSHFT) /* These macros are used to map between kernel virtual ** and physical address. Note that all of physical ** memory is mapped into kernel virtual address space ** in segment zero at the actual physical address of ** the start of memory which is MAINSTORE. */ #define kvtophys(vaddr) (svirtophys(vaddr)) #define phystokv(paddr) (paddr) /* Between kernel virtual address and physical page frame number. */ #define kvtopfn(vaddr) (svirtophys(vaddr) >> PNUMSHFT) #define pfntokv(pfn) ((pfn) << PNUMSHFT) /* Between kernel virtual addresses and the kernel ** segment table entry. */ #define kvtokstbl(vaddr) (&((sde_t *)(*(srama + 1)))[snum(vaddr)]) /* Between kernel virtual addresses and the kernel page ** table. */ #define kvtokptbl(X) (&kptbl[pgndx((uint)(X) - (uint)syssegs)]) /* The following routines are involved with the pfdat ** table described in pfdat.h */ #define kvtopfdat(kv) (&pfdat[kvtopfn(kv) - btoc(kpbase)]) #define pfntopfdat(pfn) (&pfdat[pfn - btoc(kpbase)]) #define pfdattopfn(pfd) (pfd - pfdat + btoc(kpbase)) /* Test whether a virtual address is in the kernel dynamically ** allocated area. */ #define iskvir(va) ((secnum((uint)va) == SCN1) && \ (uint)va >= (uint)syssegs) /* * vatosde(v) * returns the segment descriptor entry location * of the virtual address v. */ sde_t *vatosde(); /* * pde_t * * svtopde(v) * returns the pde entry location of v. * * This macro works only with paged virtual address. */ #define svtopde(v) ((pde_t *)(phystokv(vatosde(v)->wd2.address)) + pnum(soff(v))) /* * svtopfn(v) */ #define svtopfn(v) (pnum(svirtophys(v))) /* Page frame number to kernel pde. */ #define pfntokptbl(P) (kvtokptbl(pfntokv(P))) /* flags used in ptmemall() call */ #define PHYSCONTIG 02 #define NOSLEEP 01 /* Section Id used in flushsect() and loadmmu() */ #define SCN0 0 #define SCN1 1 #define SCN2 2 #define SCN3 3 /* Load the mmu registers for a section with the address ** and length found in the proc table. This is a macro ** rather than a function since it speeds up context ** switches by eliminating the subroutine linkage. */ #define loadmmu(p, section) \ { \ register int index; \ register int ipl; \ \ ipl = spl7(); \ index = (section) - SCN2; \ \ if (((int *)(p)->p_sramb)[index] != -1) { \ srama[section] = (p)->p_srama[index]; \ sramb[section] = (p)->p_sramb[index]; \ } \ splx(ipl); \ }

2022b236904d972eee5a2155c02c505b674f96f6

4344664b8b1ab4cfce7ff90d4eafda90cb06cae8

/main.c

b6cb8929f490443d43699e60d03a4b2a9f14a741

no_license

mhmmdmngl/StackArray

41270483a9996236fc074fd0a1f3d2c21d9f65ed

30e74327b91174656d936fb820f47f83f00d5cf6

refs/heads/master

UTF-8

C

c

#include <stdio.h> #define ARRAY_SIZE 10 int array[ARRAY_SIZE]; int top = -1; int push(int data) { //we check if stack already full //top + 1 means getting new top index after push data for stack if(top + 1 >= ARRAY_SIZE) { printf("\nStack overflow...."); return top; } //push operation made here, we just add at top + 1 index array[top+1] = data; top++; return top; } int pop() { // top == -1 means stack is empty if(top - 1 < -1) { printf("Stack is empty"); return top; } array[top] = -1; top--; return top; } int peek() { return top; } void printStack() { for(int i = top; i >= 0; i--) { if(i == top) { printf("\n %d ==> Top", array[i]); } else { printf("\n %d", array[i]); } } } int main() { }

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/libs/STLPort-4.0/stlport/stl/_threads.c

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rickyharis39/nolf2

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refs/heads/master

UTF-8

C

c

/* * * * Copyright (c) 1994 * Hewlett-Packard Company * * Copyright (c) 1996,1997 * Silicon Graphics Computer Systems, Inc. * * Copyright (c) 1997 * Moscow Center for SPARC Technology * * Copyright (c) 1999 * Boris Fomitchev * * This material is provided "as is", with absolutely no warranty expressed * or implied. Any use is at your own risk. * * Permission to use or copy this software for any purpose is hereby granted * without fee, provided the above notices are retained on all copies. * Permission to modify the code and to distribute modified code is granted, * provided the above notices are retained, and a notice that the code was * modified is included with the above copyright notice. * */ #ifndef __STL_THREADS_C #define __STL_THREADS_C # if defined (__BUILDING_STLPORT) || ! defined (__SGI_STL_OWN_IOSTREAMS) __STL_BEGIN_NAMESPACE # if ( __STL_STATIC_TEMPLATE_DATA > 0 ) # if defined (__STL_PTHREADS) || defined (__STL_UITHREADS) template<int __dummy> _STL_STATIC_MUTEX _Swap_lock_struct<__dummy>::_S_swap_lock __STL_MUTEX_INITIALIZER; # endif template <int __inst> unsigned _STL_mutex_spin<__inst>::__max = _STL_mutex_spin<__inst>::__low_max; template <int __inst> unsigned _STL_mutex_spin<__inst>::__last = 0; # else /* ( __STL_STATIC_TEMPLATE_DATA > 0 ) */ # if defined (__STL_PTHREADS) || defined (__STL_UITHREADS) __DECLARE_INSTANCE(_STL_STATIC_MUTEX, _Swap_lock_struct<0>::_S_swap_lock, __STL_MUTEX_INITIALIZER ); # endif /* __STL_PTHREADS */ __DECLARE_INSTANCE(unsigned, _STL_mutex_spin<0>::__max, =30); __DECLARE_INSTANCE(unsigned, _STL_mutex_spin<0>::__last, =0); # endif /* ( __STL_STATIC_TEMPLATE_DATA > 0 ) */ #if defined(__STL_SGI_THREADS) || defined(__STL_WIN32THREADS) template <int __inst> void __STL_CALL _STL_mutex_spin<__inst>::_S_nsec_sleep(int __log_nsec) { # ifdef __STL_SGI_THREADS struct timespec __ts; /* Max sleep is 2**27nsec ~ 60msec */ __ts.tv_sec = 0; __ts.tv_nsec = 1 << __log_nsec; nanosleep(&__ts, 0); # elif defined(__STL_WIN32THREADS) if (__log_nsec <= 20) { Sleep(0); } else { Sleep(1 << (__log_nsec - 20)); } # else # error unimplemented # endif } template <int __inst> void __STL_CALL _STL_mutex_spin<__inst>::_M_do_lock(volatile unsigned long* __lock) { #if defined(__STL_SGI_THREADS) || defined(__STL_WIN32THREADS) if (_Atomic_swap((unsigned long*)__lock, 1)) { unsigned __my_spin_max = _STL_mutex_spin<0>::__max; unsigned __my_last_spins = _STL_mutex_spin<0>::__last; volatile unsigned __junk = 17; // Value doesn't matter. unsigned __i; for (__i = 0; __i < __my_spin_max; ++__i) { if (__i < __my_last_spins/2 || *__lock) { __junk *= __junk; __junk *= __junk; __junk *= __junk; __junk *= __junk; } else { if (!_Atomic_swap((unsigned long*)__lock, 1)) { // got it! // Spinning worked. Thus we're probably not being scheduled // against the other process with which we were contending. // Thus it makes sense to spin longer the next time. _STL_mutex_spin<0>::__last = __i; _STL_mutex_spin<0>::__max = _STL_mutex_spin<0>::__high_max; return; } } } // We are probably being scheduled against the other process. Sleep. _STL_mutex_spin<0>::__max = _STL_mutex_spin<0>::__low_max; for (__i = 0 ;; ++__i) { int __log_nsec = __i + 6; if (__log_nsec > 27) __log_nsec = 27; if (!_Atomic_swap((unsigned long *)__lock, 1)) { break; } _S_nsec_sleep(__log_nsec); } } /* first _Atomic_swap */ # endif } # endif /* if SGI or WIN */ __STL_END_NAMESPACE # endif /* BUILDING_STLPORT */ #endif /* __STL_THREADS_C */ // Local Variables: // mode:C++ // End:

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/osprey1.0/be/purple2/prp_driver.h

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no_license

sriharikrishna/Open64

fe764dd267f5c0cb040b3eceb2efbda71f8be9be

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refs/heads/master

UTF-8

C

h

/* Copyright (C) 2000, 2001 Silicon Graphics, Inc. All Rights Reserved. This program is free software; you can redistribute it and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it would be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Further, this software is distributed without any warranty that it is free of the rightful claim of any third person regarding infringement or the like. Any license provided herein, whether implied or otherwise, applies only to this software file. Patent licenses, if any, provided herein do not apply to combinations of this program with other software, or any other product whatsoever. You should have received a copy of the GNU General Public License along with this program; if not, write the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pky, Mountain View, CA 94043, or: http://www.sgi.com For further information regarding this notice, see: http://oss.sgi.com/projects/GenInfo/NoticeExplan */ #ifndef prp_driver_INCLUDED #define prp_driver_INCLUDED #ifdef __cplusplus extern "C" { #endif /* ============================================================== * ============================================================== * * Module: prp_driver.h * $Revision: 1.1.1.1 $ * $Date: 2002-05-22 20:06:53 $ * $Author: dsystem $ * $Source: /m_home/m_utkej/Argonne/cvs2svn/cvs/Open64/osprey1.0/be/purple2/prp_driver.h,v $ * * Description: * * Defines utilities exported by purple_instr.so * * ============================================================== * ============================================================== */ void Prp_Process_Command_Line (INT phase_argc, char *phase_argv[], INT argc, char *argv[]); BOOL Prp_Needs_Whirl2c(void); BOOL Prp_Needs_Whirl2f(void); void Prp_Init(void); void Prp_Instrument_And_EmitSrc(WN *pu); void Prp_Fini(void); #ifdef __cplusplus } #endif #endif /* prp_driver_INCLUDED */

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/scaler/src/horizInputData.h

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Q-Mart/QLight

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refs/heads/master

UTF-8

C

h

uint_fast8_t horizInputData[432000] = { 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 0, 0, 0, 255, 255, 255, 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/* Copyright (c) 2019, Ameer Haj Ali (UC Berkeley), and Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "header.h" short sa[16384]; short sb[16384]; short sc[16384]; int out1[16384] ALIGNED16; int out2[16384] ALIGNED16; int out3[16384] ALIGNED16; __attribute__((noinline)) void example10b(short *__restrict__ sa, short *__restrict__ sb, short *__restrict__ sc, int* __restrict__ out1, int* __restrict__ out2, int* __restrict__ out3) { int i; for (i = 0; i < 16384-1; i+=2) { out1[i] = (int) sa[i]; out1[i+1] = (int) sa[i+1]; out2[i] = (int) sb[i]; out2[i+1] = (int) sb[i+1]; out3[i] = (int) sc[i]; out3[i+1] = (int) sc[i+1]; } } int main(int argc,char* argv[]){ init_memory(&out1[0], &out1[16384]); init_memory(&out2[0], &out2[16384]); init_memory(&out3[0], &out3[16384]); init_memory(&sa[0], &sa[16384]); init_memory(&sb[0], &sb[16384]); init_memory(&sc[0], &sc[16384]); BENCH("Example10b", example10b(sa,sb,sc,out1,out2,out3), Mi*4/16384*512, digest_memory(&out1[0], &out1[16384])+digest_memory(&out2[0], &out2[16384])+digest_memory(&out3[0], &out3[16384])); return 0; }

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refs/heads/master