mradermacher/VeriSeek-GGUF
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_pixel_1/pikachu_pixel_stub.v
// Design : pikachu_pixel
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module pikachu_pixel(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [12:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:20:13 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top led_controller_design_auto_pc_0 -prefix
// led_controller_design_auto_pc_0_ led_controller_design_auto_pc_0_stub.v
// Design : led_controller_design_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
module led_controller_design_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Module: hilo_reg
// File: hilo_reg.v
// Author: Lei Silei
// E-mail:
// Description: ±£´æ³Ë·¨½á¹ûµÄHI¡¢LO¼Ä´æÆ÷
// Revision: 1.0
//////////////////////////////////////////////////////////////////////
`include "defines.v"
module hilo_reg(
input wire clk,
input wire rst,
//д¶Ë¿Ú
input wire we,
input wire[`RegBus] hi_i,
input wire[`RegBus] lo_i,
//¶Á¶Ë¿Ú1
output reg[`RegBus] hi_o,
output reg[`RegBus] lo_o
);
always @ (posedge clk) begin
if (rst == `RstEnable) begin
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end else if((we == `WriteEnable)) begin
hi_o <= hi_i;
lo_o <= lo_i;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; inline int read() { int w = 1, s = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = 0; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { s = (s << 1) + (s << 3) + ch - 0 ; ch = getchar(); } return w ? s : -s; } const int N = 1001; struct point { int x, y, num; } p[N]; struct square { int x, y, r; } s[N]; int opp[N], bel[N]; bool num[N]; int n, m, k, ans; vector<int> f[N]; bool cmp1(point a, point b) { return a.x < b.x; } bool cmp2(square a, square b) { return a.x - a.r < b.x - b.r; } bool solve(int x) { if (x == 0) return 1; return 0; } void content() { n = read(), m = read(), k = read(); for (int i = 1; i <= n; i++) p[i].x = read(), p[i].y = read(), p[i].num = i; sort(p + 1, p + n + 1, cmp1); for (int i = 1; i <= n; i++) opp[p[i].num] = i; for (int i = 1; i <= m; i++) { s[i].r = read(); s[i].x = read(), s[i].y = read(); } sort(s + 1, s + m + 1, cmp2); for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) { if (p[j].x < s[i].x - s[i].r) continue; if (p[j].x > s[i].x + s[i].r) break; int a = p[j].x, b = p[j].y, c = s[i].x, d = s[i].y; double lc = sqrt(pow((a - c), 2) + pow((b - d), 2)); if (lc < s[i].r) f[p[j].num].push_back(i); } } for (int i = 1; i <= k; i++) { int x = read(), y = read(); for (int j = 0; j < f[x].size(); j++) num[f[x][j]] = solve(num[f[x][j]]); for (int j = 0; j < f[y].size(); j++) num[f[y][j]] = solve(num[f[y][j]]); for (int j = 1; j <= m; j++) if (num[j]) ans++; printf( %d n , ans); ans = 0; memset(num, 0, sizeof(num)); } } int main() { content(); return 0; } |
#include <cstdio> #include <algorithm> #include <vector> #include <set> #include <cstdlib> #include <utility> #include <cmath> #include <queue> #include <stack> #include <cstring> using namespace std; #define ll long long #ifndef ONLINE_JUDGE #define debug(format, ...) fprintf(stderr, %s:%d: format n , __func__, __LINE__,##__VA_ARGS__) #else #define debug(format, ...) #define NDEBUG #endif #define BLKSIZE 300 int n, q; int b[100005]; int blkid[100005]; int blkbegin[100005]; // for block i, minimum start value required for j increases int mincnt[400][405]; int f[100005]; int fen[300005]; #define lowbit(x) ((x)&(-(x))) int rquery(int* arr, int v) { int ans = 0; while (v) { ans += arr[v]; v -= lowbit(v); } return ans; } void modify(int* arr, int loc, int val) { //printf( %d %lld n , loc, val); while (loc <= n) { arr[loc] += val; loc += lowbit(loc); } } void updateblock(int id) { int start = max(id * BLKSIZE, 1); for (int i = start; blkid[i] == id; i++) { int x = 0; int curv = 0; for (int j = 16; j >= 0; j--) { int nx = x + (1 << j); if (nx <= n && curv + fen[nx] + nx <= b[i]) { x = nx; curv += fen[nx]; } } f[i] = x + 1; if (f[i] <= n) modify(fen, f[i], 1); } vector<int> vals; for (int i = start; blkid[i] == id; i++) { vals.push_back(f[i]); if (f[i] <= n) modify(fen, f[i], -1); } sort(vals.begin(), vals.end()); for (int i = 0; i < vals.size(); i++) { mincnt[id][i+1] = vals[i]; } for (int i = vals.size() + 1; i <= BLKSIZE; i++) { mincnt[id][i] = 10000000; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , b + i); blkid[0] = blkid[n + 1] = -1; for (int i = 1; i <= n; i++) { blkid[i] = i / BLKSIZE; blkbegin[i] = (blkid[i-1] == blkid[i] ? blkbegin[i-1] : i); } for (int i = 0; i <= n / BLKSIZE; i++) { updateblock(i); } scanf( %d , &q); for (int qr = 1; qr <= q; qr++) { int typ; scanf( %d , &typ); if (typ == 1) { int x, y; scanf( %d%d , &x, &y); b[x] = y; updateblock(blkid[x]); } else { int x; scanf( %d , &x); int cur = b[x] + 1; int i; for (i = x + 1; blkid[i] == blkid[x]; i++) { if (cur > b[i]) cur++; } if (i <= n) { for (int j = blkid[i]; j <= n / BLKSIZE; j++) { int l = 0; int r = BLKSIZE; while (l < r) { int mid = (l + r) / 2 + 1; if (cur >= mincnt[j][mid]) { l = mid; } else { r = mid - 1; } } cur += l; } } printf( %d n , n + 1 - cur); } } return 0; } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int n, ans[100001][4], cnt = 0; pair<int, int> t[4]; priority_queue<pair<int, int> > q; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; ++mp[x]; } for (map<int, int>::iterator it = mp.begin(); it != mp.end(); it++) { q.push({it->second, it->first}); } while (q.size() >= 3) { ++cnt; for (int i = 1; i <= 3; i++) { t[i] = q.top(); q.pop(); ans[cnt][i] = t[i].second; } for (int i = 1; i <= 3; i++) { t[i].first--; if (t[i].first) { q.push(t[i]); } } } cout << cnt << n ; for (int i = 1; i <= cnt; i++) { sort(ans[i] + 1, ans[i] + 4); cout << ans[i][3] << << ans[i][2] << << ans[i][1] << n ; } } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, i; cin >> n; int a[n], b[n + 1]; for (i = 0; i < n; i++) { cin >> a[i]; b[a[i]] = i; } int l, r, ans[n + 1]; l = b[1]; r = b[1]; for (i = 2; i <= n; i++) { l = min(l, b[i]); r = max(r, b[i]); if ((r - l + 1) != i) ans[i] = 0; else ans[i] = 1; } cout << 1; for (i = 2; i <= n; i++) cout << ans[i]; cout << endl; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; } |
`include "rv32_opcodes.vh"
module vscale_regfile(
input clk,
input [`REG_ADDR_WIDTH-1:0] ra1,
output [`XPR_LEN-1:0] rd1,
input [`REG_ADDR_WIDTH-1:0] ra2,
output [`XPR_LEN-1:0] rd2,
input wen,
input [`REG_ADDR_WIDTH-1:0] wa,
input [`XPR_LEN-1:0] wd
);
reg [`XPR_LEN-1:0] data [31:0];
wire wen_internal;
// fpga-style zero register
assign wen_internal = wen && |wa;
assign rd1 = |ra1 ? data[ra1] : 0;
assign rd2 = |ra2 ? data[ra2] : 0;
always @(posedge clk) begin
if (wen_internal) begin
data[wa] <= wd;
end
end
`ifndef SYNTHESIS
integer i;
initial begin
for (i = 0; i < 32; i = i + 1) begin
data[i] = $random;
end
end
`endif
endmodule // vscale_regfile
|
#include <bits/stdc++.h> using namespace std; long long cumu[200005]; int main() { int n, k, x; while (scanf( %d %d , &n, &k) == 2) { memset(cumu, 0ll, sizeof cumu); int mn = INT_MAX; for (int i = 0; i < n; i++) scanf( %d , &x), cumu[x + 1] -= 1, mn = min(mn, x); cumu[1] = n; for (int i = 1; i <= 200001; i++) cumu[i] += cumu[i - 1]; for (int i = 1; i <= 200001; i++) cumu[i] += cumu[i - 1]; int last = 200001; int cut = 0; int ans = 0; for (int i = 200000; i >= mn; i--) { cut = cumu[last] - cumu[i]; if (cut > k) ans++, last = i + 1, cut = cumu[last] - cumu[i]; } ans += (cut != 0); printf( %d n , ans); } return 0; } |
// chris_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
/*
assign avs_s0_readdata = 32'b00000000000000000000000000000000;
assign avs_s0_waitrequest = 1'b0;
assign LEDR = 1'b0;
*/
/*
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.aclr (),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
*/
assign avs_s0_readdata = 32'b00000000000000000000000000000000;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] data_in;
reg [31:0] data_out;
reg led_out;
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read || Reg_Status_Write;
assign LEDR = led_out;
wire [8:0] kernel_parameter;
wire [2:0] image_paramete;
//register map
// kernel parametes
assign kernel_parameter[0] = (avs_s0_address[3:0] == 4'b0000) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[1] = (avs_s0_address[3:0] == 4'b0001) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[2] = (avs_s0_address[3:0] == 4'b0010) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[3] = (avs_s0_address[3:0] == 4'b0011) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[4] = (avs_s0_address[3:0] == 4'b0100) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[5] = (avs_s0_address[3:0] == 4'b0101) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[6] = (avs_s0_address[3:0] == 4'b0110) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[7] = (avs_s0_address[3:0] == 4'b0111) & (avs_s0_write | avs_s0_read);
assign kernel_parameter[8] = (avs_s0_address[3:0] == 4'b1000) & (avs_s0_write | avs_s0_read);
//image data;
assign image_paramete[0] = (avs_s0_address[3:0] == 4'b10001) & (avs_s0_write | avs_s0_read); // 4 image pixels, only three pixeles are valid
assign image_paramete[1] = (avs_s0_address[3:0] == 4'b10010) & (avs_s0_write | avs_s0_read); // 4 image pixels, only three pixeles are valid
assign image_paramete[2] = (avs_s0_address[3:0] == 4'b10011) & (avs_s0_write | avs_s0_read); // 4 image pixels, only three pixeles are valid
// WRITE LOGIC
//
always @(posedge clock_clk)
if (reset_reset) begin
data_in <= 32'b0;
data_out <= 32'b0;
Reg_Status_Write <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
Reg_Status_Write <= 1'b0;
led_out <= avs_s0_writedata[0];
data_in <= avs_s0_writedata;
end else begin
Reg_Status_Write <= 1'b0;
end
//
// READ LOGIC
//
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace std { template <> struct hash<pair<int, int>> { size_t operator()(const pair<int, int> &x) const { long long P = 38923, Q = 109797901; return (size_t)((x.first * P + x.second) % Q); } }; }; // namespace std template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; template <typename T> void print(T t) { cout << t << endl; } template <typename T, typename... Args> void print(T t, Args... args) { cout << t << ; print(args...); } int main() { ios::sync_with_stdio(false); cin.tie(0); long long x, y, z; cin >> x >> y >> z; if (x > y + z) print( + ); else if (y > x + z) print( - ); else if (x == y && z == 0) print( 0 ); else print( ? ); return 0; } |
#include <bits/stdc++.h> int mod = 1000000007; using namespace std; using namespace std; int n, k; int a[400005]; int pos[400005]; map<int, int> m; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; cin >> n >> k; for (int i = 1; i <= n; i++) pos[i] = 1e7; m[a[1]] = 1e7; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { pos[m[a[i]]] = i; m[a[i]] = i; } int ans = 0; set<int> s; set<pair<int, int> > ss; for (int i = 1; i <= n; i++) { if (!s.count(a[i])) { if (s.size() < k) { ans++; s.insert(a[i]); ss.insert(make_pair(pos[i], a[i])); } else { ans++; set<pair<int, int> >::iterator it = ss.end(); it--; int val = (*it).second; ss.erase(it); s.erase((val)); s.insert(a[i]); ss.insert(make_pair(pos[i], a[i])); } } else { ss.erase(ss.begin()); ss.insert(make_pair(pos[i], a[i])); } } cout << ans; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_chip_tb
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_chip_tb.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_chip_tb.v,v $
// Revision 1.1 2006/07/10 07:30:08 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_chip_tb
//
// No user `defines in this module
module avfb_chip_tb
//
// Generated module avfb_chip_tb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for dut
avfb_chip dut (
);
// End of Generated Instance Port Map for dut
endmodule
//
// End of Generated Module rtl of avfb_chip_tb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b; scanf( %lld%lld , &a, &b); long long int c = a, d = b; long long int cnt = 0, rem; while (c >= 1 && d >= 1) { if (d == 1) { printf( %lld , cnt + c); return 0; } if (c >= d) { cnt += c / d; c = c % d; } else { cnt += d / c; d = d % c; } } printf( %lld n , cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; int h; long long n, des; long long GetRes(long long l) { if (l == 1) return 0; if ((l + l / 2) % 2) { return 1 + GetRes(l / 2); } else { return pow(2, h - (int)(log2(l)) + 1) + GetRes(l / 2); } } int main() { while (cin >> h >> n) { des = pow(2, h) - 1 + n; cout << GetRes(des) << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O21A_BEHAVIORAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_BEHAVIORAL_V |
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_prbs_gen
*/
module test_lfsr_prbs_gen_prbs31_64;
// Parameters
parameter LFSR_WIDTH = 31;
parameter LFSR_POLY = 31'h10000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 0;
parameter INVERT = 1;
parameter DATA_WIDTH = 64;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
enable
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_prbs_gen_prbs31_64.lxt");
$dumpvars(0, test_lfsr_prbs_gen_prbs31_64);
end
lfsr_prbs_gen #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.INVERT(INVERT),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.enable(enable),
.data_out(data_out)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// phasemeter.v: Clock phase meter using high freq. sampling clock and a counter //
// //
// Ameer M.S. Abdelhadi (; ), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module phasemeter
( input clk_500, // sampling clock, 500Mhz
input clk_ref, // reference clock
input clk_phs, // phase-shifted clock, same frequency as reference clock
output reg phs_sgn, // measured pahse shift / sign
output [11:0] phs_bcd); // measured pahse shift / BCD {ones,tens,hundreds}
wire clk_ph1 = clk_ref && ~clk_phs;
localparam cntW = 8;
reg [cntW-1:0] cntR, cntF,cntR_,cntF_;
always @(posedge clk_500)
if (!clk_ph1) cntR <= {cntW{1'b0}};
else cntR <= cntR+{cntW{1'b1}};
always @(negedge clk_500)
if (!clk_ph1) cntF <= {cntW{1'b0}};
else cntF <= cntR+{cntW{1'b1}};
always @(negedge clk_ph1)
{cntR_,cntF_} <= {cntR,cntF};
always @(negedge clk_ref)
phs_sgn <= clk_phs;
wire [cntW:0] cnt_sum = cntR_ + cntF_;// + !phs_sign;
//wire [8:0] phs_bin = cnt_sum*8'd10/8'd8+(|cnt_sum[1:0]);
bin2bcd9 bin2bcd9_00 (cnt_sum,phs_bcd);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_TB_V
`define SKY130_FD_SC_MS__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[50]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; a[i] %= m; } sort(a, a + n); set<int> S1, S2; for (int i = 0; i < n; i++) { set<int> s = i < n / 2 ? S1 : S2; s.insert(a[i]); for (auto b : i < n / 2 ? S1 : S2) { s.insert((a[i] + b) % m); } if (i < n / 2) S1 = s; else S2 = s; } S1.insert(0); S2.insert(0); int best = 0; for (auto b : S1) { best = max(best, b + *(--S2.lower_bound(m - b))); } cout << best; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_BLACKBOX_V
`define SKY130_FD_SC_MS__O221AI_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int d[n]; d[0] = a[0]; map<int, int> even, odd; even[d[0]]++; odd[0]++; long long int c = 0; for (int i = 1; i < n; i++) { d[i] = a[i] ^ d[i - 1]; if (i % 2 == 0) { even[d[i]]++; if (even.find(d[i]) != even.end()) c += even[d[i]] - 1; } else { odd[d[i]]++; if (odd.find(d[i]) != odd.end()) c += odd[d[i]] - 1; } } cout << c; } |
module I2C_AV_Config ( // Host Side
iCLK,
iRST_N,
// I2C Side
I2C_SCLK,
I2C_SDAT );
// Host Side
input iCLK;
input iRST_N;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 51;
// Audio Data Index
parameter Dummy_DATA = 0;
parameter SET_LIN_L = 1;
parameter SET_LIN_R = 2;
parameter SET_HEAD_L = 3;
parameter SET_HEAD_R = 4;
parameter A_PATH_CTRL = 5;
parameter D_PATH_CTRL = 6;
parameter POWER_ON = 7;
parameter SET_FORMAT = 8;
parameter SAMPLE_CTRL = 9;
parameter SET_ACTIVE = 10;
// Video Data Index
parameter SET_VIDEO = 11;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
if(LUT_INDEX<SET_VIDEO)
mI2C_DATA <= {8'h34,LUT_DATA};
else
mI2C_DATA <= {8'h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
Dummy_DATA : LUT_DATA <= 16'h0000;
SET_LIN_L : LUT_DATA <= 16'h001A;
SET_LIN_R : LUT_DATA <= 16'h021A;
SET_HEAD_L : LUT_DATA <= 16'h047B;
SET_HEAD_R : LUT_DATA <= 16'h067B;
A_PATH_CTRL : LUT_DATA <= 16'h08F8;
D_PATH_CTRL : LUT_DATA <= 16'h0A06;
POWER_ON : LUT_DATA <= 16'h0C00;
SET_FORMAT : LUT_DATA <= 16'h0E01;
SAMPLE_CTRL : LUT_DATA <= 16'h1002;
SET_ACTIVE : LUT_DATA <= 16'h1201;
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0860;
SET_VIDEO+31: LUT_DATA <= 16'h0a18;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df8;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
default: LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long x, y; cin >> x >> y; long long n; cin >> n; n %= 6; if (n == 0) n = 6; long long data[7]; data[1] = x; data[2] = y; for (int i = 3; i <= 6; i++) { data[i] = data[i - 1] - data[i - 2]; } for (int i = 1; i <= 6; i++) if (data[i] < 0) data[i] += 1000000007; if (data[n] < 0) data[n] += 1000000007; cout << data[n] % 1000000007 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100010; int ans = -1, ansd, a[MAXN], b[MAXN], n, m; inline int Pow(int x, int y, int mod) { int s = 1; for (; y; y >>= 1, x = 1ll * x * x % mod) if (y & 1) s = 1ll * s * x % mod; return s; } inline bool find(int *a, int n, int x) { int t = lower_bound(a + 1, a + n + 1, x) - a; return a[t] == x; } inline void solve(int *a, int n) { if (n == 1) { ans = a[1], ansd = 1; return; } int tmp = a[2] - a[1], cnt = 0; for (int i = 1; i <= n; i++) if (find(a, n, (a[i] + tmp) % m)) cnt++; ansd = 1ll * tmp * Pow(n - cnt, m - 2, m) % m; int d = (m - ansd) % m; for (int i = 1; i <= n; i++) if (!find(a, n, (a[i] + d) % m)) { if (ans == -1) ans = a[i]; else { ans = -1; return; } } } int main() { scanf( %d%d , &m, &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); if (n == 1 || n == m) return printf( %d 1 n , a[1], 1), 0; if (2 * n - 4 < m) solve(a, n); else { int t = 0; for (int i = 0; i < m; i++) if (!find(a, n, i)) b[++t] = i; solve(b, t); if (ans != -1) (ans += 1ll * ansd * t % m) %= m; } if (ans == -1) return printf( -1 n ), 0; return printf( %d %d n , ans, ansd), 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; int edge_n = 2 * n; double edges[edge_n]; double currX, currA; for (int i = 0; i < n; i++) { cin >> currX >> currA; edges[2 * i] = currX - currA / 2; edges[2 * i + 1] = currX + currA / 2; } for (int i = 0; i < edge_n; i++) { for (int j = i; j > 0 && (edges[j] < edges[j - 1]);) { double temp = edges[j - 1]; edges[j - 1] = edges[j]; edges[j] = temp; j--; } } int count = 2; for (int i = 1; i < edge_n; i += 2) { if (edges[i + 1] - edges[i] > t) { count += 2; } else if (edges[i + 1] - edges[i] == t) { count++; } } cout << count; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, ans; int f[2005][2005], A[2005][2005]; int mul[2005], tr1[2005], tr2[2005], vis[2005], lck[2005]; int Getsum(int *tree, int x) { int ans = 0; for (int i = x; i; i -= i & -i) ans += tree[i]; return ans; } void Update(int *tree, int x, int v) { for (int i = x; i <= n; i += i & -i) tree[i] += v; } int main() { scanf( %d , &n); f[0][0] = 1; for (int i = 1; i <= n; i++) { for (int j = 0; j <= i; j++) { if (j == 0) f[i][j] = (long long)f[i - 1][j] * i % 998244353; else { f[i][j] = (f[i][j] + (long long)(i - j) * f[i - 1][j - 1] % 998244353) % 998244353; if (j >= 2) f[i][j] = (f[i][j] + (long long)(j - 1) * f[i - 1][j - 2] % 998244353) % 998244353; } } } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &A[i][j]); mul[0] = 1; for (int i = 1; i <= n; i++) mul[i] = (long long)mul[i - 1] * f[n][n] % 998244353; for (int i = 1; i <= n; i++) { int s = A[1][i] - 1 - Getsum(tr1, A[1][i] - 1); ans = (ans + (long long)s * f[n - i][0] % 998244353 * mul[n - 1] % 998244353) % 998244353; Update(tr1, A[1][i], 1); } for (int i = 2; i <= n; i++) { for (int j = 1; j <= n; j++) tr1[j] = tr2[j] = vis[j] = lck[j] = 0; int all = 0; for (int j = 1; j <= n; j++) { int s = A[i][j] - 1 - Getsum(tr1, A[i][j] - 1) - ((A[i - 1][j] < A[i][j]) && !vis[A[i - 1][j]]); int s1 = Getsum(tr2, A[i][j] - 1); int s2 = s - s1; lck[A[i - 1][j]] = 1; if (!vis[A[i - 1][j]]) Update(tr2, A[i - 1][j], 1), all++; if (s1) ans = (ans + (long long)s1 * f[n - j][n - j - (all - 1)] % 998244353 * mul[n - i] % 998244353) % 998244353; if (s2) ans = (ans + (long long)s2 * f[n - j][n - j - all] % 998244353 * mul[n - i] % 998244353) % 998244353; vis[A[i][j]] = 1; if (lck[A[i][j]]) Update(tr2, A[i][j], -1), all--; Update(tr1, A[i][j], 1); } } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const long long INF = 0x3f3f3f3f3f3f3f3fLL; const int MOD = 1e9 + 7; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, m; cin >> n >> m; vector<vector<int>> e(n + 1); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; e[x].push_back(y); e[y].push_back(x); } vector<int> val(n + 1); for (int i = 1; i <= n; i++) { cin >> val[i]; } vector<int> order(n); iota(order.begin(), order.end(), 1); sort(order.begin(), order.end(), [&](int i, int j) { return val[i] < val[j]; }); for (int i = 0; i < n; i++) { set<int> s; for (int x : e[order[i]]) { s.insert(val[x]); } int c = 1; while (s.count(c)) { c++; } if (c != val[order[i]]) { cout << -1 << n ; return 0; } } for (int i : order) { cout << i << ; } cout << n ; } |
#include <bits/stdc++.h> template <typename T> T mymax(T x, T y) { return (x > y ? x : y); } using namespace std; const int N = 100005; const long long inf = 1e18; vector<int> graph[N], cost[N]; int n, m; long long dis[N]; struct node { int nd, c; node(int _nd, int _c) { nd = _nd; c = _c; } bool operator<(const node& p) const { return c > p.c; } }; void dijkstra() { priority_queue<node> pq; pq.push(node(1, 0)); for (int i = 0; i < N; i++) dis[i] = inf; dis[1] = 0; while (!pq.empty()) { node top = pq.top(); pq.pop(); int u = top.nd; for (int i = 0; i < (int)graph[u].size(); i++) { int v = graph[u][i]; if (dis[v] > dis[u] + cost[u][i]) { dis[v] = dis[u] + cost[u][i]; pq.push(node(v, dis[v])); } } } queue<int> q; q.push(n); vector<int> ans; ans.push_back(n); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < graph[u].size(); i++) { int v = graph[u][i]; if (dis[u] - cost[u][i] == dis[v]) { ans.push_back(v); q.push(v); break; } } } if (ans.size() == 1) { printf( -1 n ); return; } reverse((ans).begin(), (ans).end()); for (int x : ans) { printf( %d , x); } printf( n ); } void solve() { cin >> n >> m; for (int i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; graph[u].push_back(v); graph[v].push_back(u); if (cost[u].size() == 0) { cost[u].push_back(w); cost[v].push_back(w); } else { int mn = 1e9; for (int i = 0; i < graph[u].size() - 1; i++) { int adj = graph[u][i]; if (adj == v) { mn = min(mn, cost[u][i]); } } mn = min(mn, w); cost[u].push_back(mn); cost[v].push_back(mn); } } dijkstra(); return; } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200200; int n; const long long neutro = 0; struct RMQ { int sz; long long tope; long long t[4 * MAXN]; long long &operator[](int p) { return t[sz + p]; } void init(int n, long long tope_) { sz = 1 << (32 - __builtin_clz(n)); tope = tope_; for (int i = (0); i < (2 * sz); i++) t[i] = neutro; } void updall() { for (int i = sz - 1; i >= 0; i--) t[i] = (t[2 * i] + t[2 * i + 1]); } long long get(int i, int j) { if (j <= i) return 0; return get(i, j, 1, 0, sz); } long long get(int i, int j, int n, int a, int b) { if (j <= a || i >= b) return neutro; if (i <= a && b <= j) return t[n]; int c = (a + b) / 2; return (get(i, j, 2 * n, a, c) + get(i, j, 2 * n + 1, c, b)); } void set(int p, long long val) { p += sz; val = min(tope, t[p] + val); for (; p > 0 && t[p] != val;) { t[p] = val; p /= 2; val = (t[p * 2] + t[p * 2 + 1]); } } } rmqa, rmqb; int k, a, b, q; int main() { ios::sync_with_stdio(0); while (cin >> n >> k >> a >> b >> q) { rmqa.init(n, a); rmqb.init(n, b); for (int _ = (0); _ < (q); _++) { int t; cin >> t; if (t == 1) { int d, a; cin >> d >> a; rmqa.set(d - 1, a); rmqb.set(d - 1, a); } else { int p; cin >> p; p--; cout << rmqb.get(0, p) + rmqa.get(p + k, n) << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2, s3; cin >> s1 >> s2 >> s3; int i; s1 = s1.append(s2); sort(s1.begin(), s1.end()); sort(s3.begin(), s3.end()); if (s1.length() != s3.length()) { cout << NO ; return 0; } else { for (i = 0; i < s1.length(); i++) { if (s1[i] != s3[i]) { cout << NO ; return 0; } } cout << YES ; } return 0; } |
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_BEHAVIORAL_V
`define SKY130_FD_SC_LP__FILL_BEHAVIORAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; struct State { int len, link; map<char, int> nxtc; } SA[2 * 2006]; bool vis[2 * 2006]; char str[2006], pref[2 * 2006], suf[2006]; class SuffixAutomata { int sz, last; void init(int idx) { SA[idx].len = 0, SA[idx].link = -1; SA[idx].nxtc.clear(); } bool traverse(int cur, char *ch) { if (*ch == 0) return true; if (SA[cur].nxtc.count(*ch) == 0) return false; int p = SA[cur].nxtc[*ch]; return traverse(p, ++ch); } int findState(int cur, char *ch) { if (*ch == 0) return cur; int p = SA[cur].nxtc[*ch]; return findState(p, ++ch); } public: SuffixAutomata() { sz = last = 0; init(0); ++sz; } int size() { return sz; } void extend(char ch) { int p, q, clone, cur = sz++; init(cur); SA[cur].len = SA[last].len + 1; for (p = last; p != -1 && SA[p].nxtc.count(ch) == 0; p = SA[p].link) SA[p].nxtc[ch] = cur; if (p == -1) SA[cur].link = 0; else { q = SA[p].nxtc[ch]; if (SA[p].len + 1 == SA[q].len) SA[cur].link = q; else { clone = sz++; init(clone); SA[clone] = SA[q]; SA[clone].len = SA[p].len + 1; for (; p != -1 && SA[p].nxtc[ch] == q; p = SA[p].link) SA[p].nxtc[ch] = clone; SA[cur].link = SA[q].link = clone; } } last = cur; } bool traverse(char *str) { return traverse(0, str); } int findState(char *str) { return findState(0, str); } }; int lenp, lens, dp[2 * 2006][2006]; int rec(int cur, int idx) { if (suf[idx] == 0) return 1; if (dp[cur][idx] != -1) return dp[cur][idx]; int &ret = dp[cur][idx]; ret = 0; char ch; int p; if (idx) { ch = suf[idx]; if (SA[cur].nxtc.count(ch) == 0) return ret = 0; p = SA[cur].nxtc[ch]; return ret = rec(p, idx + 1); } map<char, int> &M = SA[cur].nxtc; map<char, int>::iterator im; for (im = M.begin(); im != M.end(); ++im) { ch = im->first; p = im->second; ret += rec(p, idx); if (ch == suf[idx]) ret += rec(p, idx + 1); } return ret; } int main() { int i, j, ans, n; while (scanf( %s , str) != EOF) { SuffixAutomata sa; for (i = 0; str[i]; ++i) sa.extend(str[i]); ans = 0; scanf( %s %s , pref, suf); lenp = strlen(pref), lens = strlen(suf); if (!sa.traverse(pref)) { puts( 0 ); continue; } for (i = 0; i < lenp; ++i) { if (i + lens < lenp) continue; for (j = 0; j < lens; ++j) { if (pref[i + j] != suf[j]) break; } if (i + j == lenp) { strcat(pref, &suf[lenp - i]); ans += sa.traverse(pref); pref[lenp] = 0; } } n = sa.findState(pref); memset(dp, -1, sizeof(dp)); ans += rec(n, 0); printf( %d n , ans); } return 0; } |
`include "common.vh"
`timescale 1ms/10us
module Tenyr(
input clk, reset, inout halt,
output[7:0] seg, output[3:0] an, inout[23:0] gpio,
output[2:0] vgaRed, vgaGreen, output[2:1] vgaBlue, output hsync, vsync, inframe
);
parameter RAMABITS = 13;
wire d_wen, d_stb, d_cyc, d_ack;
wire i_wen, i_stb, i_cyc, i_ack;
wire[3:0] d_sel, i_sel;
wire valid_clk, clk_vga, clk_core;
wire[31:0] i_adr;
wire[31:0] d_adr, d_to_slav, i_to_slav;
wire[31:0] d_to_mast, i_to_mast;
assign i_ack = i_stb;
tenyr_mainclock clocks(
.clk_in ( clk ), .clk_core ( clk_core ),
.reset ( reset ), .clk_vga ( clk_vga ),
.locked ( )
);
Core core(
.clk ( clk_core ),
.halt ( halt ),
.reset ( reset ),
.adr_o ( d_adr ),
.dat_o ( d_to_slav ),
.dat_i ( d_to_mast ),
.wen_o ( d_wen ),
.sel_o ( d_sel ),
.stb_o ( d_stb ),
.ack_i ( d_ack ),
.err_i ( 1'b0 ),
.rty_i ( 1'b0 ),
.cyc_o ( d_cyc )
);
// -----------------------------------------------------------------------------
// MEMORY ----------------------------------------------------------------------
wire r_wen, r_stb, r_cyc, r_ack;
wire[3:0] r_sel;
wire[31:0] r_adr, r_ddn, r_dup;
TwoPortRAM #(
.INIT(0),
.PBITS(32), .ABITS(RAMABITS), .OFFSET(`RESETVECTOR)
) ram(
.clka ( clk_core ), .clkb ( '0 ),
.ena ( r_stb ), .enb ( '0 ),
.acka ( r_ack ), .ackb ( ),
.wea ( r_wen ), .web ( '0 ),
.addra ( r_adr ), .addrb ( '0 ),
.dina ( r_ddn ), .dinb ( '0 ),
.douta ( r_dup ), .doutb ( )
);
// -----------------------------------------------------------------------------
// DEVICES ---------------------------------------------------------------------
wire s_wen, s_stb, s_cyc;
wire[3:0] s_sel;
wire[31:0] s_adr, s_ddn, s_dup;
wire s_stbcyc = s_stb & s_cyc;
`ifdef SERIAL
// TODO write a hardware-compatible serial device ; rename to eliminate `Sim`
SimWrap_simserial #(.BASE(32'h20), .SIZE(2)) serial(
.clk ( clk_core ), .reset ( reset ), .enable ( s_stbcyc ),
.rw ( s_wen ), .addr ( s_adr ), .data ( s_ddn )
);
`endif
wire g_wen, g_stb, g_cyc, g_ack;
wire[3:0] g_sel;
wire[31:0] g_adr, g_ddn, g_dup;
wire g_stbcyc = g_stb & g_cyc;
Seg7 seg7(
.clk ( clk_core ), .rw ( g_wen ), .seg ( seg ),
.reset ( reset ), .addr ( g_adr ), .an ( an ),
.strobe ( g_stbcyc ), .d_in ( g_ddn ), .d_out ( g_dup ), .ack( g_ack )
);
wire o_wen, o_stb, o_cyc;
wire[3:0] o_sel;
wire[31:0] o_adr, o_ddn, o_dup;
wire o_stbcyc = o_stb & o_cyc;
Gpio #(.COUNT(24)) gio(
.clk ( clk_core ), .rw ( o_wen ), .gpio ( gpio ),
.reset ( reset ), .addr ( o_adr ), .data_i ( o_ddn ),
.strobe ( o_stbcyc ), .data_o ( o_dup )
);
wire v_wen, v_stb, v_cyc;
wire[3:0] v_sel;
wire[31:0] v_adr, v_ddn, v_dup;
wire v_stbcyc = v_stb & v_cyc;
`ifdef VGA
VGAwrap vga(
.clk_core ( clk_core ), .rw ( v_wen ), .vgaRed ( vgaRed ),
.clk_vga ( clk_vga ), .addr ( v_adr ), .vgaGreen ( vgaGreen ),
.en ( 1'b1 ), .d_in ( v_ddn ), .vgaBlue ( vgaBlue ),
.reset ( reset ), .d_out ( v_dup ), .hsync ( hsync ),
.strobe ( v_stbcyc ), .vsync ( vsync ),
.inframe ( inframe )
);
`endif
wire x_wen, x_stb, x_cyc;
wire[3:0] x_sel;
wire[31:0] x_adr, x_ddn, x_dup;
assign x_dup = 32'hffffffff;
wb_mux #(
.num_slaves(6),
.MATCH_ADDR({
// GPIO 7-seg VGA display serial port memory default
32'h200,32'h100,`VIDEO_ADDR ,32'h00000020,`RESETVECTOR,-32'sd1 }),
.MATCH_MASK({
-32'd4 ,-32'd2 ,32'hffff0000,32'hfffffffe,32'hffffd000,-32'sd1 })
) mux (
.wb_clk_i ( clk_core ),
.wb_rst_i ( reset ),
.wbm_adr_i ( d_adr ),
.wbm_dat_i ( d_to_slav ),
.wbm_dat_o ( d_to_mast ),
.wbm_we_i ( d_wen ),
.wbm_sel_i ( d_sel ),
.wbm_stb_i ( d_stb ),
.wbm_ack_o ( d_ack ),
.wbm_err_o ( /* TODO */ ),
.wbm_rty_o ( /* TODO */ ),
.wbm_cyc_i ( d_cyc ),
// gpio 7-seg VGA serial mem def.
.wbs_adr_o ({ o_adr, g_adr, v_adr, s_adr, r_adr, x_adr }),
.wbs_dat_o ({ o_ddn, g_ddn, v_ddn, s_ddn, r_ddn, x_ddn }),
.wbs_dat_i ({ o_dup, g_dup, v_dup, s_dup, r_dup, x_dup }),
.wbs_we_o ({ o_wen, g_wen, v_wen, s_wen, r_wen, x_wen }),
.wbs_sel_o ({ o_sel, g_sel, v_sel, s_sel, r_sel, x_sel }),
.wbs_stb_o ({ o_stb, g_stb, v_stb, s_stb, r_stb, x_stb }),
.wbs_ack_i ({ o_stb, g_ack, v_stb, s_stb, r_ack, x_stb }),
.wbs_err_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_rty_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_cyc_o ({ o_cyc, g_cyc, v_cyc, s_cyc, r_cyc, x_cyc }),
// unused ports
.wbm_cti_i ( '0 ),
.wbm_bte_i ( '0 ),
.wbs_cti_o ( ),
.wbs_bte_o ( )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int Find(int x) { if (mp.find(x) == mp.end()) return x; return mp[x] = Find(mp[x]); } int main() { int n; while (scanf( %d , &n) != EOF) { mp.clear(); int a; for (int i = 0; i < n; i++) { scanf( %d , &a); a = Find(a); mp[a] = a + 1; if (i) printf( ); printf( %d , a); } printf( n ); } return 0; } |
/*
File: ewrapper_io_rx_slow.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_io_rx_slow (/*AUTOARG*/
// Outputs
CLK_DIV_OUT, DATA_IN_TO_DEVICE,
// Inputs
CLK_IN_P, CLK_IN_N, CLK_RESET, IO_RESET, DATA_IN_FROM_PINS_P,
DATA_IN_FROM_PINS_N, BITSLIP
);
//###########
//# INPUTS
//###########
input CLK_IN_P; // Differential clock from IOB
input CLK_IN_N;
input CLK_RESET;
input IO_RESET;
input [8:0] DATA_IN_FROM_PINS_P;
input [8:0] DATA_IN_FROM_PINS_N;
input BITSLIP;
//#############
//# OUTPUTS
//#############
output CLK_DIV_OUT; // Slow clock output
output [71:0] DATA_IN_TO_DEVICE;
//############
//# REGS
//############
reg [1:0] clk_cnt;
reg [8:0] clk_even_reg;
reg [8:0] clk_odd_reg;
reg [8:0] clk0_even;
reg [8:0] clk1_even;
reg [8:0] clk2_even;
reg [8:0] clk3_even;
reg [8:0] clk0_odd;
reg [8:0] clk1_odd;
reg [8:0] clk2_odd;
reg [8:0] clk3_odd;
reg [71:0] rx_out_sync_pos;
reg rx_outclock_del_45;
reg rx_outclock_del_135;
reg [71:0] rx_out;
//############
//# WIRES
//############
wire reset;
wire rx_outclock;
wire rxi_lclk;
wire [71:0] rx_out_int;
wire rx_pedge_first;
wire [8:0] rx_in;
wire [8:0] clk_even;
wire [8:0] clk_odd;
wire [8:0] iddr_d;
wire [8:0] iddr_q1;
wire [8:0] iddr_q2;
/*AUTOINPUT*/
/*AUTOWIRE*/
`ifdef EP64
assign clk_even[8:0] = iddr_q2[8:0];
assign clk_odd[8:0] = iddr_q1[8:0];
assign iddr_d[8:0] = ~rx_in[8:0];
`else
assign clk_even[8:0] = iddr_q1[8:0];
assign clk_odd[8:0] = iddr_q2[8:0];
assign iddr_d[8:0] = rx_in[8:0];
`endif
assign reset = CLK_RESET;
assign DATA_IN_TO_DEVICE[71:0] = rx_out[71:0];
assign CLK_DIV_OUT = rx_outclock;
//################################
//# Input Buffers Instantiation
//################################
genvar pin_count;
generate
for (pin_count = 0; pin_count < 9; pin_count = pin_count + 1) begin: pins
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (`IOSTND))
ibufds_inst
(.I (DATA_IN_FROM_PINS_P[pin_count]),
.IB (DATA_IN_FROM_PINS_N[pin_count]),
.O (rx_in[pin_count]));
end
endgenerate
//#####################
//# Clock Buffers
//#####################
IBUFGDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (`IOSTND))
ibufds_clk_inst
(.I (CLK_IN_P),
.IB (CLK_IN_N),
.O (rxi_lclk));
// BUFR generates the slow clock
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4"))
clkout_buf_inst
(.O (rx_outclock),
.CE(1'b1),
.CLR(CLK_RESET),
.I (rxi_lclk));
//#################################
//# De-serialization Cycle Counter
//#################################
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk_cnt[1:0] <= 2'b00;
else if(rx_pedge_first)
clk_cnt[1:0] <= 2'b11;
else
clk_cnt[1:0] <= clk_cnt[1:0] + 2'b01;
//################################################################
//# Posedge Detection of the Slow Clock in the Fast Clock Domain
//################################################################
always @ (negedge rxi_lclk)
rx_outclock_del_45 <= rx_outclock;
always @ (negedge rxi_lclk)
rx_outclock_del_135 <= rx_outclock_del_45;
assign rx_pedge_first = rx_outclock_del_45 & ~rx_outclock_del_135;
//#############################
//# De-serialization Output
//#############################
// Synchronizing the clocks (fast to slow)
always @ (posedge rxi_lclk or posedge reset)
if(reset)
rx_out_sync_pos[71:0] <= {(72){1'b0}};
else
rx_out_sync_pos[71:0] <= rx_out_int[71:0];
always @ (posedge rx_outclock or posedge reset)
if(reset)
rx_out[71:0] <= {(72){1'b0}};
else
rx_out[71:0] <= rx_out_sync_pos[71:0];
//#############################
//# IDDR instantiation
//#############################
genvar iddr_cnt;
generate
for (iddr_cnt = 0; iddr_cnt < 9; iddr_cnt = iddr_cnt + 1) begin: iddrs
IDDR #(
.DDR_CLK_EDGE (`CLKEDGE),
.SRTYPE ("ASYNC"))
iddr_inst (
.Q1 (iddr_q1[iddr_cnt]),
.Q2 (iddr_q2[iddr_cnt]),
.C (rxi_lclk),
.CE (1'b1),
.D (iddr_d[iddr_cnt]),
.R (reset),
.S (1'b0));
end
endgenerate
//#############################
//# De-serialization Registers
//#############################
always @ (posedge rxi_lclk or posedge reset)
if(reset)
begin
clk_even_reg[8:0] <= {(8){1'b0}};
clk_odd_reg[8:0] <= {(8){1'b0}};
end
else
begin
clk_even_reg[8:0] <= clk_even[8:0];
clk_odd_reg[8:0] <= clk_odd[8:0];
end
//# even bytes
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk0_even[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b00)
clk0_even[8:0] <= clk_even_reg[8:0];
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk1_even[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b01)
clk1_even[8:0] <= clk_even_reg[8:0];
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk2_even[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b10)
clk2_even[8:0] <= clk_even_reg[8:0];
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk3_even[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b11)
clk3_even[8:0] <= clk_even_reg[8:0];
//# odd bytes
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk0_odd[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b00)
clk0_odd[8:0] <= clk_odd_reg[8:0];
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk1_odd[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b01)
clk1_odd[8:0] <= clk_odd_reg[8:0];
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk2_odd[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b10)
clk2_odd[8:0] <= clk_odd_reg[8:0];
always @ (posedge rxi_lclk or posedge reset)
if(reset)
clk3_odd[8:0] <= {(8){1'b0}};
else if(clk_cnt[1:0] == 2'b11)
clk3_odd[8:0] <= clk_odd_reg[8:0];
//#####################################
//# De-serialization Data Construction
//#####################################
assign rx_out_int[71:64]={clk0_even[8],clk0_odd[8],clk1_even[8],clk1_odd[8],
clk2_even[8],clk2_odd[8],clk3_even[8],clk3_odd[8]};
assign rx_out_int[63:56]={clk0_even[7],clk0_odd[7],clk1_even[7],clk1_odd[7],
clk2_even[7],clk2_odd[7],clk3_even[7],clk3_odd[7]};
assign rx_out_int[55:48]={clk0_even[6],clk0_odd[6],clk1_even[6],clk1_odd[6],
clk2_even[6],clk2_odd[6],clk3_even[6],clk3_odd[6]};
assign rx_out_int[47:40]={clk0_even[5],clk0_odd[5],clk1_even[5],clk1_odd[5],
clk2_even[5],clk2_odd[5],clk3_even[5],clk3_odd[5]};
assign rx_out_int[39:32]={clk0_even[4],clk0_odd[4],clk1_even[4],clk1_odd[4],
clk2_even[4],clk2_odd[4],clk3_even[4],clk3_odd[4]};
assign rx_out_int[31:24]={clk0_even[3],clk0_odd[3],clk1_even[3],clk1_odd[3],
clk2_even[3],clk2_odd[3],clk3_even[3],clk3_odd[3]};
assign rx_out_int[23:16]={clk0_even[2],clk0_odd[2],clk1_even[2],clk1_odd[2],
clk2_even[2],clk2_odd[2],clk3_even[2],clk3_odd[2]};
assign rx_out_int[15:8] ={clk0_even[1],clk0_odd[1],clk1_even[1],clk1_odd[1],
clk2_even[1],clk2_odd[1],clk3_even[1],clk3_odd[1]};
assign rx_out_int[7:0] ={clk0_even[0],clk0_odd[0],clk1_even[0],clk1_odd[0],
clk2_even[0],clk2_odd[0],clk3_even[0],clk3_odd[0]};
endmodule // dv_io_rx
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module filterbank
#(
parameter N = 8,
parameter WIDTH = 32,
parameter MWIDTH = 1,
parameter FLTLEN = 10,
parameter ID = 0,
parameter MSG_BUFFER_LENGTH = 64
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
// Takes input messages to set taps.
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output wire out_nd,
output wire [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output wire first_filter,
output wire error
);
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
localparam integer LOG_N = clog2(N);
localparam integer LOG_FLTLEN = clog2(FLTLEN);
wire [N-1:0] in_nds;
reg [N-1:0] in_nds_mask;
wire [WIDTH-1:0] out_datas[N-1:0];
reg [LOG_N-1:0] out_filter;
wire [N-1:0] out_nds;
wire [N-1:0] out_filter_unexpected;
wire out_filter_unexpected_error;
assign in_nds = in_nds_mask & {N{in_nd}};
assign out_nd = out_nds[out_filter];
assign out_data = out_datas[out_filter];
assign out_filter_unexpected_error = | out_filter_unexpected;
reg [`MSG_WIDTH-1:0] in_filter_msg;
reg in_filter_msg_nd;
wire [N-1:0] filter_errors;
wire filter_error;
assign filter_error = |filter_errors;
genvar i;
generate
for (i=0; i<N; i=i+1) begin: loop_0
// We got new data from a filter and weren't expecting it.
assign out_filter_unexpected[i] = ((i!=out_filter) & (out_nds[i]))?1'b1:1'b0;
reg in_m;
wire out_m;
wire [`MSG_WIDTH-1:0] out_filter_msg;
wire out_filter_msg_nd;
filter #(WIDTH, MWIDTH, FLTLEN, i) filter_0
(.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nds[i]),
.in_m(in_m),
.in_msg(in_filter_msg),
.in_msg_nd(in_filter_msg_nd),
.out_data(out_datas[i]),
.out_nd(out_nds[i]),
.out_m(out_m),
.out_msg(out_filter_msg),
.out_msg_nd(out_filter_msg_nd),
.error(filter_errors[i])
);
end
endgenerate
wire buffer_error;
wire [WIDTH-1:0] read_msg;
wire read_msg_ready;
reg delete_msg;
buffer_BB #(WIDTH, MSG_BUFFER_LENGTH) buffer_BB_0
(.clk(clk),
.rst_n(rst_n),
.write_strobe(in_msg_nd),
.write_data(in_msg),
.read_delete(delete_msg),
.read_full(read_msg_ready),
.read_data(read_msg),
.error(buffer_error)
);
localparam N_LENGTH = 10;
reg [N_LENGTH-1:0] which_filter;
// which_pos is one bit longer then we would expect.
// We use this to indicate a header is to be sent.
reg [LOG_FLTLEN:0] which_pos;
reg setting_taps;
reg [`MSG_WIDTH-1:0] filter_msg_header;
reg [`MSG_LENGTH_WIDTH-1:0] msg_length;
reg tap_set_error;
// Read from the msg buffer and forward messages on to filter modules.
always @ (posedge clk)
if (~rst_n)
begin
setting_taps <= 1'b0;
tap_set_error <= 1'b0;
msg_length <= FLTLEN;
end
else if (read_msg_ready)
begin
// If first bit is 1 then this is a header so we start reseting taps.
if (read_msg[`MSG_WIDTH-1])
begin
// FIXME: Check that length is correct.
// FIXME: Check that ID is correct.
which_filter <= {N_LENGTH{1'b0}};
// Now send a header to the first filter.
which_pos <= {LOG_FLTLEN{1'b0}};
setting_taps <= 1'b1;
in_filter_msg <= {1'b1, msg_length, 4'b0, {N_LENGTH{1'b0}}, 7'b0};
// Delete the received header from the buffer.
delete_msg <= 1'b1;
in_filter_msg_nd <= 1'b1;
// We tried to set taps while being in the middle of setting them.
if (setting_taps)
begin
tap_set_error <= 1'b1;
end
end
else if (setting_taps)
begin
in_filter_msg_nd <= 1'b1;
if (which_pos == FLTLEN)
begin
// We finished sending the taps for the previous filter.
// Send out a header for the next filter.
// `which_filter` has already been updated.
in_filter_msg <= {1'b1, msg_length, 4'b0, which_filter, 7'b0};
which_pos <= {LOG_FLTLEN{1'b0}};
delete_msg <= 1'b0;
end
else
begin
which_pos <= which_pos + 1;
in_filter_msg <= read_msg;
delete_msg <= 1'b1;
if (which_pos == FLTLEN-1)
begin
if (which_filter == N-1)
// If this is the last tap of the last filter we are finished.
begin
setting_taps <= 1'b0;
end
else
// If there is another filter then update `which_filter` so
// we send the header to the right place.
begin
which_pos <= which_pos + 1;
which_filter <= which_filter + 1;
end
end
end
end
else
begin
// A message is there but it's not a header and we're
// not setting taps so just delete it.
delete_msg <= 1'b1;
end // else: !if(setting_taps)
end
else
begin
// No message ready.
// Not setting any taps.
in_filter_msg_nd <= 1'b0;
// Not reading any taps.
delete_msg <= 1'b0;
end
// Pass the input stream to the filters.
always @ (posedge clk)
begin
if (~rst_n)
begin
in_nds_mask <= {{N-1{1'b0}}, 1'b1};
end
else if (in_nd)
begin
if (in_nds_mask[N-1])
in_nds_mask <= {{N-1{1'b0}}, 1'b1};
else
in_nds_mask <= in_nds_mask << 1;
end
end
// Get the output stream from the filters.
always @ (posedge clk)
if (~rst_n)
out_filter <= {LOG_N{1'b0}};
else if (out_nd)
if (out_filter == N-1)
out_filter <= {LOG_N{1'b0}};
else
out_filter <= out_filter + 1;
always @ (posedge clk)
begin
//if (error)
// $display("%d %d %d %d %d", out_filter_unexpected_error, buffer_write_error, buffer_read_error, tap_set_error, filter_error);
//$display("out_filter=%d in_nds=%b out_nds=%b", out_filter, in_nds, out_nds);
end
assign error = out_filter_unexpected_error | buffer_error | tap_set_error | filter_error;
endmodule |
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, set<T> S) { os << { ; for (auto s : S) os << s << ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class L, class R> ostream& operator<<(ostream& os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.F << : << m.S << ) ; return os << } ; } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int R = 65; char G[R][R]; int solve() { int n, m; cin >> n >> m; bool all = true, none = true; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> G[i][j]; if (G[i][j] == A ) none = false; else all = false; } } if (all) return 0; if (none) return -1; bool row = true; for (int i = 1; i <= m; ++i) if (G[1][i] == P ) row = false; if (row) return 1; row = true; for (int i = 1; i <= m; ++i) if (G[n][i] == P ) row = false; if (row) return 1; row = true; for (int i = 1; i <= n; ++i) if (G[i][1] == P ) row = false; if (row) return 1; row = true; for (int i = 1; i <= n; ++i) if (G[i][m] == P ) row = false; if (row) return 1; if (G[1][1] == A ) return 2; if (G[1][m] == A ) return 2; if (G[n][1] == A ) return 2; if (G[n][m] == A ) return 2; for (int i = 2; i <= n - 1; ++i) { bool eq = true; for (int j = 1; j <= m; ++j) { if (G[i][j] == P ) eq = false; } if (eq) return 2; } for (int i = 2; i <= m - 1; ++i) { bool eq = true; for (int j = 1; j <= n; ++j) { if (G[j][i] == P ) eq = false; } if (eq) return 2; } bool any = false; for (int i = 2; i <= n - 1; ++i) { if (G[i][1] == A || G[i][m] == A ) any = true; } for (int i = 2; i <= m - 1; ++i) { if (G[1][i] == A || G[n][i] == A ) any = true; } if (any) return 3; return 4; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << fixed << setprecision(25); int t; cin >> t; while (t--) { int ans = solve(); if (ans != -1) cout << ans << n ; else cout << MORTAL << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int isp[100005]; void pp() { for (long long int i = 2; i <= 100000; i++) { if (!isp[i]) { for (long long int j = i * i; j <= 100000; j += i) { isp[j] = 1; } } } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; pp(); while (t--) { long long int n, i, j, x, y; cin >> n; if (!isp[n]) { for (long long int i = 1; i <= n; i++) { for (long long int j = 1; j <= n; j++) { cout << 1 << ; } cout << n ; } continue; } x = -1; for (long long int i = n + 1; i <= 100000; i++) { if (!isp[i] && isp[i - n + 1]) { x = i - n + 1; break; } } for (long long int i = 1; i < n; i++) { for (long long int j = 1; j < n; j++) { cout << 1 << ; } cout << x << n ; } y = 0; for (long long int i = 1; i < n; i++) { y += x; cout << x << ; } for (long long int i = y; i <= 100000; i++) { if (!isp[i] && isp[i - y]) { x = i - y; break; } } cout << x << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = LLONG_MAX; const int inf = INT_MAX; const int mod = 1e9 + 7; const int pi = acos(-1); const int dx[8] = {0, 0, 1, -1, 1, 1, -1, -1}; const int dy[8] = {1, -1, 0, 0, 1, -1, 1, -1}; const int N = 2e5 + 5; const int MAXN = 1e5 + 1; int a[N], dp[N][6], p[N][6]; vector<int> v; void ans(int n, int val) { v.push_back(val); if (n == 1) { reverse(v.begin(), v.end()); for (int i = 0; i < (int)v.size(); i++) { cout << v[i] << ; } exit(0); } int to = p[n][val]; ans(n - 1, to); } int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= 5; i++) { dp[1][i] = 1; } for (int i = 2; i <= n; i++) { for (int j = 1; j <= 5; j++) { int w = INT_MIN; for (int k = 1; k <= 5; k++) { if (k == j) continue; if (a[i] > a[i - 1]) { if (j > k) w = max(w, dp[i - 1][k]); } if (a[i] < a[i - 1]) { if (j < k) w = max(w, dp[i - 1][k]); } if (a[i] == a[i - 1]) { w = max(w, dp[i - 1][k]); } } if (w == 1) { dp[i][j] = 1; int ans; for (int k = 1; k <= 5; k++) { if (k == j) continue; if (a[i] > a[i - 1]) { if (j > k) { if (dp[i - 1][k] == 1) { ans = k; break; } } } else if (a[i] < a[i - 1]) { if (j < k) { if (dp[i - 1][k] == 1) { ans = k; break; } } } else { if (dp[i - 1][k] == 1) { ans = k; break; } } } p[i][j] = ans; } else { dp[i][j] = INT_MIN; } } } for (int i = 1; i <= 5; i++) { if (dp[n][i] == 1) { ans(n, i); return 0; } } cout << -1; } |
`timescale 1ps / 1ps
`default_nettype none
module example (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
//debug
output wire [15:0] DEBUG_D,
output wire LED1,
output wire LED2,
output wire LED3,
output wire LED4,
output wire LED5,
inout wire FPGA_BUTTON,
inout wire SDA,
inout wire SCL
);
wire [15:0] BUS_ADD;
wire BUS_CLK, BUS_RD, BUS_WR, BUS_RST;
assign BUS_CLK = FCLK_IN;
fx2_to_bus i_fx2_to_bus (
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.BUS_CLK(BUS_CLK),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CS_FPGA()
);
reset_gen i_reset_gen (
.CLK(BUS_CLK),
.RST(BUS_RST)
);
//MODULE ADREESSES
localparam GPIO_BASEADDR = 16'h0000;
localparam GPIO_HIGHADDR = 16'h000f;
// USER MODULES //
wire [1:0] GPIO_NOT_USED;
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.IO_WIDTH(8),
.IO_DIRECTION(8'h1f) // 3 MSBs are input the rest output
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO({FPGA_BUTTON, GPIO_NOT_USED, LED5, LED4, LED3, LED2, LED1})
);
assign GPIO_NOT_USED = {LED2, LED1};
//For simulation
initial begin
$dumpfile("mio_example.vcd");
$dumpvars(0);
end
assign SDA = 1'bz;
assign SCL = 1'bz;
assign DEBUG_D = 16'ha5a5;
`ifdef COCOTB_SIM
assign FPGA_BUTTON = 0;
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:03:21 10/28/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart(
input clk,
input reset,
input rxin,
output txout
);
`define TXREG 3'b001
`define CONTROLTX 3'b011
`define RXREG 3'b101
`define CONTROLRX 3'b111
`define TXR 2'b00
`define CTX 2'b01
`define RXR 2'b10
`define CRX 2'b11
`define START 3'b000
`define WAITRX 3'b001
wire [7:0] to_tx;
reg [2:0] addr, pstate, nstate;
reg [1:0] addmux;
reg [3:0] din;
reg wr_rx, rd_rx, wr_tx, rd_tx;
uart_rx #(.PERIOD(8'h1A)) RX(
.clk (clk),
.reset (reset),
.wren (wr_rx),
.rden (rd_rx),
.din (8'b00000001),
.dout (to_tx),
.rxin (rxin),
.addr (addr)
);
uart_tx #(.PERIOD(8'h1A)) TX(
.clk (clk),
.reset (reset),
.wren (wr_tx),
.rden (rd_tx),
.din (to_tx),
.dout (dout),
.txout (txout),
.addr (addr)
);
always @* begin
addr = 3'b010;
case(addmux)
`TXR:
addr = `TXREG;
`CTX:
addr = `CONTROLTX;
`RXR:
addr = `RXREG;
`CRX:
addr = `CONTROLRX;
endcase
end
always @(posedge clk or posedge reset) begin
if(reset)
pstate <= `START;
else begin
pstate <= nstate;
end
end
always @* begin
wr_rx = 0; rd_rx = 0;
wr_tx = 0; rd_tx = 0;
nstate = pstate;
case(pstate)
`START: begin
wr_rx = 1;
addmux = `CRX;
nstate = `WAITRX;
end
`WAITRX: begin
rd_rx = 1;
if(to_tx[1])
//recieve is done/
end
endcase
end
endmodule |
#include <bits/stdc++.h> long long mod; long long solve(int dep, long long idx, long long left, long long right, long long l, long long r, long long u, long long v) { if (right < l) return 0; if (left > r) return 0; if (left >= l && right <= r) { long long delta = (1LL << dep); long long begin = idx, end = idx + (right - left) * delta; if (end < u) return 0; if (begin > v) return 0; if (begin < u) begin = begin + (u - begin) / delta * delta; if (begin < u) begin += delta; if (end > v) end = end - (end - v) / delta * delta; if (end > v) end -= delta; if (begin > end) return 0; long long total = (end - begin) / delta + 1; return ((total % mod) * ((begin + end) % mod)) % mod; } long long delta = (1LL << dep); long long mid = (left + right) / 2; return (solve(dep + 1, idx, left, mid, l, r, u, v) + solve(dep + 1, idx + delta, mid + 1, right, l, r, u, v)) % mod; } int main() { long long n; int m; while (scanf( %I64d%d%I64d , &n, &m, &mod) == 3) { mod *= 2; for (int i = 0; i < m; i++) { long long l, r, u, v; scanf( %I64d%I64d%I64d%I64d , &l, &r, &u, &v); printf( %I64d n , solve(0, 1, 1, n, l, r, u, v) / 2); } } return 0; } |
`include "../spi_ctl.v"
module test;
reg nss;
reg mosi;
reg sck;
wire miso;
wire [6:0] address_bus;
wire [7:0] data_bus;
wire read_n;
wire write_n;
spi_ctl s1(nss, mosi, sck, miso, address_bus, data_bus, read_n, write_n);
// There are no devices connected to the bus for this test
// bench so here we use write_data_bus to drive the bus
// when read cycle is enabled.
reg [7:0] write_data_bus;
assign data_bus = (~read_n) ? write_data_bus : 8'bz;
// data to be written to the slave
reg [7:0] w_mosi;
reg [4:0] i;
initial begin
$dumpfile("spi_ctl-test.vcd");
$dumpvars(0,test);
sck = 0;
mosi = 0;
nss = 1; // disabled
// This value will be read during a read from the bus.
// Used along with the assign = data_bus above.
write_data_bus = 8'hAA;
//write_data_bus = 8'h53; // 0 1 0 1 0 0 1 1
#2;
/*
* Given below are examples of a read cycle and a write cycle.
* Either or both can be uncommented to test their functionality.
* Each section contains comments that describe what
* values to look for (in Gtkwave) if it is operating properly.
*/
// *** EXAMPLE #1: WRITE CYCLE ***
#1 nss = 0; // enabled
//
// At the START of the FIRST byte you should see the following:
//
// both 'read_n' and 'write_n' high.
//
// At the END of the FIRST byte you should see the following:
//
// both 'read_n' and 'write_n' high.
//
// At the END of the SECOND byte you should see the following:
//
// 'read_n' high, 'write_n' LOW
//
// The value to be written (0xF3 in this example) driven
// to the data bus.
//
// And finally when NSS goes high (disabled) both 'read_n'
// and 'write_n' should go high (disabled).
// And the data bus should go high z.
//
w_mosi = 8'h01; // WRITE address 0x01
SPI_once();
w_mosi = 8'hF3; // value to be written
SPI_once();
#1 nss = 1; // disabled
// *** END EXAMPLE #1 ***
// *** EXAMPLE #2: READ CYCLE ***
/*
#1 nss = 0; // enabled
// What to look for?
//
// Refer to the figure in the documentation (doc/)
// title "Timing diagram of SPI read cycle".
// This should approximately match that diagram.
//
// At the START of the first byte you should see the following:
//
// 'count' set to 1 at the first SAMPLE edge of sck
//
// At the END of the first byte should see the following:
//
// The address should be on the 'address_bus'.
// In this case 0x85 (read 0x05) would result in 0x05
// If 0x84 was sent 0x04 would result.
//
// The value to read (in this case 0xAA in write_data_bus) should
// be on the 'data_bus'.
//
// 'rw' should be 1 for a read
//
// 'read_n' should go low (enabled) during the sample when
// count changes from 7 to 8.
//
// 'write_n' should remain high (disabled.
//
//w_mosi = 8'hD5; // READ address 0x55
w_mosi = 8'h85; // READ address 0x05
//w_mosi = 8'h84;
SPI_once();
//
// During the second cycle the MISO should reflect
// the value transferred to the master.
// (this value is not stored in this test bench so
// it is not easy to view).
// For example, if r_reg is loaded with 0xAA (change this
// value using 'write_bus_data'), the follwing values
// should be seen on the MISO pin during each SPI sample
// (remember that 0xA == 1010_b).
//
// t=n t=(n+A) (n+A > n)
// ---------------------
// MISO 1 0 1 0 1 0 1 0
//
w_mosi = 8'h33; // form feed, value is ignored
SPI_once();
#1 nss = 1; // disabled
// *** END EXAMPLE #2 ***
*/
#3 $finish;
end
// {{{ SPI_once()
/*
* SPI_once()
*
* Perform a single 8-bit SPI cycle.
*
* It mutates the global variables: mosi, sck
* And it writes to mosi whatever value is in w_mosi.
*
* It does not mutate nss, this is left to the controlling
* block.
*/
task SPI_once;
begin
// enable SPI and assign the first value
mosi = w_mosi[7];
// and finish the remaining 7 bits
i = 7;
repeat (7) begin
i = i - 1;
#1;
// sample
sck = 1;
#1;
// propagate
sck = 0;
mosi = w_mosi[i];
end
#1 sck = 1;
#1 sck = 0; // CPOL = 0
end
endtask
// }}}
endmodule
// vim:foldmethod=marker
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: b2m_kbd.v
//
// Keyboard interface design file of Bashkiria-2M replica.
module b2m_kbd(
input clk,
input reset,
input ps2_clk,
input ps2_dat,
input[8:0] addr,
output reg cpurst,
output reg[7:0] odata);
reg[7:0] keystate[10:0];
always @(addr,keystate) begin
if (addr[8])
odata =
(keystate[8] & {8{addr[0]}})|
(keystate[9] & {8{addr[1]}})|
(keystate[10] & {8{addr[2]}});
else
odata =
(keystate[0] & {8{addr[0]}})|
(keystate[1] & {8{addr[1]}})|
(keystate[2] & {8{addr[2]}})|
(keystate[3] & {8{addr[3]}})|
(keystate[4] & {8{addr[4]}})|
(keystate[5] & {8{addr[5]}})|
(keystate[6] & {8{addr[6]}})|
(keystate[7] & {8{addr[7]}});
end
reg[2:0] c;
reg[3:0] r;
reg extkey;
reg unpress;
reg[3:0] prev_clk;
reg[11:0] shift_reg;
wire[11:0] kdata = {ps2_dat,shift_reg[11:1]};
wire[7:0] kcode = kdata[9:2];
always begin
case (kcode)
8'h4E: {c,r} <= 7'h74; // -
8'h41: {c,r} <= 7'h05; // ,
8'h4C: {c,r} <= 7'h15; // ;
8'h55: {c,r} <= 7'h25; // =
8'h0E: {c,r} <= 7'h35; // `
8'h5D: {c,r} <= 7'h55; // \!
8'h45: {c,r} <= 7'h65; // 0
8'h16: {c,r} <= 7'h45; // 1
8'h1E: {c,r} <= 7'h64; // 2
8'h26: {c,r} <= 7'h54; // 3
8'h25: {c,r} <= 7'h44; // 4
8'h2E: {c,r} <= 7'h34; // 5
8'h36: {c,r} <= 7'h24; // 6
8'h3D: {c,r} <= 7'h14; // 7
8'h3E: {c,r} <= 7'h04; // 8
8'h46: {c,r} <= 7'h75; // 9
8'h1C: {c,r} <= 7'h10; // A
8'h32: {c,r} <= 7'h61; // B
8'h21: {c,r} <= 7'h42; // C
8'h23: {c,r} <= 7'h02; // D
8'h24: {c,r} <= 7'h22; // E
8'h2B: {c,r} <= 7'h60; // F
8'h34: {c,r} <= 7'h72; // G
8'h33: {c,r} <= 7'h52; // H
8'h43: {c,r} <= 7'h43; // I
8'h3B: {c,r} <= 7'h01; // J
8'h42: {c,r} <= 7'h31; // K
8'h4B: {c,r} <= 7'h30; // L
8'h3A: {c,r} <= 7'h73; // M
8'h31: {c,r} <= 7'h32; // N
8'h44: {c,r} <= 7'h23; // O
8'h4D: {c,r} <= 7'h53; // P
8'h15: {c,r} <= 7'h51; // Q
8'h2D: {c,r} <= 7'h41; // R
8'h1B: {c,r} <= 7'h63; // S
8'h2C: {c,r} <= 7'h20; // T
8'h3C: {c,r} <= 7'h00; // U
8'h2A: {c,r} <= 7'h21; // V
8'h1D: {c,r} <= 7'h40; // W
8'h22: {c,r} <= 7'h13; // X
8'h35: {c,r} <= 7'h11; // Y
8'h1A: {c,r} <= 7'h62; // Z
8'h54: {c,r} <= 7'h71; // [
8'h5B: {c,r} <= 7'h03; // ]
8'h0B: {c,r} <= 7'h50; // F6
8'h83: {c,r} <= 7'h70; // F7
8'h0A: {c,r} <= 7'h12; // F8
8'h01: {c,r} <= 7'h33; // F9
8'h29: {c,r} <= 7'h06; // space
8'h0D: {c,r} <= 7'h16; // tab
8'h66: {c,r} <= 7'h26; // bksp
8'h7C: {c,r} <= 7'h46; // gray*
8'h07: {c,r} <= 7'h56; // F12 - stop
8'h7B: {c,r} <= 7'h66; // gray-
8'h5A: {c,r} <= 7'h76; // enter
8'h59: {c,r} <= 7'h07; // rshift
8'h11: {c,r} <= 7'h17; // lalt
8'h14: {c,r} <= extkey ? 7'h37 : 7'h27; // rctrl + lctrl
8'h76: {c,r} <= 7'h47; // esc
8'h78: {c,r} <= 7'h67; // F11 - rus
8'h12: {c,r} <= 7'h77; // lshift
8'h6C: {c,r} <= 7'h08; // 7 home
8'h74: {c,r} <= 7'h18; // 6 right
8'h73: {c,r} <= 7'h28; // 5 center
8'h6B: {c,r} <= 7'h38; // 4 left
8'h7A: {c,r} <= 7'h48; // 3 pgdn
8'h72: {c,r} <= 7'h58; // 2 down
8'h69: {c,r} <= 7'h68; // 1 end
8'h70: {c,r} <= 7'h78; // 0 ins
8'h4A: {c,r} <= extkey ? 7'h36 : 7'h09; // gray/ + /
8'h71: {c,r} <= 7'h19; // . del
8'h52: {c,r} <= 7'h29; // '
8'h49: {c,r} <= 7'h39; // .
8'h7D: {c,r} <= 7'h69; // 9 pgup
8'h75: {c,r} <= 7'h79; // 8 up
8'h05: {c,r} <= 7'h7A; // F1
8'h06: {c,r} <= 7'h6A; // F2
8'h04: {c,r} <= 7'h5A; // F3
8'h0C: {c,r} <= 7'h4A; // F4
8'h03: {c,r} <= 7'h3A; // F5
default: {c,r} <= 7'h7F;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
extkey <= 0;
unpress <= 0;
keystate[0] <= 0;
keystate[1] <= 0;
keystate[2] <= 0;
keystate[3] <= 0;
keystate[4] <= 0;
keystate[5] <= 0;
keystate[6] <= 0;
keystate[7] <= 0;
keystate[8] <= 0;
keystate[9] <= 0;
keystate[10] <= 0;
cpurst <= 0;
end else begin
prev_clk <= {ps2_clk,prev_clk[3:1]};
if (prev_clk==4'b1) begin
if (kdata[11]==1'b1 && ^kdata[10:2]==1'b1 && kdata[1:0]==2'b1) begin
shift_reg <= 12'hFFF;
if (kcode==8'hE0) extkey <= 1'b1; else
if (kcode==8'hF0) unpress <= 1'b1; else
begin
extkey <= 0;
unpress <= 0;
if(r!=4'hF) keystate[r][c] <= ~unpress;
if(kcode == 8'h7E && unpress == 1'b1) cpurst <= 1'b1; else cpurst <= 1'b0;
end
end else
shift_reg <= kdata;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &t) { t = 0; char ch = getchar(); int f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } do { (t *= 10) += ch - 0 ; ch = getchar(); } while ( 0 <= ch && ch <= 9 ); t *= f; } const long long mod = 998244353; long long ksm(long long x, long long y) { if (x < 0) x += mod; if (x >= mod) x -= mod; long long res = 1; while (y) { if (y & 1) res = res * x % mod; x = x * x % mod; y >>= 1; } return res; } long long n, m, N, L, R, ans, x, y; int main() { read(n); read(m); read(L); read(R); N = n * m; x = R / 2 - (L - 1) / 2; y = R - L + 1 - x; if (N % 2 == 1) ans = ksm(x + y, N); else { ans = ksm(x + y, N) + ksm(x - y, N); ans %= mod; if (N % 2 == 0) ans = ans * ksm(2, mod - 2) % mod; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; using INT = long long; string a[111]; int main() { int n; string s; cin >> s; cin >> n; int flag = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == s) flag |= 3; if (a[i][1] == s[0]) flag |= 1; if (a[i][0] == s[1]) flag |= 2; } if (flag == 3) return puts( YES ), 0; return puts( NO ), 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, x, y, sum, cnt, ans; int main() { printf( red n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_SYMBOL_V
`define SKY130_FD_SC_LS__XOR3_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_SYMBOL_V
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 19/09/2010
Design Name: reverse
*******************************************************************/
`timescale 1ns/1ns
module reverse
#(parameter
C_CNT_BW = 32,
C_RETRY_DELAY = 16
)
(
input clk ,
input rstn ,
//-- to/from producer/consumer ----
output p_prdy ,
input p_crdy ,
input p_cerr ,
output [31:0] p_data ,
input c_prdy ,
output c_crdy ,
output c_cerr ,
input [31:0] c_data ,
//-- to/from reconfiguration controller----
input rc_reqn ,
output rc_ackn
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
/* main data register: data1,2 */
wire data1_wr_en, data2_wr_en;
wire is_data_1; wire is_data_2; wire is_1_or_2;
reg [31:0] data1,data2;
/* retry & timeout counter */
reg [7:0] retrycnt; wire is_retry;
reg [3:0] tocnt;
/* main fsm */
reg [3:0] state_c, state_n;
localparam [3:0]
S_Rd1 = 4'd0,
S_Rd2 = 4'd1,
S_Wr1 = 4'd2,
S_Wr2 = 4'd3,
S_ReTry1 = 4'd4,
S_ReTry2 = 4'd5,
S_IDLE = 4'd15;
//-------------------------------------------------------------------
// Datapath Registers
//-------------------------------------------------------------------
/* the retry & timeout counter */
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
retrycnt <= 8'h0;
end else begin
if ((state_c == S_ReTry1)||(state_c == S_ReTry2)) retrycnt <= retrycnt+1'b1;
else if ((state_c == S_Wr1)||(state_c == S_Wr2)) retrycnt <= 'b0;
end
end
assign is_retry = (retrycnt == C_RETRY_DELAY-1);
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
tocnt <= 4'h0;
end else begin
if (c_prdy && ~c_crdy) tocnt <= tocnt + 'h1;
else tocnt <= 4'h0;
end
end
assign c_cerr = (tocnt == 4'hf) & (~c_crdy);
/* the data1,2 register */
assign data1_wr_en = c_prdy & c_crdy & is_data_1;
assign data2_wr_en = c_prdy & c_crdy & is_data_2;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
data1 <= 32'h0;
data2 <= 32'h0;
end else begin
if (data1_wr_en) data1 <= c_data;
if (data2_wr_en) data2 <= c_data;
end
end
/* assigning the output signals */
assign p_data = (is_1_or_2)? data2: data1;
/* instantiate the stastical counter */
stat_cnt #(C_CNT_BW) stat_0(
.clk(clk),
.rstn(rstn),
//-- to/from the datapath to be monitored----
.din(c_data),
.din_valid(c_prdy & c_crdy),
.dout(p_data),
.dout_valid(p_prdy & p_crdy)
);
//-------------------------------------------------------------------
// Main FSM - Reverse fsm
//-------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
if (~rstn)
state_c <= S_IDLE;
else
state_c <= state_n;
end
always @(*) begin
case (state_c)
S_IDLE:begin state_n = (c_prdy)? S_Rd1:S_IDLE; end
S_Rd1:begin state_n = (c_prdy)? S_Rd2:S_Rd1; end
S_Rd2:begin state_n = (c_prdy)? S_Wr1:S_Rd2; end
S_Wr1:begin state_n = (p_crdy)? S_Wr2: (p_cerr)? S_ReTry1: S_Wr1; end
S_Wr2:begin state_n = (p_crdy)? S_IDLE: (p_cerr)? S_ReTry2: S_Wr2; end
S_ReTry1: begin state_n = (is_retry)? S_Wr1: S_ReTry1; end
S_ReTry2: begin state_n = (is_retry)? S_Wr2: S_ReTry2; end
default: begin state_n = S_IDLE; end
endcase
end
assign p_prdy = (state_c == S_Wr1) || (state_c == S_Wr2);
assign c_crdy = (state_c == S_Rd1) || (state_c == S_Rd2);
assign is_data_1 = (state_c == S_Rd1);
assign is_data_2 = (state_c == S_Rd2);
assign is_1_or_2 = (state_c == S_Wr1);
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(*) begin
if (state_c==S_Rd1) state_ascii <= "RD1";
else if (state_c==S_Rd2) state_ascii <= "RD2";
else if (state_c==S_Wr1) state_ascii <= "WR1";
else if (state_c==S_Wr2) state_ascii <= "WR2";
else if (state_c==S_ReTry1) state_ascii <= "RETRY1";
else if (state_c==S_ReTry2) state_ascii <= "RETRY2";
else if (state_c==S_IDLE) state_ascii <= "IDLE";
else state_ascii <= "ERROR";
end
// synthesis translate_on
//-------------------------------------------------------------------
// FilterSync
//-------------------------------------------------------------------
/* filter_sync: synchronize by monitoring module IO */
/* instantiate the reconfiguration add-on: filter_sync */
filter_sync #(32'h1,32'h1) sync_0(
.clk(clk),
.rstn(rstn),
//-- to/from core----
.is_data_in(c_prdy & c_crdy),
.is_data_out(p_prdy & p_crdy),
//-- to/from centeral reconfiguration controller----
.rc_reqn(rc_reqn),
.rc_ackn(rc_ackn)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, a[10][110], b[410]; int main() { while (~scanf( %d%d , &n, &m)) { memset(a, 0, sizeof(a)); for (int i = 1; i <= min(m, 2 * n); i++) { if (i & 1) { a[1][(i + 1) >> 1] = i; } else { a[4][i >> 1] = i; } } for (int i = 2 * n + 1; i <= m; i++) { if (i & 1) { a[2][(i - 2 * n + 1) >> 1] = i; } else { a[3][(i - 2 * n) >> 1] = i; } } int cnt = 0; for (int i = 1; i <= n; i++) { if (a[2][i]) b[cnt++] = a[2][i]; if (a[1][i]) b[cnt++] = a[1][i]; if (a[3][i]) b[cnt++] = a[3][i]; if (a[4][i]) b[cnt++] = a[4][i]; } for (int i = 0; i < cnt - 1; i++) printf( %d , b[i]); printf( %d n , b[cnt - 1]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_PP_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s6s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_PP_SYMBOL_V
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_4_V
`define SKY130_FD_SC_LP__O21A_4_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_4_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:04:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.v
// Design : system_inverter_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_0_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
#include <bits/stdc++.h> int main() { int n, k; scanf( %d %d , &n, &k); char a[n]; scanf( %s , a); int i, start, end; for (i = 0; i < n; i++) { if (a[i] == G ) start = i; if (a[i] == T ) end = i; } int sign = start - end; if (start > end) k = -k; while ((sign * (start - end)) > 0) { start = start + k; if (a[start] == # ) { printf( NO ); break; } if (a[start] == T ) { printf( YES ); break; } } if (((sign * (start - end)) < 0) && (a[start] != # )) printf( NO ); return 0; } |
#include<bits/stdc++.h> using namespace std; #define M 500000 typedef long long ll; typedef unsigned long long ull; inline ll read() { char ch; ll f = 1, res = 0; while ((ch = getchar()) < 0 || ch > 9 ) if (ch == - ) f = -1; while (ch >= 0 && ch <= 9 ) { res = (res << 1) + (res << 3) + (ch ^ 48); ch = getchar(); } return f * res; } inline void pt(ll u,ll mod) { printf( %lld , u); if (mod == 1) putchar( ); else if (mod == 2) putchar( n ); } ll mod=1e9+7; ll arr[M]; ll p[M]; int main() { //freopen( ../in , r , stdin); //freopen( ../out , w , stdout); p[1]=1; p[0]=1; for(ll i=2;i<M;i++) p[i]=p[i-1]*i%mod; ll q = read(); while (q--) { ll n = read(); ll k = pow(2, 40) + 0.1 - 1; for (ll i = 0; i < n; i++) { ll t = read(); arr[i] = t; k &= t; } ll cnt = 0; for (ll i = 0; i < n; i++) { if (arr[i] == k) cnt++; } ll ans = cnt * (cnt - 1) % mod; pt(ans * p[n - 2] % mod, 2); } return 0; } |
#include <bits/stdc++.h> // #include <ext/pb_ds/assoc_container.hpp> // #include <ext/pb_ds/tree_policy.hpp> using namespace std; // using namespace __gnu_pbds; #define lli long long int #define llu unsigned long long int #define pb push_back #define rt return 0 #define endln n #define all(x) x.begin(), x.end() #define sz(x) (lli)(x.size()) #define len(x) (lli)(x.length()) const lli MOD = 1e9 + 7; const double PI = 2 * acos(0.0); // cout << fixed << setprecision(0) << pi <<endl; // typedef tree<int, null_type, less<int>, rb_tree_tag, // tree_order_statistics_node_update> // new_data_set; // for multiset // typedef tree<int, null_type, less_equal<int>, rb_tree_tag, // tree_order_statistics_node_update> // new_data_set; // order_of_key(val): returns the number of values less than val // find_by_order(k): returns an iterator to the kth largest element (0-based) void solve() { lli n, a; cin >> n; vector<lli> v; for (lli i = 0; i < n; i++) { cin >> a; v.pb(a); } for (lli i = 0; i < n; i++) { lli tmp = v[i], ind = 0, one; while (tmp > 0) { if (tmp % 2 == 1) { one = ind; } tmp /= 2; ind++; } lli p = pow(2, one); cout << p << ; } cout << endl; } int main(void) { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); lli t; cin >> t; while (t--) solve(); rt; } |
#include <bits/stdc++.h> using namespace std; int main() { char str[200005]; gets(str); vector<char> v; if (strlen(str) > 1) { v.push_back(str[0]); v.push_back(str[1]); } else { cout << str; return 0; } int l = strlen(str); int len; for (int i = 2; i < l; i++) { len = v.size(); if (str[i] == v[len - 1] && str[i] == v[len - 2]) continue; if (v[len - 3] == v[len - 2] && str[i] == v[len - 1]) continue; else v.push_back(str[i]); } len = v.size(); for (int i = 0; i < len; i++) printf( %c , v[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T BigMod(T b, T p, T m) { if (p == 0) return 1; if (p % 2 == 0) { T s = BigMod(b, p / 2, m); return ((s % m) * (s % m)) % m; } return ((b % m) * (BigMod(b, p - 1, m) % m)) % m; } template <typename T> T ModInv(T b, T m) { return BigMod(b, m - 2, m); } template <typename T> T in() { char ch; T n = 0; bool ng = false; while (1) { ch = getchar(); if (ch == - ) { ng = true; ch = getchar(); break; } if (ch >= 0 && ch <= 9 ) break; } while (1) { n = n * 10 + (ch - 0 ); ch = getchar(); if (ch < 0 || ch > 9 ) break; } return (ng ? -n : n); } template <typename T> T POW(T B, T printf) { if (printf == 0) return 1; if (printf & 1) return B * POW(B, printf - 1); else return (POW(B, printf / 2) * POW(B, printf / 2)); } template <typename T> T Bigmod(T b, T p, T m) { if (p == 0) return 1; else if (!(p & 1)) return (Bigmod(b, p / 2, m) * Bigmod(b, p / 2, m)) % m; else return ((b % m) * Bigmod(b, p - 1, m)) % m; } template <typename T> T Dis(T x1, T y1, T x2, T y2) { return sqrt((x1 - x2 * x1 - x2) + (y1 - y2 * y1 - y2)); } template <typename T> T Angle(T x1, T y1, T x2, T y2) { return atan(double(y1 - y2) / double(x1 - x2)); } template <typename T> T DIFF(T a, T b) { T d = a - b; if (d < 0) return -d; else return d; } template <typename T> T ABS(T a) { if (a < 0) return -a; else return a; } template <typename T> T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } template <typename T> T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } template <typename T> T euclide(T a, T b, T &x, T &y) { if (a < 0) { T d = euclide(-a, b, x, y); x = -x; return d; } if (b < 0) { T d = euclide(a, -b, x, y); y = -y; return d; } if (b == 0) { x = 1; y = 0; return a; } else { T d = euclide(b, a % b, x, y); T t = x; x = y; y = t - (a / b) * y; return d; } } template <typename T> void ia(T a[], int n) { for (int i = 0; i < n; i++) cin >> a[i]; } template <typename T> void pa(T a[], int n) { for (int i = 0; i < n - 1; i++) cout << a[i] << ; cout << a[n - 1] << endl; } template <typename T> long long int isLeft(T a, T b, T c) { return (a.x - b.x) * (b.y - c.y) - (b.x - c.x) * (a.y - b.y); } int Set(int N, int pos) { return N = N | (1 << pos); } int Reset(int N, int pos) { return N = N & ~(1 << pos); } bool Check(int N, int pos) { return (bool)(N & (1 << pos)); } template <class T, class first> inline T togglebit(T a, first i) { T t = 1; return (a ^ (t << i)); } int toInt(string s) { int sm; stringstream ss(s); ss >> sm; return sm; } int toLlint(string s) { long long int sm; stringstream ss(s); ss >> sm; return sm; } int cdigittoint(char ch) { return ch - 0 ; } bool isVowel(char ch) { ch = toupper(ch); if (ch == A || ch == U || ch == I || ch == O || ch == E ) return true; return false; } bool isConst(char ch) { if (isalpha(ch) && !isVowel(ch)) return true; return false; } double DEG(double x) { return (180.0 * x) / (2.0 * acos(0.0)); } double RAD(double x) { return (x * (double)2.0 * acos(0.0)) / (180.0); } vector<int> adj[200007], dag[200007], par[200007]; int DP[200007][18], siz[200007]; long long int dis[200007]; int L[200007]; int inDeg[200007]; bool vis[200007]; void Init(int n) { for (int i = 0; i <= n; i++) { dis[i] = 1LL << 60; adj[i].clear(); dag[i].clear(); par[i].clear(); inDeg[i] = siz[i] = vis[i] = 0; for (int j = 0; j < 18; j++) DP[i][j] = -1; } } void Update(int u, int p) { DP[u][0] = p; L[u] = L[p] + 1; adj[p].push_back(u); for (int i = 1; i < 18; i++) if (DP[u][i - 1] != -1) DP[u][i] = DP[DP[u][i - 1]][i - 1]; } int LCA(int p, int q) { if (L[p] < L[q]) swap(p, q); for (int i = 18 - 1; i >= 0; i--) if (L[p] - (1 << i) >= L[q]) p = DP[p][i]; if (p == q) return p; for (int i = 18 - 1; i >= 0; i--) if (DP[p][i] != -1 && DP[p][i] != DP[q][i]) { p = DP[p][i]; q = DP[q][i]; } return DP[p][0]; } void Dijkstra(int n, int s) { set<pair<long long int, long long int> > pq; pq.insert(make_pair(0, s)); dis[s] = 0; L[s] = 1; while (!pq.empty()) { pair<long long int, long long int> tmp = *pq.begin(); pq.erase(pq.begin()); int u = tmp.second; for (int i = 0; i < adj[u].size(); i += 2) { int v = adj[u][i]; int w = adj[u][i + 1]; if (dis[v] > dis[u] + w) { dis[v] = dis[u] + w; pq.insert(make_pair(dis[v], v)); } } } for (int i = 1; i <= n; i++) { for (int j = 0; j < adj[i].size(); j += 2) { int v = adj[i][j]; int w = adj[i][j + 1]; if (dis[i] + w == dis[v]) { inDeg[v]++; dag[i].push_back(v); par[v].push_back(i); } } adj[i].clear(); } } void TopSort(int s) { queue<int> q; q.push(s); L[s] = 1; while (!q.empty()) { int u = q.front(); q.pop(); if (!par[u].empty()) { int lca = par[u][0]; for (int i = 1; i < par[u].size(); i++) { lca = LCA(lca, par[u][i]); } Update(u, lca); } for (int i = 0; i < dag[u].size(); i++) { int v = dag[u][i]; inDeg[v]--; if (!inDeg[v]) q.push(v); } } } void Dfs(int u) { siz[u] = 1; vis[u] = 1; for (int i = 0; i < adj[u].size(); i++) { Dfs(adj[u][i]); siz[u] += siz[adj[u][i]]; } } int main() { int n, m, s; scanf( %d%d%d , &n, &m, &s); Init(n); for (int i = 1; i <= m; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); adj[u].push_back(v); adj[u].push_back(w); adj[v].push_back(u); adj[v].push_back(w); } Dijkstra(n, s); TopSort(s); Dfs(s); int mx = 0; for (int i = 1; i <= n; i++) { if (i != s) mx = max(mx, siz[i]); } cout << mx << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Node { Node *ch[26]; Node() { for (int i = 0; i < 26; i++) ch[i] = NULL; } } * Root; struct Trie { void init() { Root = new Node(); } void ins(Node *t, string s) { for (int i = 0; i < s.size(); i++) { int id = s[i] - a ; if (t->ch[id] == NULL) { Node *p = new Node(); t->ch[id] = p; } t = t->ch[id]; } } void del(Node *t) { for (int i = 0; i < 26; i++) if (t->ch[i] != NULL) del(t->ch[i]); free(t); } bool win(Node *t) { for (int i = 0; i < 26; i++) if (t->ch[i] != NULL) if (!win(t->ch[i])) return true; return false; } bool lose(Node *t) { bool flag = 0; for (int i = 0; i < 26; i++) if (t->ch[i] != NULL) { flag = true; if (!lose(t->ch[i])) return true; } return false || !flag; } }; const int Maxn = 1e5 + 8; char s[Maxn]; int main() { Trie T; T.init(); int n, k; scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %s , s); T.ins(Root, s); } bool win = T.win(Root), lose = T.lose(Root); if (win && lose) puts( First ); else { if (win) { if (k & 1) puts( First ); else puts( Second ); } else puts( Second ); } return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_qpram #(
parameter depth = 11 /* < log2 of the capacity in bytes */
) (
input sys_clk,
input [depth-1:0] raa, /* < in bytes, 16-bit aligned */
output reg [15:0] rda,
input [depth-1:0] rab,
output reg [15:0] rdb,
input [depth-1:0] rac,
output reg [15:0] rdc,
input [depth-1:0] rad,
output reg [15:0] rdd,
input we,
input [depth-1:0] wa, /* < in bytes, 256-bit aligned */
input [255:0] wd
);
wire [127:0] rd128a;
wire [127:0] rd128b;
wire [127:0] rd128c;
wire [127:0] rd128d;
reg [2:0] rala;
reg [2:0] ralb;
reg [2:0] ralc;
reg [2:0] rald;
always @(posedge sys_clk) begin
rala <= raa[3:1];
ralb <= rab[3:1];
ralc <= rac[3:1];
rald <= rad[3:1];
end
always @(*) begin
case(rala)
3'd0: rda = rd128a[127:112];
3'd1: rda = rd128a[111:96];
3'd2: rda = rd128a[95:80];
3'd3: rda = rd128a[79:64];
3'd4: rda = rd128a[63:48];
3'd5: rda = rd128a[47:32];
3'd6: rda = rd128a[31:16];
default: rda = rd128a[15:0];
endcase
case(ralb)
3'd0: rdb = rd128b[127:112];
3'd1: rdb = rd128b[111:96];
3'd2: rdb = rd128b[95:80];
3'd3: rdb = rd128b[79:64];
3'd4: rdb = rd128b[63:48];
3'd5: rdb = rd128b[47:32];
3'd6: rdb = rd128b[31:16];
default: rdb = rd128b[15:0];
endcase
case(ralc)
3'd0: rdc = rd128c[127:112];
3'd1: rdc = rd128c[111:96];
3'd2: rdc = rd128c[95:80];
3'd3: rdc = rd128c[79:64];
3'd4: rdc = rd128c[63:48];
3'd5: rdc = rd128c[47:32];
3'd6: rdc = rd128c[31:16];
default: rdc = rd128c[15:0];
endcase
case(rald)
3'd0: rdd = rd128d[127:112];
3'd1: rdd = rd128d[111:96];
3'd2: rdd = rd128d[95:80];
3'd3: rdd = rd128d[79:64];
3'd4: rdd = rd128d[63:48];
3'd5: rdd = rd128d[47:32];
3'd6: rdd = rd128d[31:16];
default: rdd = rd128d[15:0];
endcase
end
tmu2_tdpram #(
.depth(depth-4),
.width(128)
) ram0 (
.sys_clk(sys_clk),
.a(we ? {wa[depth-1:5], 1'b0} : raa[depth-1:4]),
.we(we),
.di(wd[255:128]),
.do(rd128a),
.a2(we ? {wa[depth-1:5], 1'b1} : rab[depth-1:4]),
.we2(we),
.di2(wd[127:0]),
.do2(rd128b)
);
tmu2_tdpram #(
.depth(depth-4),
.width(128)
) ram1 (
.sys_clk(sys_clk),
.a(we ? {wa[depth-1:5], 1'b0} : rac[depth-1:4]),
.we(we),
.di(wd[255:128]),
.do(rd128c),
.a2(we ? {wa[depth-1:5], 1'b1} : rad[depth-1:4]),
.we2(we),
.di2(wd[127:0]),
.do2(rd128d)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire GCLK_b ;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b , m0n, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( ( GATE_delayed === 1'b0 ) & awake );
assign GATE_awake = ( ( SCE_delayed === 1'b0 ) & awake );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); int main() { int n; double R, r; double st; while (scanf( %d %lf , &n, &R) != EOF) { st = pi / (1.0 * n); r = sin(st) * R / (1 - sin(st)); printf( %.7lf n , r); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 2000 + 5; int s, n, m, a[maxN]; vector<int> p[maxN]; vector<int> f[maxN], g[maxN]; void initialize() { ios::sync_with_stdio(false); cin >> n >> s; s--; for (int i = 0; i < n; ++i) cin >> a[i]; vector<int> t(a, a + n); sort(t.begin(), t.end()); t.erase(unique(t.begin(), t.end()), t.end()); for (int i = 0; i < n; ++i) a[i] = lower_bound(t.begin(), t.end(), a[i]) - t.begin() + 1; m = t.size(); for (int i = 0; i < n; ++i) p[a[i]].push_back(i); p[0].push_back(s); f[0].push_back(0); g[0].push_back(-1); } int cyc(int x, int y) { return y < x ? y + n - x : y - x; } int cont(int x, int y) { return cyc(y, x); } int sp(int x, int y) { return min(cyc(x, y), cont(x, y)); } template <typename T> bool chmin(T &x, const T &y) { return y < x ? x = y, true : false; } int solve() { for (int st = 1; st <= m; ++st) { int sz = p[st].size(); f[st].assign(sz, maxN * maxN); g[st].assign(sz, -1); for (int i = 0; i < sz; ++i) { int pre = i - 1, post = i + 1; if (pre == -1) pre = sz - 1; if (post == sz) post = 0; for (int j = 0; j < (int)p[st - 1].size(); ++j) { chmin(f[st][i], f[st - 1][j] + sp(p[st - 1][j], p[st][pre]) + cont(p[st][pre], p[st][i])) && (g[st][i] = j); chmin(f[st][i], f[st - 1][j] + sp(p[st - 1][j], p[st][post]) + cyc(p[st][post], p[st][i])) && (g[st][i] = j); } } } return *min_element(f[m].begin(), f[m].end()); } void psp(int x, int y) { if (cyc(x, y) <= cont(x, y)) printf( +%d n , cyc(x, y)); else printf( -%d n , cont(x, y)); } void print(int st, int i) { if (st == 0) return; int j = g[st][i]; print(st - 1, j); int sz = p[st].size(); int pre = i - 1, post = i + 1; if (pre == -1) pre = sz - 1; if (post == sz) post = 0; int cpre = f[st - 1][j] + sp(p[st - 1][j], p[st][pre]) + cont(p[st][pre], p[st][i]); int cpost = f[st - 1][j] + sp(p[st - 1][j], p[st][post]) + cyc(p[st][post], p[st][i]); if (cpre < cpost) { psp(p[st - 1][j], p[st][pre]); while (pre != i) { int pp = pre - 1; if (pp == -1) pp = sz - 1; printf( -%d n , cont(p[st][pre], p[st][pp])); pre = pp; } } else { psp(p[st - 1][j], p[st][post]); while (post != i) { int pp = post + 1; if (pp == sz) pp = 0; printf( +%d n , cyc(p[st][post], p[st][pp])); post = pp; } } } int main() { initialize(); cout << solve() << endl; print(m, min_element(f[m].begin(), f[m].end()) - f[m].begin()); return 0; } |
module Fifo36E1TestSuite_UserTop_1(input deqClk, input enqClk, input reset,
output io_enq_ready,
input io_enq_valid,
input [71:0] io_enq_bits,
input io_deq_ready,
output io_deq_valid,
output[71:0] io_deq_bits,
output[8:0] io_count
);
wire[7:0] T0;
wire[63:0] T1;
wire[71:0] T2;
wire T3;
wire T4;
wire[63:0] testFifo_io_dout;
wire[7:0] testFifo_io_dop;
wire testFifo_io_full;
wire testFifo_io_empty;
`ifndef SYNTHESIS
// synthesis translate_off
// assign io_count = {1{$random}};
// synthesis translate_on
`endif
assign T0 = io_enq_bits[7:0];
assign T1 = io_enq_bits[71:8];
assign io_deq_bits = T2;
assign T2 = {testFifo_io_dout, testFifo_io_dop};
assign io_deq_valid = T3;
assign T3 = testFifo_io_empty ^ 1'h1;
assign io_enq_ready = T4;
assign T4 = testFifo_io_full ^ 1'h1;
Fifo36E1 # (
.ALMOST_FULL_OFFSET(500),
.ALMOST_EMPTY_OFFSET(100),
.FIRST_WORD_FALL_THROUGH(TRUE),
.DO_REG(1),
.DATA_WIDTH(72),
.FIFO_MODE("FIFO36"),
.EN_SYN(FALSE),
.SRVAL(0),
.INIT(0)
) testFifo(.deqClk(deqClk), .enqClk(enqClk), .RST(reset),
.io_din( T1 ),
.io_dip( T0 ),
.io_wren( io_enq_valid ),
.io_rden( io_deq_ready ),
.io_dout( testFifo_io_dout ),
.io_dop( testFifo_io_dop ),
.io_full( testFifo_io_full ),
//.io_almostFull( )
.io_empty( testFifo_io_empty )
//.io_almostEmpty( )
//.io_rdCount( )
//.io_wrCount( )
//.io_wrErr( )
//.io_rdErr( )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2007; const int mod = 998244353; template <class I> inline void read(I &x) { int f = 1; char c; for (c = getchar(); c < 0 || c > 9 ; c = getchar()) if (c == - ) f = -1; for (x = 0; c >= 0 && c <= 9 ; x = (x << 3) + (x << 1) + (c & 15), c = getchar()) ; x *= f; } long long ksm(int x, int y) { long long res = 1; while (y) { if (y & 1) res = res * x % mod; y >>= 1; x = 1ll * x * x % mod; } return res; } long long f[2 * N][2 * N][2], jc[N * 2]; int main() { int n, l, k; read(n), read(k), read(l); f[0][0][0] = 1; for (int i = 0; i <= 2 * n; i++) for (int j = 0; j <= i; j++) for (int o = 0; o <= 1; o++) { f[i + 1][j + 1][o] = (f[i + 1][j + 1][o] + f[i][j][o]) % mod; if (o == 0 && j >= k) f[i + 1][j][1] = (f[i + 1][j][1] + f[i][j][o]) % mod; if (j) f[i + 1][j - 1][o] = (f[i + 1][j - 1][o] + f[i][j][o] * j) % mod; } jc[0] = 1; for (int i = 1; i <= 2 * n + 1; i++) jc[i] = jc[i - 1] * i % mod; long long ans = f[2 * n + 1][0][1] * ksm(2, n) % mod * jc[n] % mod * ksm(jc[2 * n + 1], mod - 2) % mod * l % mod; printf( %lld n , ans); return 0; } |
module multiboot (
input wire clk_icap,
input wire REBOOT
);
reg [23:0] spi_addr = 24'h058000; // default: SPI address of second core as defined by the SPI memory map
reg [4:0] q = 5'b00000;
reg reboot_ff = 1'b0;
always @(posedge clk_icap) begin
q[0] <= REBOOT;
q[1] <= q[0];
q[2] <= q[1];
q[3] <= q[2];
q[4] <= q[3];
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
end
multiboot_spartan6 hacer_multiboot (
.CLK(clk_icap),
.MBT_RESET(1'b0),
.MBT_REBOOT(reboot_ff),
.spi_addr(spi_addr)
);
endmodule
module multiboot_spartan6 (
input wire CLK,
input wire MBT_RESET,
input wire MBT_REBOOT,
input wire [23:0] spi_addr
);
reg [15:0] icap_din;
reg icap_ce;
reg icap_wr;
reg [15:0] ff_icap_din_reversed;
reg ff_icap_ce;
reg ff_icap_wr;
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
.CE (ff_icap_ce), // Clock enable input
.CLK (CLK), // Clock input
.I (ff_icap_din_reversed), // 16-bit data input
.WRITE (ff_icap_wr) // Write input
);
// -------------------------------------------------
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
// -------------------------------------------------
parameter IDLE = 0,
SYNC_H = 1,
SYNC_L = 2,
CWD_H = 3,
CWD_L = 4,
GEN1_H = 5,
GEN1_L = 6,
GEN2_H = 7,
GEN2_L = 8,
GEN3_H = 9,
GEN3_L = 10,
GEN4_H = 11,
GEN4_L = 12,
GEN5_H = 13,
GEN5_L = 14,
NUL_H = 15,
NUL_L = 16,
MOD_H = 17,
MOD_L = 18,
HCO_H = 19,
HCO_L = 20,
RBT_H = 21,
RBT_L = 22,
NOOP_0 = 23,
NOOP_1 = 24,
NOOP_2 = 25,
NOOP_3 = 26;
reg [4:0] state;
reg [4:0] next_state;
always @*
begin: COMB
case (state)
IDLE:
begin
if (MBT_REBOOT)
begin
next_state = SYNC_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hAA99; // Sync word 1
end
else
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'hFFFF; // Null
end
end
SYNC_H:
begin
next_state = SYNC_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h5566; // Sync word 2
end
SYNC_L:
begin
next_state = NUL_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
NUL_H:
begin
// next_state = NUL_L;
next_state = GEN1_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
end
//Q
GEN1_H:
begin
next_state = GEN1_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
end
GEN1_L:
begin
next_state = GEN2_H;
icap_ce = 0;
icap_wr = 0;
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
end
GEN2_H:
begin
next_state = GEN2_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3281; // Escritura a reg GENERAL_2
end
GEN2_L:
begin
next_state = MOD_H;
icap_ce = 0;
icap_wr = 0;
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
end
/////// Registro MODE (para carga a 4x tras reboot)
MOD_H:
begin
next_state = MOD_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3301; // Escritura a reg MODE
end
MOD_L:
begin
next_state = NUL_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
end
/////
NUL_L:
begin
next_state = RBT_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
RBT_H:
begin
next_state = RBT_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h000E; // REBOOT Command 0x000E
end
//--------------------
RBT_L:
begin
next_state = NOOP_0;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_0:
begin
next_state = NOOP_1;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_1:
begin
next_state = NOOP_2;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_2:
begin
next_state = NOOP_3;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
//--------------------
NOOP_3:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // NULL value
end
default:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // 16'h1111"
end
endcase
end
always @(posedge CLK)
begin: SEQ
if (MBT_RESET)
state <= IDLE;
else
state <= next_state;
end
always @(posedge CLK)
begin: ICAP_FF
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
ff_icap_din_reversed[1] <= icap_din[6];
ff_icap_din_reversed[2] <= icap_din[5];
ff_icap_din_reversed[3] <= icap_din[4];
ff_icap_din_reversed[4] <= icap_din[3];
ff_icap_din_reversed[5] <= icap_din[2];
ff_icap_din_reversed[6] <= icap_din[1];
ff_icap_din_reversed[7] <= icap_din[0];
ff_icap_din_reversed[8] <= icap_din[15];
ff_icap_din_reversed[9] <= icap_din[14];
ff_icap_din_reversed[10] <= icap_din[13];
ff_icap_din_reversed[11] <= icap_din[12];
ff_icap_din_reversed[12] <= icap_din[11];
ff_icap_din_reversed[13] <= icap_din[10];
ff_icap_din_reversed[14] <= icap_din[9];
ff_icap_din_reversed[15] <= icap_din[8];
ff_icap_ce <= icap_ce;
ff_icap_wr <= icap_wr;
end
endmodule
|
module x_vector_cache_tb;
parameter SUB_WIDTH = 8;
parameter LOG2_SUB_WIDTH = log2(SUB_WIDTH - 1);
reg clk;
reg rst;
reg [31:0] col;
reg push_col;
reg [47:0] start_address;
wire req_mem;
wire [47:0] req_mem_addr;
reg rsp_mem_push;
reg [63:0] rsp_mem_q;
wire push_x;
wire [63:0] x_val;
reg stall;
wire almost_full;
x_vector_cache #(SUB_WIDTH) dut(clk, rst, col, push_col, start_address, req_mem, req_mem_addr, rsp_mem_push, rsp_mem_q, push_x, x_val, stall, almost_full);
initial begin
#1000 $display("watchdog timer reached");
$finish;
end
initial begin
clk = 0;
forever #5 clk = !clk;
end
initial begin
stall = 0;
rst = 1;
col = 0;
push_col = 0;
start_address = 0;
#100 rst = 0;
#100 push_col = 1;
#10 push_col = 0;
#10 push_col = 1;
col = 1;
#10 push_col = 1;
col = 0;
#10 push_col = 0;
end
reg [63:0] memory [0:9];
integer i;
initial begin
for(i = 0; i < 10; i = i + 1) begin
memory[i] = i;
end
end
always @(posedge clk) begin
rsp_mem_push <= req_mem;
rsp_mem_q <= memory[req_mem_addr / 8];
if(req_mem)
$display("memory request");
end
always @(posedge clk) begin
if(push_x)
$display("woot: %d", x_val);
end
`include "common.vh"
endmodule
|
#include <bits/stdc++.h> using namespace std; string S; int MOD; int len; long long dp[1 << 18][100]; int cnt[1 << 18]; int bits[1 << 18]; int DMASKS[1 << 18]; int powers[20]; int orig; long long solve(int mask, int mod) { if (mask == 0) { return mod == 0; } long long &ret = dp[mask][mod]; if (ret != -1) return ret; ret = 0; int pos = len - cnt[mask]; int dMask = pos == 0; int m = mask; while (m > 0) { int b = m & -m; if (!(dMask & (1 << (S[bits[b]] - 0 )))) { ret += solve(mask ^ b, (mod + powers[len - pos - 1] * (S[bits[b]] - 0 )) % MOD); dMask |= 1 << (S[bits[b]] - 0 ); } m -= b; } return ret; } int main() { memset(dp, -1, sizeof dp); cin >> S >> MOD; len = S.size(); powers[0] = 1; powers[0] %= MOD; for (int i = 1; i < 20; i++) { powers[i] = powers[i - 1] * 10; powers[i] %= MOD; } for (int i = 0; i < 18; i++) { bits[1 << i] = i; } for (int i = 0, to = 1 << 18; i < to; i++) { cnt[i] = __builtin_popcount(i); } orig = (1 << len) - 1; cout << solve(orig, 0) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using ii = tuple<long long, long long>; const long long N = 1e6 + 7, inf = 1e9 + 42; long long binpow(long long a, long long b) { if (b == 0) return 1; long long res = binpow(a, b / 2); if (b % 2) return (res * res * a) % 1000000007; else return (res * res) % 1000000007; } bool compare(pair<long long, long long> a, pair<long long, long long> b) { return (a.first - a.second > b.first - b.second); } long long n; vector<long long> prime_factors; signed main() { puts( Odd ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 50005, M = 50005; int mo; struct matrix { int a[2][2]; int *operator[](const int i) { return a[i]; } const int *operator[](const int i) const { return a[i]; } friend matrix operator*(const matrix &a, const matrix &b) { matrix c; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { long long s = 0; for (int k = 0; k < 2; k++) s += (long long)a[i][k] * b[k][j]; c[i][j] = s % mo; } return c; } }; int n, m; long long k; int s[N]; pair<long long, int> a[M]; inline int gs(long long i) { pair<long long, int> *it = lower_bound(a, a + m, pair<long long, int>(i, 0)); if (it < a + m && it->first == i) return it->second; return s[i % n]; } matrix t[N * 4]; void build(int cur, int beg, int end) { if (end - beg == 1) { t[cur][1][0] = 1 % mo; t[cur][0][1] = s[beg]; t[cur][1][1] = s[(beg + 1) % n]; return; } int mid = beg + end >> 1; build(cur << 1, beg, mid); build(cur << 1 | 1, mid, end); t[cur] = t[cur << 1] * t[cur << 1 | 1]; } matrix ans; void query(int cur, int beg, int end, int L, int R) { if (end <= L || beg >= R) return; if (beg >= L && end <= R) { ans = ans * t[cur]; return; } int mid = beg + end >> 1; query(cur << 1, beg, mid, L, R); query(cur << 1 | 1, mid, end, L, R); } long long p[M * 2], *top = p; long long q[M * 2], *toq = q; void power(long long s) { matrix a = t[1]; for (; s; s >>= 1, a = a * a) if (s & 1) ans = ans * a; } int main() { scanf( %I64d%d , &k, &mo); scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &s[i]), s[i] %= mo; scanf( %d , &m); for (int i = 0; i < m; i++) scanf( %I64d%d , &a[i].first, &a[i].second), a[i].second %= mo; sort(a, a + m); for (int i = 0; i < m; i++) p[i << 1] = a[i].first - 1, p[i << 1 | 1] = a[i].first; p[m * 2] = k; sort(p, p + m * 2 + 1); top = unique(p, p + m * 2 + 1); for (int i = 0; i < top - p; i++) q[i] = p[i] / n; toq = unique(q, q + (top - p)); build(1, 0, n); ans[0][0] = ans[1][1] = 1 % mo; ans[0][1] = ans[1][0] = 0; long long block = 0; for (int i = 0, j = 0; i < toq - q; i++) { power(q[i] - block); block = q[i]; long long id = block * n; for (; j < top - p && p[j] / n == block; j++) { query(1, 0, n, id % n, p[j] % n); id = p[j]; if (id == k) { printf( %d n , ans[1][0]); return 0; } matrix tmp; tmp[0][0] = 0; tmp[1][0] = 1 % mo; tmp[0][1] = gs(id); tmp[1][1] = gs(id + 1); ans = ans * tmp; id++; } query(1, 0, n, id - block * n, n); id = (++block) * n; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> const double eps = 1e-8; const int mod = 8 * 9 * 7 * 11 * 13 * 5; const int maxn = 205; const double pi = acos(-1.0); const int INF = 0x7f7f7f7f; const double inf = 1e50; template <class T> inline T minx(T a, T b) { return (a == -1 || b < a) ? b : a; } template <class T> inline T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <class T> inline T lcm(T a, T b) { return a * (b / gcd(a, b)); } template <class T> inline T getbit(T n) { return n ? (1 + getbit(n & (n - 1))) : 0; } template <class T> inline T lowbit(T n) { return n & (-n); } using namespace std; long long dp[mod + 2]; long long a, b, k, c, y = 0, l, i, t; int main() { cin >> a >> b >> k; while (a > b) { l = 1; for (i = 2; i <= k; i++) { t = a % i; if ((t > l) && (a - t) >= b) l = t; } y++, a -= l; if (dp[a % mod]) { c = y - dp[a % mod]; y += c * ((a - b) / mod); a -= ((a - b) / mod) * mod; } dp[a % mod] = y; } cout << y << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 Rand(time(0)); const int maxn = 1e5 + 5; const long long maxc = 1e9 + 7; int n, m, d, a[maxn]; long long sum[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> d >> m; for (int i = (1); i <= (n); ++i) cin >> a[i]; sort(a + 1, a + n + 1); for (int i = (1); i <= (n); ++i) sum[i] = sum[i - 1] + a[i]; if (a[n] <= m) return cout << sum[n], 0; int id = upper_bound(a + 1, a + n + 1, m) - a; long long res = a[n] + sum[id - 1]; long long ans = res; for (int i = (n - 1); i >= (id); --i) { if (1LL * (n - i) * d > n) continue; int r = (n - i) * d; if (r - (i - id) < id) { ans = max(ans, res + sum[n - 1] - sum[i - 1] - sum[max(0, r - (i - id))]); } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, d[333][333], k; int main() { cin >> n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cin >> d[i][j]; } } cin >> k; while (k--) { int a = 0, b = 0, c = 0; cin >> a >> b >> c; d[a][b] = min(d[a][b], c); d[b][a] = min(d[b][a], c); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { d[i][j] = min(d[i][j], d[a][j] + d[i][b] + d[a][b]); d[i][j] = min(d[i][j], d[b][j] + d[i][a] + d[b][a]); } } long long sum = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { sum += d[i][j]; } } cout << sum / 2 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); int n, h, a[100005]; pair<int, int> A[100005]; void solve() { sort(A, A + n); for (int i = (0); i < (n); i++) a[i] = A[i].first; int res = a[n - 1] + a[n - 2] - a[0] - a[1], ind = n - 1; if (n >= 3) { int v = max(a[n - 1] + a[n - 2], a[n - 1] + a[0] + h) - min(a[1] + a[2], a[1] + a[0] + h); if (res > v) { res = v; ind = 0; } v = max(a[n - 3] + a[n - 2], a[n - 1] + a[n - 2] + h) - (a[0] + a[1]); if (res > v) { res = v; ind = n - 2; } } for (int i = 1; i + 2 < n; i++) { int v = max(a[n - 1] + a[n - 2], a[n - 1] + a[i] + h) - (a[0] + a[1]); if (res > v) { res = v; ind = i; } } cout << res << endl; set<int> L; for (int i = (0); i < (ind + 1); i++) L.insert(A[i].second); for (int i = (0); i < (n); i++) { printf( %d , (L.find(i) == L.end()) + 1); } cout << endl; } int main() { while (cin >> n >> h) { for (int i = (0); i < (n); i++) { scanf( %d , &A[i].first); A[i].second = i; } solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long a, b, x, y, n; cin >> a >> b >> x >> y >> n; long long p = a - x, q = b - y; long long pp = min(p, n), qq = min(q, n); long long aa = a - pp, bb = b - qq; long long tt = a + b - n; if (p + q <= n) cout << x * y << endl; else { if (aa < bb) cout << aa * (tt - aa) << endl; else cout << bb * (tt - bb) << endl; } } return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// d_parallel_FFM_gate_GF12.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_parallel_FFM_gate_GF12
// File Name: d_parallel_FFM_gate_GF12.v
//
// Version: v2.0.2-GF12tB
//
// Description:
// - parallel Finite Field Multiplier (FFM) module
// - 2 polynomial form input, 1 polynomial form output
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v2.0.2
// - minor modification for releasing
//
// * v2.0.1
// - re-factoring
//
// * v2.0.0
// - based on partial multiplication
// - fixed GF
//
// * v1.0.0
// - based on LFSR
// - variable GF by parameter setting
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module d_parallel_FFM_gate_GF12
(
input wire [11: 0] i_poly_form_A, // input term A, polynomial form
input wire [11: 0] i_poly_form_B, // input term B, polynomial form
output wire [11: 0] o_poly_form_result // output term result, polynomial form
);
///////////////////////////////////////////////////////////
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
// //
// ONLY FOR 12 BIT POLYNOMIAL MULTIPLICATION //
// //
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
///////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
// //
// PRIMITIVE POLYNOMIAL //
// P(X) = X^12 + X^7 + X^4 + X^3 + 1 //
// //
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
///////////////////////////////////////////////////////////
wire [11: 6] w_p_A1; // partial term A1
wire [ 5: 0] w_p_A0; // partial term A0
wire [11: 6] w_p_B1; // partial term B1
wire [ 5: 0] w_p_B0; // partial term B0
wire [16: 6] w_p_r_A1_B0; // partial multiplication result A1*B0
wire [10: 0] w_p_r_A0_B0; // partial multiplication result A0*B0
wire [22:12] w_p_r_A1_B1; // partial multiplication result A1*B1
wire [16: 6] w_p_r_A0_B1; // partial multiplication result A0*B1
wire [22: 0] w_p_r_sum; // multiplication result
assign w_p_A1[11: 6] = i_poly_form_A[11: 6];
assign w_p_A0[ 5: 0] = i_poly_form_A[ 5: 0];
assign w_p_B1[11: 6] = i_poly_form_B[11: 6];
assign w_p_B0[ 5: 0] = i_poly_form_B[ 5: 0];
// multipliers for partial multiplication
d_partial_FFM_gate_6b p_mul_A1_B0 (
.i_a(w_p_A1[11: 6]),
.i_b(w_p_B0[ 5: 0]),
.o_r(w_p_r_A1_B0[16: 6]));
d_partial_FFM_gate_6b p_mul_A0_B0 (
.i_a(w_p_A0[ 5: 0]),
.i_b(w_p_B0[ 5: 0]),
.o_r(w_p_r_A0_B0[10: 0]));
d_partial_FFM_gate_6b p_mul_A1_B1 (
.i_a(w_p_A1[11: 6]),
.i_b(w_p_B1[11: 6]),
.o_r(w_p_r_A1_B1[22:12]));
d_partial_FFM_gate_6b p_mul_A0_B1 (
.i_a(w_p_A0[ 5: 0]),
.i_b(w_p_B1[11: 6]),
.o_r(w_p_r_A0_B1[16: 6]));
// sum partial results
assign w_p_r_sum[22:17] = w_p_r_A1_B1[22:17];
assign w_p_r_sum[16:12] = w_p_r_A1_B1[16:12] ^ w_p_r_A0_B1[16:12] ^ w_p_r_A1_B0[16:12];
assign w_p_r_sum[11] = w_p_r_A0_B1[11] ^ w_p_r_A1_B0[11];
assign w_p_r_sum[10: 6] = w_p_r_A0_B1[10: 6] ^ w_p_r_A1_B0[10: 6] ^ w_p_r_A0_B0[10: 6];
assign w_p_r_sum[ 5: 0] = w_p_r_A0_B0[ 5: 0];
// reduce high order terms
assign o_poly_form_result[11] = w_p_r_sum[11] ^ w_p_r_sum[16] ^ w_p_r_sum[19] ^ w_p_r_sum[20] ^ w_p_r_sum[21];
assign o_poly_form_result[10] = w_p_r_sum[10] ^ w_p_r_sum[15] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[20] ^ w_p_r_sum[22];
assign o_poly_form_result[ 9] = w_p_r_sum[ 9] ^ w_p_r_sum[14] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[21];
assign o_poly_form_result[ 8] = w_p_r_sum[ 8] ^ w_p_r_sum[13] ^ w_p_r_sum[16] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[20];
assign o_poly_form_result[ 7] = w_p_r_sum[ 7] ^ w_p_r_sum[12] ^ w_p_r_sum[15] ^ w_p_r_sum[16] ^ w_p_r_sum[17] ^ w_p_r_sum[19] ^ w_p_r_sum[22];
assign o_poly_form_result[ 6] = w_p_r_sum[ 6] ^ w_p_r_sum[14] ^ w_p_r_sum[15] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[20] ^ w_p_r_sum[22];
assign o_poly_form_result[ 5] = w_p_r_sum[ 5] ^ w_p_r_sum[13] ^ w_p_r_sum[14] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
assign o_poly_form_result[ 4] = w_p_r_sum[ 4] ^ w_p_r_sum[12] ^ w_p_r_sum[13] ^ w_p_r_sum[16] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[20] ^ w_p_r_sum[21];
assign o_poly_form_result[ 3] = w_p_r_sum[ 3] ^ w_p_r_sum[12] ^ w_p_r_sum[15] ^ w_p_r_sum[17] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
assign o_poly_form_result[ 2] = w_p_r_sum[ 2] ^ w_p_r_sum[14] ^ w_p_r_sum[19] ^ w_p_r_sum[22];
assign o_poly_form_result[ 1] = w_p_r_sum[ 1] ^ w_p_r_sum[13] ^ w_p_r_sum[18] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
assign o_poly_form_result[ 0] = w_p_r_sum[ 0] ^ w_p_r_sum[12] ^ w_p_r_sum[17] ^ w_p_r_sum[20] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [32:0] in = crc[32:0];
logic bank_rd_vec_m3;
always_ff @(posedge clk) bank_rd_vec_m3 <= crc[33];
logic [3:0][31:0] data_i;
wire [3:0] out;
for (genvar i = 0; i < 4; ++i) begin
always_ff @(posedge clk) data_i[i] <= crc[63:32];
ecc_check_pipe u_bank_data_ecc_check(
.clk (clk),
.bank_rd_m3 (bank_rd_vec_m3),
.data_i ({1'b0, data_i[i]}),
.ecc_err_o (out[i])
);
end
// Aggregate outputs into a single result vector
wire [63:0] result = {60'b0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha2601675a6ae4972
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module ecc_check_pipe (
input logic clk,
input logic bank_rd_m3,
input logic [32:0] data_i,
output logic ecc_err_o
);
logic [3:0] check_group_6_0;
logic check_group_6_0_q;
always_comb check_group_6_0 = {data_i[0], data_i[2], data_i[4], data_i[7] };
always_ff @(posedge clk) if (bank_rd_m3) check_group_6_0_q <=^check_group_6_0;
assign ecc_err_o = check_group_6_0_q;
endmodule
|
End of preview. Expand
in Dataset Viewer.
Dataset Card for Opencores
In the process of continual pre-training, we utilized the publicly available VGen dataset. VGen aggregates Verilog repositories from GitHub, systematically filters out duplicates and excessively large files, and retains only those files containing \texttt{module} and \texttt{endmodule} statements.
We also incorporated the CodeSearchNet dataset \cite{codesearchnet}, which contains approximately 40MB function codes and their documentation.
Dataset Features
- text (string): The pretraining corpus: nature language and Verilog/C code.
Loading the dataset
from datasets import load_dataset
ds = load_dataset("LLM-EDA/vgen_cpp", split="train")
print(ds[0])
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