document: Bit-serial AB/sup 2 / multiplier using modified inner product This paper presents a new multiplication algorithm and , based on this algorithm , proposes a hardware architecture , called modified inner-product multiplier -LRB- MIPM -RRB- , which computes AB/sup 2 / multiplication based on a linear feedback shift register -LRB- LFSR -RRB- . The algorithm is based on the property of the irreducible all one polynomial -LRB- AOP -RRB- over the finite field GF -LRB- 2/sup m / -RRB- . The proposed architecture reduces the time and space complexity for computing AB/sup 2 / . The proposed architecture has a potential application to implementing exponentiation architecture for a public-key cryptosystem
doc_bio_tags: O O O O O O B I I O O O O O B I O O O O O O O O O B I O O O O O O O O O O O O O O O O O O B I I I O O O O O O O O O O O O O B I I I O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O
extractive_keyphrases: modified inner product multiplication algorithm hardware architecture linear feedback shift register irreducible all one polynomial space complexity
abstractive_keyphrases: bit-serial ab/sup 2/ multiplier modified inner-product multiplier time complexity public-key cryptosystem