document: High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic In this paper , we describe parallel dynamic logic -LRB- PDL -RRB- which exhibits high speed without charge sharing problem . PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation . It has less back-bias effect compared to other logic styles , which use stacked transistors . Furthermore , PDL needs no signal ordering or tapering . PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication . Our experimental results on two 32-bit carry lookahead adders using 0.25 - mu m CMOS technology show that PDL with speed-enhanced skewed static -LRB- SSS -RRB- look reduces the delay over clock-delayed -LRB- CD -RRB- - domino by 15 % -27 % and the power-delay product by 20 % -37 %
doc_bio_tags: O O O O B I I O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O
extractive_keyphrases: parallel dynamic logic logic synthesis carry lookahead adders delay stacked transistors
abstractive_keyphrases: high-speed cmos circuits speed-enhanced skewed static logic parallel-connected transistors low-voltage operation power-delay product back-bias effect 32 bit 0.25 micron